5 * AMD Family_10 NB Pstate Initialization
7 * Performs the action described in F3x1F0[NbPstate] as
8 * described in the BKDG.
10 * @xrefitem bom "File Content Label" "Release Content"
12 * @e sub-project: CPU/F10
13 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
17 ******************************************************************************
19 * Copyright (C) 2012 Advanced Micro Devices, Inc.
20 * All rights reserved.
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23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 ******************************************************************************
47 /*----------------------------------------------------------------------------------------
48 * M O D U L E S U S E D
49 *----------------------------------------------------------------------------------------
53 #include "cpuRegisters.h"
54 #include "cpuF10PowerMgmt.h"
55 #include "cpuApicUtilities.h"
56 #include "GeneralServices.h"
57 #include "cpuFamilyTranslation.h"
58 #include "F10PmNbPstateInit.h"
59 #include "OptionMultiSocket.h"
64 #define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE
66 /*----------------------------------------------------------------------------------------
67 * D E F I N I T I O N S A N D M A C R O S
68 *----------------------------------------------------------------------------------------
70 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
71 /*----------------------------------------------------------------------------------------
72 * T Y P E D E F S A N D S T R U C T U R E S
73 *----------------------------------------------------------------------------------------
75 /// Structure used for modifying the P-state
76 /// MSRs on fuse enable CPUs.
78 UINT8 NbVid1; ///< Destination NB VID code
79 UINT8 NbPstate; ///< Status of NbVidUpdateAll
82 /*----------------------------------------------------------------------------------------
83 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
84 *----------------------------------------------------------------------------------------
89 IN VOID *NbPstateParams,
90 IN AMD_CONFIG_PARAMS *StdHeader
93 /*----------------------------------------------------------------------------------------
94 * E X P O R T E D F U N C T I O N S
95 *----------------------------------------------------------------------------------------
98 /*---------------------------------------------------------------------------------------*/
100 * Family 10h core 0 entry point for performing the actions described in the
101 * description of F3x1F0[NbPstate].
103 * If F3x1F0[NbPstate] is non zero, it specifies the highest performance
104 * P-state in which to enable NbDid. Each core must loop through their
105 * P-state MSRs, enabling NbDid and changing NbVid to a lower voltage.
107 * @param[in] FamilySpecificServices The current Family Specific Services.
108 * @param[in] CpuEarlyParamsPtr Service related parameters (unused).
109 * @param[in] StdHeader Config handle for library and services.
114 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
115 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
116 IN AMD_CONFIG_PARAMS *StdHeader
120 UINT32 LocalPciRegister;
123 NB_PSTATE_INIT ApParams;
125 if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) {
126 if (CpuEarlyParamsPtr->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife) {
127 OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
128 GetCurrentCore (&Core, StdHeader);
131 PciAddress.Address.Function = FUNC_3;
132 PciAddress.Address.Register = 0x1F0;
133 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
134 if ((LocalPciRegister & 0x00070000) != 0) {
135 ApParams.NbPstate = (UINT8) ((LocalPciRegister & 0x00070000) >> 16);
136 ASSERT (ApParams.NbPstate < NM_PS_REG);
138 PciAddress.Address.Function = FUNC_4;
139 PciAddress.Address.Register = 0x1F4;
140 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
141 ApParams.NbVid1 = (UINT8) ((LocalPciRegister & 0x00003F80) >> 7);
143 TaskPtr.FuncAddress.PfApTaskI = PmNbPstateInitCore;
144 TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_PSTATE_INIT);
145 TaskPtr.DataTransfer.DataPtr = &ApParams;
146 TaskPtr.DataTransfer.DataTransferFlags = 0;
147 TaskPtr.ExeFlags = WAIT_FOR_CORE;
148 ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
156 /*---------------------------------------------------------------------------------------*/
158 * Support routine for F10PmNbPstateInit.
160 * This function modifies NbVid and NbDid on each core.
162 * @param[in] NbPstateParams Appropriate NbVid1 and NbPstate as determined by core 0.
163 * @param[in] StdHeader Config handle for library and services.
169 IN VOID *NbPstateParams,
170 IN AMD_CONFIG_PARAMS *StdHeader
174 UINT64 LocalMsrRegister;
176 for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
177 LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
178 if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
179 ((PSTATE_MSR *) &LocalMsrRegister)->NbDid = 1;
180 ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
181 LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader);