5 * AMD Family_10 NB COF VID Initialization
7 * Performs the "BIOS Northbridge COF and VID Configuration" as
8 * described in the BKDG.
10 * @xrefitem bom "File Content Label" "Release Content"
12 * @e sub-project: CPU/F10
13 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
17 ******************************************************************************
19 * Copyright (C) 2012 Advanced Micro Devices, Inc.
20 * All rights reserved.
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23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
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33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 ******************************************************************************
47 /*----------------------------------------------------------------------------------------
48 * M O D U L E S U S E D
49 *----------------------------------------------------------------------------------------
53 #include "cpuRegisters.h"
54 #include "cpuF10PowerMgmt.h"
55 #include "cpuApicUtilities.h"
56 #include "OptionMultiSocket.h"
57 #include "cpuServices.h"
58 #include "GeneralServices.h"
59 #include "cpuFamilyTranslation.h"
60 #include "cpuF10Utilities.h"
61 #include "F10PmNbCofVidInit.h"
66 #define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE
68 /*----------------------------------------------------------------------------------------
69 * D E F I N I T I O N S A N D M A C R O S
70 *----------------------------------------------------------------------------------------
73 /*----------------------------------------------------------------------------------------
74 * T Y P E D E F S A N D S T R U C T U R E S
75 *----------------------------------------------------------------------------------------
77 /// Structure used for performing the steps outlined in
78 /// the NB COFVID configuration sequence
80 UINT8 NewNbVid; ///< Destination NB VID code
81 BOOLEAN NbVidUpdateAll; ///< Status of NbVidUpdateAll
82 } NB_COF_VID_INIT_WARM;
84 /*----------------------------------------------------------------------------------------
85 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
86 *----------------------------------------------------------------------------------------
90 PmNbCofVidInitP0P1Core (
92 IN AMD_CONFIG_PARAMS *StdHeader
97 PmNbCofVidInitWarmCore (
98 IN VOID *FunctionData,
99 IN AMD_CONFIG_PARAMS *StdHeader
102 /*----------------------------------------------------------------------------------------
103 * E X P O R T E D F U N C T I O N S
104 *----------------------------------------------------------------------------------------
106 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
108 /*---------------------------------------------------------------------------------------*/
110 * Family 10h core 0 entry point for performing the "Northbridge COF and
111 * VID Configuration" algorithm.
113 * The steps are as follows:
114 * 1. Determine if the algorithm is necessary by checking if all NB FIDs
115 * match in the coherent fabric. If so, check to see if NbCofVidUpdate
116 * is zero for all CPUs. If that is also true, no further steps are
117 * necessary. If not + cold reset, proceed to step 2. If not + warm
118 * reset, proceed to step 8.
119 * 2. Determine NewNbVid & NewNbFid.
120 * 3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
121 * 4. Copy NewNbVid to P0 NbVid on all local cores.
122 * 5. Transition to P1 on all local cores.
123 * 6. Transition to P0 on local core 0 only.
124 * 7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
125 * 8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
126 * on all local cores.
127 * 9. Transition to Startup Pstate on all local cores.
129 * @param[in] FamilySpecificServices The current Family Specific Services.
130 * @param[in] CpuEarlyParamsPtr Service related parameters (unused).
131 * @param[in] StdHeader Config handle for library and services.
136 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
137 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
138 IN AMD_CONFIG_PARAMS *StdHeader
141 BOOLEAN PerformNbCofVidCfg;
143 BOOLEAN SystemNbCofsMatch;
152 UINT32 FrequencyDivisor;
153 WARM_RESET_REQUEST Request;
156 NB_COF_VID_INIT_WARM FunctionData;
158 PerformNbCofVidCfg = TRUE;
159 OptionMultiSocketConfiguration.GetSystemNbPstateSettings ((UINT32) 0, &CpuEarlyParamsPtr->PlatformConfig, &SystemNbCof, &FrequencyDivisor, &SystemNbCofsMatch, &NotUsed, StdHeader);
160 if (SystemNbCofsMatch) {
161 if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
162 PerformNbCofVidCfg = FALSE;
165 if (PerformNbCofVidCfg) {
166 OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
168 GetCurrentCore (&Core, StdHeader);
172 FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
173 &CpuEarlyParamsPtr->PlatformConfig,
180 ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
181 NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
182 ASSERT (NewNbVid < 0x80);
184 if (!(IsWarmReset (StdHeader))) {
186 // determine NewNbFid
187 NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
189 TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
190 TaskPtr.DataTransfer.DataSizeInDwords = 1;
191 TaskPtr.DataTransfer.DataPtr = &NewNbVid;
192 TaskPtr.DataTransfer.DataTransferFlags = 0;
193 TaskPtr.ExeFlags = 0;
194 ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
196 // Transition core 0 to P0 and wait for change to complete
197 FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
199 PciAddress.Address.Register = CPTC0_REG;
200 AndMask = 0xFFFFFFFF;
201 ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
203 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
204 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
205 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
207 // warm reset request
208 GetWarmResetFlag (StdHeader, &Request);
209 Request.RequestBit = TRUE;
210 Request.StateBits = Request.PostStage - 1;
211 SetWarmResetFlag (StdHeader, &Request);
215 FunctionData.NewNbVid = NewNbVid;
216 FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
218 TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
219 TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
220 TaskPtr.DataTransfer.DataPtr = &FunctionData;
221 TaskPtr.DataTransfer.DataTransferFlags = 0;
222 TaskPtr.ExeFlags = WAIT_FOR_CORE;
223 ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
225 } // skip whole algorithm
229 /*---------------------------------------------------------------------------------------*/
231 * Cold reset support routine for F10PmNbCofVidInit.
233 * This function implements steps 3, 4, & 5 on each core.
235 * @param[in] NewNbVid NewNbVid determined by core 0 in step 2.
236 * @param[in] StdHeader Config handle for library and services.
241 PmNbCofVidInitP0P1Core (
243 IN AMD_CONFIG_PARAMS *StdHeader
246 UINT8 NumBoostStates;
248 UINT64 LocalMsrRegister;
249 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
251 NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader);
252 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
253 LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
254 MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &LocalMsrRegister)->StartupPstate) + PS_REG_BASE);
255 LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
256 LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1 + NumBoostStates), &LocalMsrRegister, StdHeader);
257 ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = *(UINT8 *) NewNbVid;
258 LibAmdMsrWrite (PS_REG_BASE + NumBoostStates, &LocalMsrRegister, StdHeader);
259 FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
263 /*---------------------------------------------------------------------------------------*/
265 * Warm reset support routine for F10PmNbCofVidInit.
267 * This function implements steps 8 & 9 on each core.
269 * @param[in] FunctionData Contains NewNbVid determined by core 0 in step
270 * 2, and NbVidUpdateAll.
271 * @param[in] StdHeader Config handle for library and services.
276 PmNbCofVidInitWarmCore (
277 IN VOID *FunctionData,
278 IN AMD_CONFIG_PARAMS *StdHeader
282 UINT64 LocalMsrRegister;
283 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
285 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
286 for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
287 LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
288 if (((PSTATE_MSR *) &LocalMsrRegister)->IddValue != 0) {
289 if ((((PSTATE_MSR *) &LocalMsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
290 ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
291 LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader);