5 * AMD Family_10 Asymmetric Boost Initialization
7 * Performs the "BIOS Configuration for Asymmetric Boost" as
8 * described in the BKDG.
10 * @xrefitem bom "File Content Label" "Release Content"
12 * @e sub-project: CPU/F10
13 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
17 ******************************************************************************
19 * Copyright (C) 2012 Advanced Micro Devices, Inc.
20 * All rights reserved.
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23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 ******************************************************************************
47 /*----------------------------------------------------------------------------------------
48 * M O D U L E S U S E D
49 *----------------------------------------------------------------------------------------
53 #include "cpuRegisters.h"
54 #include "cpuApicUtilities.h"
55 #include "cpuServices.h"
56 #include "GeneralServices.h"
57 #include "cpuFamilyTranslation.h"
58 #include "cpuF10PowerMgmt.h"
59 #include "F10PmAsymBoostInit.h"
60 #include "OptionMultiSocket.h"
65 #define FILECODE PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE
67 /*----------------------------------------------------------------------------------------
68 * D E F I N I T I O N S A N D M A C R O S
69 *----------------------------------------------------------------------------------------
71 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
72 /*----------------------------------------------------------------------------------------
73 * T Y P E D E F S A N D S T R U C T U R E S
74 *----------------------------------------------------------------------------------------
77 /*----------------------------------------------------------------------------------------
78 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
79 *----------------------------------------------------------------------------------------
84 IN VOID *AsymBoostRegister,
85 IN AMD_CONFIG_PARAMS *StdHeader
88 /*----------------------------------------------------------------------------------------
89 * E X P O R T E D F U N C T I O N S
90 *----------------------------------------------------------------------------------------
93 /*---------------------------------------------------------------------------------------*/
95 * Family 10h core 0 entry point for performing the "Asymmetric Boost
96 * Configuration" algorithm.
98 * The algorithm is as follows:
99 * // Determine whether the processor support boost
100 * if (CPUID CPUID Fn8000_0007[CPB]==1)&& CPUID Fn8000_0008[NC]==5) {
101 * Core0 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore0]
102 * Core1 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore1]
103 * Core2 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore2]
104 * Core3 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore3]
105 * Core4 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore4]
106 * Core5 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore5]
109 * @param[in] FamilySpecificServices The current Family Specific Services.
110 * @param[in] CpuEarlyParamsPtr Service related parameters (unused).
111 * @param[in] StdHeader Config handle for library and services.
116 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
117 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
118 IN AMD_CONFIG_PARAMS *StdHeader
122 UINT32 LocalPciRegister;
124 CPUID_DATA CpuidData;
126 // Check if CPB is supported. if yes, skip boosted p-state.
127 LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
128 if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
129 LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuidData, StdHeader);
130 if ((CpuidData.ECX_Reg & 0x000000FF) == 5) {
131 OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
132 // Read F3x10C [Boost Offset]
133 PciAddress.AddressValue = F3x10C_ADDR;
134 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
136 TaskPtr.FuncAddress.PfApTaskI = SetAsymBoost;
137 TaskPtr.ExeFlags = WAIT_FOR_CORE;
138 TaskPtr.DataTransfer.DataTransferFlags = 0;
139 TaskPtr.DataTransfer.DataSizeInDwords = 1;
140 TaskPtr.DataTransfer.DataPtr = &LocalPciRegister;
141 ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
146 /*---------------------------------------------------------------------------------------*/
148 * Set Asymmetric Boost.
150 * This function set Asymmetric Boost.
152 * @param[in] AsymBoostRegister Contains the value of Asymmetric Boost register
153 * @param[in] StdHeader Config handle for library and services
159 IN VOID *AsymBoostRegister,
160 IN AMD_CONFIG_PARAMS *StdHeader
167 AGESA_STATUS IgnoredSts;
169 IdentifyCore (StdHeader, &Ignored, &Ignored, &Core, &IgnoredSts);
170 ControlByte = (UINT8) ((Core & 0xFF) * 2);
171 LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader);
173 ((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3);
174 LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);