src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_10 PCI tables from Multi-Link BKDG paragraph recommended settings.
   6  *
   7  * @xrefitem bom "File Content Label" "Release Content"
   8  * @e project:      AGESA
   9  * @e sub-project:  CPU/FAMILY/0x10
  10  * @e \$Revision: 59564 $   @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $
  11  *
  12  */
  13 /*
  14  ******************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  ******************************************************************************
  42  */
  43
  44 /*----------------------------------------------------------------------------------------
  45  *                             M O D U L E S    U S E D
  46  *----------------------------------------------------------------------------------------
  47  */
  48 #include "AGESA.h"
  49 #include "Ids.h"
  50 #include "cpuRegisters.h"
  51 #include "Table.h"
  52 #include "Filecode.h"
  53 CODE_GROUP (G1_PEICC)
  54 RDATA_GROUP (G2_PEI)
  55
  56 #define FILECODE PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE
  57
  58 /*----------------------------------------------------------------------------------------
  59  *                   D E F I N I T I O N S    A N D    M A C R O S
  60  *----------------------------------------------------------------------------------------
  61  */
  62
  63 /*----------------------------------------------------------------------------------------
  64  *                  T Y P E D E F S     A N D     S T R U C T U R E S
  65  *----------------------------------------------------------------------------------------
  66  */
  67
  68 /*----------------------------------------------------------------------------------------
  69  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
  70  *----------------------------------------------------------------------------------------
  71  */
  72
  73 /*----------------------------------------------------------------------------------------
  74  *                          E X P O R T E D    F U N C T I O N S
  75  *----------------------------------------------------------------------------------------
  76  */
  77
  78 //  P C I    T a b l e s
  79 // ----------------------
  80
  81 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10MultiLinkPciRegisters[] =
  82 {
  83   // Function 0
  84
  85 // F0x68 - Link Transaction Control
  86 // bit[14:13], BufPriRel = 02h
  87   {
  88     PciRegister,
  89     {
  90       AMD_FAMILY_10,                        // CpuFamily
  91       (AMD_F10_ALL & ~AMD_F10_Dx),          // CpuRevision  rev C or less.
  92     },
  93     {AMD_PF_MULTI_LINK},                     // platformFeatures
  94     {{
  95       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
  96       0x00004000,                           // regData
  97       0x00006000,                           // regMask
  98     }}
  99   },
 100   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 101   // 27:25 FreeData: 2
 102   // 24:20 FreeCmd: 8
 103   // 19:18 RspData: 2
 104   // 17:16 NpReqData: 2
 105   // 15:12 ProbeCmd: 9
 106   // 11:8 RspCmd: 9
 107   // 7:5 PReq: 2
 108   // 4:0 NpReqCmd: 4
 109 {
 110     HtHostPciRegister,
 111     {
 112       AMD_FAMILY_10,                      // CpuFamily
 113       AMD_F10_ALL                         // CpuRevision
 114     },
 115     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 116     {{
 117       HT_HOST_FEAT_COHERENT,              // link features
 118       0x10,                               // address
 119       0x048A9944,                         // data
 120       0x0FFFFFFF                          // mask
 121     }}
 122   },
 123   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 124   // 27:25 FreeData: 2
 125   // 24:20 FreeCmd: 8
 126   // 19:18 RspData: 1
 127   // 17:16 NpReqData: 1
 128   // 15:12 ProbeCmd: 0
 129   // 11:8 RspCmd: 2
 130   // 7:5 PReq: 4
 131   // 4:0 NpReqCmd: 18
 132   {
 133     HtHostPciRegister,
 134     {
 135       AMD_FAMILY_10,                      // CpuFamily
 136       AMD_F10_Cx                         // CpuRevision
 137     },
 138     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 139     {{
 140       HT_HOST_FEAT_NONCOHERENT,           // link features
 141       0x10,                               // address
 142       0x04850292,                         // data
 143       0x0FFFFFFF                          // mask
 144     }}
 145   },
 146   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 147   // 27:25 FreeData: 0
 148   // 24:20 FreeCmd: 8
 149   // 19:18 RspData: 1
 150   // 17:16 NpReqData: 1
 151   // 15:12 ProbeCmd: 0
 152   // 11:8 RspCmd: 2
 153   // 7:5 PReq: 6
 154   // 4:0 NpReqCmd: 16
 155   {
 156     HtHostPciRegister,
 157     {
 158       AMD_FAMILY_10,                      // CpuFamily
 159       AMD_F10_Dx                         // CpuRevision
 160     },
 161     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 162     {{
 163       HT_HOST_FEAT_NONCOHERENT,           // link features
 164       0x10,                               // address
 165       0x008502D0,                         // data
 166       0x0FFFFFFF                          // mask
 167     }}
 168   },
 169   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 170   // 27:25 FreeData: 0
 171   // 24:20 FreeCmd: 8
 172   // 19:18 RspData: 3
 173   // 17:16 NpReqData: 2
 174   // 15:12 ProbeCmd: 8
 175   // 11:8 RspCmd: 9
 176   // 7:5 PReq: 2
 177   // 4:0 NpReqCmd: 4
 178   {
 179     HtHostPciRegister,
 180     {
 181       AMD_FAMILY_10,                      // CpuFamily
 182       AMD_F10_ALL                         // CpuRevision
 183     },
 184     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 185     {{
 186       HT_HOST_FEAT_COHERENT,              // link features
 187       0x10,                               // address
 188       0x008E8944,                         // data
 189       0x0FFFFFFF                          // mask
 190     }}
 191   },
 192   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 193   // 27:25 FreeData: 0
 194   // 24:20 FreeCmd: 8
 195   // 19:18 RspData: 1
 196   // 17:16 NpReqData: 1
 197   // 15:12 ProbeCmd: 0
 198   // 11:8 RspCmd: 2
 199   // 7:5 PReq: 6
 200   // 4:0 NpReqCmd: 15
 201   {
 202     HtHostPciRegister,
 203     {
 204       AMD_FAMILY_10,                      // CpuFamily
 205       AMD_F10_ALL                         // CpuRevision
 206     },
 207     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 208     {{
 209       HT_HOST_FEAT_NONCOHERENT,           // link features
 210       0x10,                               // address
 211       0x008502CF,                         // data
 212       0x0FFFFFFF                          // mask
 213     }}
 214   },
 215   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 216   // 28:27 IsocRspData: 0
 217   // 26:25 IsocNpReqData: 0
 218   // 24:22 IsocRspCmd: 0
 219   // 21:19 IsocPReq: 0
 220   // 18:16 IsocNpReqCmd: 0
 221 {
 222     HtHostPciRegister,
 223     {
 224       AMD_FAMILY_10,                      // CpuFamily
 225       AMD_F10_ALL                         // CpuRevision
 226     },
 227     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 228     {{
 229       HT_HOST_FEAT_COHERENT,              // link features
 230       0x14,                               // address
 231       0x00000000,                         // data
 232       0x1FFF0000                          // mask
 233     }}
 234   },
 235   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 236   // 28:27 IsocRspData: 0
 237   // 26:25 IsocNpReqData: 0
 238   // 24:22 IsocRspCmd: 0
 239   // 21:19 IsocPReq: 0
 240   // 18:16 IsocNpReqCmd: 0
 241   {
 242     HtHostPciRegister,
 243     {
 244       AMD_FAMILY_10,                      // CpuFamily
 245       AMD_F10_ALL                         // CpuRevision
 246     },
 247     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 248     {{
 249       HT_HOST_FEAT_NONCOHERENT,           // link features
 250       0x14,                               // address
 251       0x00000000,                         // data
 252       0x1FFF0000                          // mask
 253     }}
 254   },
 255   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 256   // 28:27 IsocRspData: 0
 257   // 26:25 IsocNpReqData: 1
 258   // 24:22 IsocRspCmd: 0
 259   // 21:19 IsocPReq: 0
 260   // 18:16 IsocNpReqCmd: 1
 261   {
 262     HtHostPciRegister,
 263     {
 264       AMD_FAMILY_10,                      // CpuFamily
 265       AMD_F10_ALL                         // CpuRevision
 266     },
 267     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 268     {{
 269       HT_HOST_FEAT_COHERENT,              // link features
 270       0x14,                               // address
 271       0x02010000,                         // data
 272       0x1FFF0000                          // mask
 273     }}
 274   },
 275   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 276   // 28:27 IsocRspData: 0
 277   // 26:25 IsocNpReqData: 0
 278   // 24:22 IsocRspCmd: 0
 279   // 21:19 IsocPReq: 0
 280   // 18:16 IsocNpReqCmd: 1
 281   {
 282     HtHostPciRegister,
 283     {
 284       AMD_FAMILY_10,                      // CpuFamily
 285       AMD_F10_ALL                         // CpuRevision
 286     },
 287     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 288     {{
 289       HT_HOST_FEAT_NONCOHERENT,           // link features
 290       0x14,                               // address
 291       0x00010000,                         // data
 292       0x1FFF0000                          // mask
 293     }}
 294   },
 295
 296 // Function 3 - Misc. Control
 297
 298 // F3x6C - Data Buffer Control
 299 // XBAR buffer settings
 300 // bits[2:0]   UpReqDBC = 2
 301 // bits[5:4]   DnReqDBC = 1
 302 // bits[7:6]   DnRspDBC = 1
 303 // bit[15]     DatBuf24 = 1
 304 // bits[18:16] UpRspDBC = 1
 305 // bits[30:28] IsocRspDBC = 0
 306   {
 307     PciRegister,
 308     {
 309       AMD_FAMILY_10,                      // CpuFamily
 310       AMD_F10_Cx                          // CpuRevision
 311     },
 312     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 313     {{
 314       MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
 315       0x00018052,                           // regData
 316       0x700780F7,                           // regMask
 317     }}
 318   },
 319 // F3x6C - Data Buffer Control
 320 // XBAR buffer settings
 321 // bits[2:0]   UpReqDBC = 2
 322 // bits[5:4]   DnReqDBC = 1
 323 // bits[7:6]   DnRspDBC = 1
 324 // bit[15]     DatBuf24 = 1
 325 // bits[18:16] UpRspDBC = 2
 326 // bits[30:28] IsocRspDBC = 0
 327   {
 328     PciRegister,
 329     {
 330       AMD_FAMILY_10,                      // CpuFamily
 331       AMD_F10_Dx                         // CpuRevision
 332     },
 333     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 334     {{
 335       MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
 336       0x00028052,                           // regData
 337       0x700780F7,                           // regMask
 338     }}
 339   },
 340 // F3x6C - Data Buffer Control
 341 // bits[2:0]   UpReqDBC = 2
 342 // bits[5:4]   DnReqDBC = 1
 343 // bits[7:6]   DnRspDBC = 1
 344 // bit[15]     DatBuf24 = 1
 345 // bits[18:16] UpRspDBC = 1
 346 // bits[30:28] IsocRspDBC = 1
 347   {
 348     PciRegister,
 349     {
 350       AMD_FAMILY_10,                      // CpuFamily
 351       AMD_F10_ALL                         // CpuRevision
 352     },
 353     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 354     {{
 355       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
 356       0x10018052,                           // regData
 357       0x700780F7,                           // regMask
 358     }}
 359   },
 360 // F3x70 - SRI_to_XBAR Command Buffer Count
 361 // bits[2:0]   UpReqCBC = 3
 362 // bits[5:4]   DnReqCBC = 1
 363 // bits[7:6]   DnRspCBC = 1
 364 // bits[10:8]  UpPreqCBC = 1
 365 // bits[14:12] DnPreqCBC = 1
 366 // bits[18:16] UpRspCBC = 4
 367 // bits[22:20] IsocReqCBC = 0
 368 // bits[26:24] IsocPreqCBC = 0
 369 // bits[30:28] IsocRspCBC = 0
 370   {
 371     PciRegister,
 372     {
 373       AMD_FAMILY_10,                      // CpuFamily
 374       AMD_F10_Cx                          // CpuRevision
 375     },
 376     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 377     {{
 378       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
 379       0x00041153,                           // regData
 380       0x777777F7,                           // regMask
 381     }}
 382   },
 383 // F3x70 - SRI_to_XBAR Command Buffer Count
 384 // bits[2:0]   UpReqCBC = 3
 385 // bits[5:4]   DnReqCBC = 1
 386 // bits[7:6]   DnRspCBC = 1
 387 // bits[10:8]  UpPreqCBC = 1
 388 // bits[14:12] DnPreqCBC = 1
 389 // bits[18:16] UpRspCBC = 5
 390 // bits[22:20] IsocReqCBC = 0
 391 // bits[26:24] IsocPreqCBC = 0
 392 // bits[30:28] IsocRspCBC = 0
 393   {
 394     PciRegister,
 395     {
 396       AMD_FAMILY_10,                      // CpuFamily
 397       AMD_F10_Dx                          // CpuRevision
 398     },
 399     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 400     {{
 401       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
 402       0x00051153,                           // regData
 403       0x777777F7,                           // regMask
 404     }}
 405   },
 406 // F3x70 - SRI_to_XBAR Command Buffer Count
 407 // bits[2:0]   UpReqCBC = 3
 408 // bits[5:4]   DnReqCBC = 1
 409 // bits[7:6]   DnRspCBC = 1
 410 // bits[10:8]  UpPreqCBC = 1
 411 // bits[14:12] DnPreqCBC = 1
 412 // bits[18:16] UpRspCBC = 5
 413 // bits[22:20] IsocReqCBC = 1
 414 // bits[26:24] IsocPreqCBC = 0
 415 // bits[30:28] IsocRspCBC = 1
 416   {
 417     PciRegister,
 418     {
 419       AMD_FAMILY_10,                      // CpuFamily
 420       AMD_F10_ALL                         // CpuRevision
 421     },
 422     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 423     {{
 424       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
 425       0x10151153,                           // regData
 426       0x777777F7,                           // regMask
 427     }}
 428   },
 429 // F3x74 - XBAR_to_SRI Command Buffer Count
 430 // bits[2:0]   UpReqCBC = 1
 431 // bits[6:4]   DnReqCBC = 1
 432 // bits[10:8]  UpPreqCBC = 1
 433 // bits[14:12] DnPreqCBC = 1
 434 // bits[19:16] ProbeCBC = 8
 435 // bits[23:20] IsocReqCBC = 0
 436 // bits[26:24] IsocPreqCBC = 0
 437 // bits[30:28] DRReqCBC = 0
 438   {
 439     PciRegister,
 440     {
 441       AMD_FAMILY_10,                      // CpuFamily
 442       AMD_F10_ALL                         // CpuRevision
 443     },
 444     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 445     {{
 446       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 447       0x00081111,                           // regData
 448       0x00FF7777,                           // regMask
 449     }}
 450   },
 451 // F3x74 - XBAR_to_SRI Command Buffer Count
 452 // bits[2:0]   UpReqCBC = 1
 453 // bits[6:4]   DnReqCBC = 1
 454 // bits[10:8]  UpPreqCBC = 1
 455 // bits[14:12] DnPreqCBC = 1
 456 // bits[19:16] ProbeCBC = 8
 457 // bits[23:20] IsocReqCBC = 1
 458 // bits[26:24] IsocPreqCBC = 0
 459 // bits[30:28] DRReqCBC = 0
 460   {
 461     PciRegister,
 462     {
 463       AMD_FAMILY_10,                      // CpuFamily
 464       AMD_F10_ALL                         // CpuRevision
 465     },
 466     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 467     {{
 468       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 469       0x00181111,                           // regData
 470       0x00FF7777,                           // regMask
 471     }}
 472   },
 473 // F3x7C - Free List Buffer Count
 474 // bits[4:0]  Xbar2SriFreeListCBC = 20
 475 // bits[11:8] Sri2XbarFreeXreqCBC = 9
 476 // bits[15:12] Sri2XbarFreeRspCBC = 0
 477 // bits[19:16] Sri2XbarFreeXreqDBC = 9
 478 // bits[22:20] Sri2XbarFreeRspDBC = 0
 479 // bits[30:28] Xbar2SriFreeListCBInc = 0
 480   {
 481     PciRegister,
 482     {
 483       AMD_FAMILY_10,                      // CpuFamily
 484       AMD_F10_Cx                          // CpuRevision
 485     },
 486     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 487     {{
 488       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
 489       0x00090914,                           // regData
 490       0x707FFF1F,                           // regMask
 491     }}
 492   },
 493 // F3x7C - Free List Buffer Count
 494 // bits[4:0]  Xbar2SriFreeListCBC = 24
 495 // bits[11:8] Sri2XbarFreeXreqCBC = 9
 496 // bits[15:12] Sri2XbarFreeRspCBC = 0
 497 // bits[19:16] Sri2XbarFreeXreqDBC = 9
 498 // bits[22:20] Sri2XbarFreeRspDBC = 0
 499 // bits[30:28] Xbar2SriFreeListCBInc = 0
 500   {
 501     CoreCountsPciRegister,
 502     {
 503       AMD_FAMILY_10,                      // CpuFamily
 504       AMD_F10_Dx                          // CpuRevision
 505     },
 506     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 507     {{
 508       PERFORMANCE_PROFILE_ALL,
 509       (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
 510       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
 511       0x00090A18,                           // regData
 512       0x007FFF1F,                           // regMask
 513     }}
 514   },
 515 // F3x7C - Free List Buffer Count
 516 // bits[4:0]  Xbar2SriFreeListCBC = 22
 517 // bits[11:8] Sri2XbarFreeXreqCBC = 9
 518 // bits[15:12] Sri2XbarFreeRspCBC = 0
 519 // bits[19:16] Sri2XbarFreeXreqDBC = 9
 520 // bits[22:20] Sri2XbarFreeRspDBC = 0
 521 // bits[30:28] Xbar2SriFreeListCBInc = 0
 522   {
 523     CoreCountsPciRegister,
 524     {
 525       AMD_FAMILY_10,                      // CpuFamily
 526       AMD_F10_Dx                         // CpuRevision
 527     },
 528     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 529     {{
 530       PERFORMANCE_PROFILE_ALL,
 531       (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
 532       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
 533       0x00090A16,                           // regData
 534       0x707FFF1F,                           // regMask
 535     }}
 536   },
 537 // F3x7C - Free List Buffer Count
 538 // bits[4:0]  Xbar2SriFreeListCBC = 23
 539 // bits[11:8] Sri2XbarFreeXreqCBC = 9
 540 // bits[15:12] Sri2XbarFreeRspCBC = 0
 541 // bits[19:16] Sri2XbarFreeXreqDBC = 9
 542 // bits[22:20] Sri2XbarFreeRspDBC = 0
 543 // bits[30:28] Xbar2SriFreeListCBInc = 0
 544   {
 545     PciRegister,
 546     {
 547       AMD_FAMILY_10,                      // CpuFamily
 548       AMD_F10_Cx                          // CpuRevision
 549     },
 550     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 551     {{
 552       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
 553       0x00090917,                           // regData
 554       0x707FFF1F,                           // regMask
 555     }}
 556   },
 557 // F3x7C - Free List Buffer Count
 558 // bits[4:0]  Xbar2SriFreeListCBC = 23
 559 // bits[11:8] Sri2XbarFreeXreqCBC = 9
 560 // bits[15:12] Sri2XbarFreeRspCBC = 0
 561 // bits[19:16] Sri2XbarFreeXreqDBC = 9
 562 // bits[22:20] Sri2XbarFreeRspDBC = 0
 563 // bits[30:28] Xbar2SriFreeListCBInc = 0
 564   {
 565     CoreCountsPciRegister,
 566     {
 567       AMD_FAMILY_10,                      // CpuFamily
 568       AMD_F10_Dx                          // CpuRevision
 569     },
 570     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 571     {{
 572       PERFORMANCE_PROFILE_ALL,
 573       (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
 574       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
 575       0x00090917,                           // regData
 576       0x007FFF1F,                           // regMask
 577     }}
 578   },
 579 // F3x7C - Free List Buffer Count
 580 // bits[4:0]  Xbar2SriFreeListCBC = 21
 581 // bits[11:8] Sri2XbarFreeXreqCBC = 9
 582 // bits[15:12] Sri2XbarFreeRspCBC = 0
 583 // bits[19:16] Sri2XbarFreeXreqDBC = 9
 584 // bits[22:20] Sri2XbarFreeRspDBC = 0
 585 // bits[30:28] Xbar2SriFreeListCBInc = 0
 586   {
 587     CoreCountsPciRegister,
 588     {
 589       AMD_FAMILY_10,                      // CpuFamily
 590       AMD_F10_Dx                         // CpuRevision
 591     },
 592     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 593     {{
 594       PERFORMANCE_PROFILE_ALL,
 595       (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
 596       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
 597       0x00090915,                           // regData
 598       0x707FFF1F,                           // regMask
 599     }}
 600   },
 601 // F3x140 - SRI_to_XCS Token Count
 602 // bits[1:0] UpReqTok = 1
 603 // bits[3:2] DnReqTok = 1
 604 // bits[5:4] UpPreqTokC = 1
 605 // bits[7:6] DnPreqTok = 1
 606 // bits[9:8] UpRspTok = 3
 607 // bits[11:10] DnRspTok = 1
 608 // bits[13:12] IsocReqTok = 0
 609 // bits[15:14] IsocPreqTok = 0
 610 // bits[17:16] IsocRspTok = 0
 611 // bits[23:20] FreeTok = A
 612   {
 613     ProcCountsPciRegister,
 614     {
 615       AMD_FAMILY_10,                      // CpuFamily
 616       AMD_F10_ALL                         // CpuRevision
 617     },
 618     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 619     {{
 620       PERFORMANCE_PROFILE_ALL,
 621       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)),  // anything but two.
 622       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 623       0x00A00755,                           // regData
 624       0x00F3FFFF,                           // regMask
 625     }}
 626   },
 627 // F3x140 - SRI_to_XCS Token Count
 628 // bits[1:0] UpReqTok = 1
 629 // bits[3:2] DnReqTok = 1
 630 // bits[5:4] UpPreqTokC = 1
 631 // bits[7:6] DnPreqTok = 1
 632 // bits[9:8] UpRspTok = 3
 633 // bits[11:10] DnRspTok = 1
 634 // bits[13:12] IsocReqTok = 0
 635 // bits[15:14] IsocPreqTok = 0
 636 // bits[17:16] IsocRspTok = 0
 637 // bits[23:20] FreeTok = 8
 638   {
 639     ProcCountsPciRegister,
 640     {
 641       AMD_FAMILY_10,                      // CpuFamily
 642       AMD_F10_ALL                         // CpuRevision
 643     },
 644     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 645     {{
 646       PERFORMANCE_PROFILE_ALL,
 647       (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),   // exactly two.
 648       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 649       0x00800755,                           // regData
 650       0x00F3FFFF,                           // regMask
 651     }}
 652   },
 653 // F3x140 - SRI_to_XCS Token Count
 654 // bits[1:0] UpReqTok = 1
 655 // bits[3:2] DnReqTok = 1
 656 // bits[5:4] UpPreqTokC = 1
 657 // bits[7:6] DnPreqTok = 1
 658 // bits[9:8] UpRspTok = 3
 659 // bits[11:10] DnRspTok = 1
 660 // bits[13:12] IsocReqTok = 1
 661 // bits[15:14] IsocPreqTok = 0
 662 // bits[17:16] IsocRspTok = 1
 663 // bits[23:20] FreeTok = 10
 664   {
 665     TokenPciRegister,
 666     {
 667       AMD_FAMILY_10,                      // CpuFamily
 668       AMD_F10_ALL                         // CpuRevision
 669     },
 670     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 671     {{
 672       PERFORMANCE_PROFILE_ALL,
 673       (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
 674       PACKAGE_TYPE_ALL,
 675       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 676       0x00A11755,                           // regData
 677       0x00F3FFFF,                           // regMask
 678     }}
 679   },
 680 // F3x140 - SRI_to_XCS Token Count
 681 // bits[1:0] UpReqTok = 1
 682 // bits[3:2] DnReqTok = 1
 683 // bits[5:4] UpPreqTokC = 1
 684 // bits[7:6] DnPreqTok = 1
 685 // bits[9:8] UpRspTok = 3
 686 // bits[11:10] DnRspTok = 1
 687 // bits[13:12] IsocReqTok = 1
 688 // bits[15:14] IsocPreqTok = 0
 689 // bits[17:16] IsocRspTok = 1
 690 // bits[23:20] FreeTok = 9
 691   {
 692     TokenPciRegister,
 693     {
 694       AMD_FAMILY_10,                      // CpuFamily
 695       AMD_F10_ALL                         // CpuRevision
 696     },
 697     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 698     {{
 699       PERFORMANCE_PROBEFILTER,
 700       (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
 701       PACKAGE_TYPE_ALL,
 702       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 703       0x00911755,                           // regData
 704       0x00F3FFFF,                           // regMask
 705     }}
 706   },
 707 // F3x140 - SRI_to_XCS Token Count
 708 // bits[1:0] UpReqTok = 1
 709 // bits[3:2] DnReqTok = 1
 710 // bits[5:4] UpPreqTokC = 1
 711 // bits[7:6] DnPreqTok = 1
 712 // bits[9:8] UpRspTok = 3
 713 // bits[11:10] DnRspTok = 1
 714 // bits[13:12] IsocReqTok = 1
 715 // bits[15:14] IsocPreqTok = 0
 716 // bits[17:16] IsocRspTok = 1
 717 // bits[23:20] FreeTok = 5
 718   {
 719     TokenPciRegister,
 720     {
 721       AMD_FAMILY_10,                      // CpuFamily
 722       AMD_F10_ALL                         // CpuRevision
 723     },
 724     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 725     {{
 726       PERFORMANCE_PROFILE_ALL,
 727       (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
 728       PACKAGE_TYPE_ALL,
 729       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 730       0x00511755,                           // regData
 731       0x00F3FFFF,                           // regMask
 732     }}
 733   },
 734 // F3x140 - SRI_to_XCS Token Count
 735 // bits[1:0] UpReqTok = 1
 736 // bits[3:2] DnReqTok = 1
 737 // bits[5:4] UpPreqTokC = 1
 738 // bits[7:6] DnPreqTok = 1
 739 // bits[9:8] UpRspTok = 1
 740 // bits[11:10] DnRspTok = 1
 741 // bits[13:12] IsocReqTok = 1
 742 // bits[15:14] IsocPreqTok = 0
 743 // bits[17:16] IsocRspTok = 1
 744 // bits[23:20] FreeTok = 7
 745   {
 746     TokenPciRegister,
 747     {
 748       AMD_FAMILY_10,                      // CpuFamily
 749       AMD_F10_ALL                         // CpuRevision
 750     },
 751     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 752     {{
 753       PERFORMANCE_PROBEFILTER,
 754       (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
 755       PACKAGE_TYPE_ALL,
 756       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 757       0x00711555,                           // regData
 758       0x00F3FFFF,                           // regMask
 759     }}
 760   },
 761 // F3x140 - SRI_to_XCS Token Count
 762 // bits[1:0] UpReqTok = 1
 763 // bits[3:2] DnReqTok = 1
 764 // bits[5:4] UpPreqTokC = 1
 765 // bits[7:6] DnPreqTok = 1
 766 // bits[9:8] UpRspTok = 3
 767 // bits[11:10] DnRspTok = 1
 768 // bits[13:12] IsocReqTok = 1
 769 // bits[15:14] IsocPreqTok = ]
 770 // bits[17:16] IsocRspTok = 1
 771 // bits[23:20] FreeTok = 8
 772   {
 773     TokenPciRegister,
 774     {
 775       AMD_FAMILY_10,                      // CpuFamily
 776       AMD_F10_ALL                         // CpuRevision
 777     },
 778     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 779     {{
 780       PERFORMANCE_PROFILE_ALL,
 781       (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE),     // 4 Socket, half populated.
 782       PACKAGE_TYPE_ALL,
 783       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 784       0x00811755,                           // regData
 785       0x00F3FFFF,                           // regMask
 786     }}
 787   },
 788 // F3x140 - SRI_to_XCS Token Count
 789 // bits[1:0] UpReqTok = 1
 790 // bits[3:2] DnReqTok = 1
 791 // bits[5:4] UpPreqTokC = 1
 792 // bits[7:6] DnPreqTok = 1
 793 // bits[9:8] UpRspTok = 3
 794 // bits[11:10] DnRspTok = 1
 795 // bits[13:12] IsocReqTok = 1
 796 // bits[15:14] IsocPreqTok = 0
 797 // bits[17:16] IsocRspTok = 2
 798 // bits[23:20] FreeTok = 2
 799   {
 800     TokenPciRegister,
 801     {
 802       AMD_FAMILY_10,                      // CpuFamily
 803       AMD_F10_ALL                         // CpuRevision
 804     },
 805     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 806     {{
 807       PERFORMANCE_PROFILE_ALL,
 808       (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
 809       PACKAGE_TYPE_ALL,
 810       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 811       0x00211755,                           // regData
 812       0x00F3FFFF,                           // regMask
 813     }}
 814   },
 815 // F3x140 - SRI_to_XCS Token Count
 816 // bits[1:0] UpReqTok = 1
 817 // bits[3:2] DnReqTok = 1
 818 // bits[5:4] UpPreqTokC = 1
 819 // bits[7:6] DnPreqTok = 1
 820 // bits[9:8] UpRspTok = 1
 821 // bits[11:10] DnRspTok = 1
 822 // bits[13:12] IsocReqTok = 1
 823 // bits[15:14] IsocPreqTok = 0
 824 // bits[17:16] IsocRspTok = 1
 825 // bits[23:20] FreeTok = 6
 826   {
 827     TokenPciRegister,
 828     {
 829       AMD_FAMILY_10,                      // CpuFamily
 830       AMD_F10_ALL                         // CpuRevision
 831     },
 832     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 833     {{
 834       PERFORMANCE_PROBEFILTER,
 835       (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
 836       PACKAGE_TYPE_ALL,
 837       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 838       0x00611555,                           // regData
 839       0x00F3FFFF,                           // regMask
 840     }}
 841   },
 842 // F3x140 - SRI_to_XCS Token Count
 843 // bits[1:0] UpReqTok = 2
 844 // bits[3:2] DnReqTok = 1
 845 // bits[5:4] UpPreqTokC = 1
 846 // bits[7:6] DnPreqTok = 1
 847 // bits[9:8] UpRspTok = 3
 848 // bits[11:10] DnRspTok = 1
 849 // bits[13:12] IsocReqTok = 0
 850 // bits[15:14] IsocPreqTok = 0
 851 // bits[17:16] IsocRspTok = 0
 852 // bits[23:20] FreeTok = 8
 853   {
 854     TokenPciRegister,
 855     {
 856       AMD_FAMILY_10,                      // CpuFamily
 857       AMD_F10_C32_ALL                     // CpuRevision
 858     },
 859     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 860     {{
 861       PERFORMANCE_PROFILE_ALL,
 862       (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
 863       PACKAGE_TYPE_ALL,
 864       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 865       0x00800756,                           // regData
 866       0x00F3FFFF,                           // regMask
 867     }}
 868   },
 869 // F3x140 - SRI_to_XCS Token Count
 870 // bits[1:0] UpReqTok = 2
 871 // bits[3:2] DnReqTok = 1
 872 // bits[5:4] UpPreqTokC = 1
 873 // bits[7:6] DnPreqTok = 1
 874 // bits[9:8] UpRspTok = 3
 875 // bits[11:10] DnRspTok = 1
 876 // bits[13:12] IsocReqTok = 1
 877 // bits[15:14] IsocPreqTok = 0
 878 // bits[17:16] IsocRspTok = 1
 879 // bits[23:20] FreeTok = 8
 880   {
 881     TokenPciRegister,
 882     {
 883       AMD_FAMILY_10,                      // CpuFamily
 884       AMD_F10_C32_ALL                     // CpuRevision
 885     },
 886     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 887     {{
 888       PERFORMANCE_PROFILE_ALL,
 889       (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
 890       PACKAGE_TYPE_ALL,
 891       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 892       0x00811756,                           // regData
 893       0x00F3FFFF,                           // regMask
 894     }}
 895   },
 896 // F3x144 - MCT to XCS Token Count
 897 // bits[3:0] RspTok = 3
 898 // bits[7:4] ProbeTok = 3
 899   {
 900     ProfileFixup,
 901     {
 902       AMD_FAMILY_10,                      // CpuFamily
 903       AMD_F10_ALL                         // CpuRevision
 904     },
 905     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 906     {{
 907       PERFORMANCE_PROFILE_ALL,
 908       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
 909       0x00000033,                           // regData
 910       0x000000FF,                           // regMask
 911     }}
 912   },
 913 // F3x144 - MCT to XCS Token Count
 914 // bits[3:0] RspTok = 5
 915 // bits[7:4] ProbeTok = 1
 916   {
 917     ProfileFixup,
 918     {
 919       AMD_FAMILY_10,                      // CpuFamily
 920       AMD_F10_ALL                         // CpuRevision
 921     },
 922     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
 923     {{
 924       PERFORMANCE_PROBEFILTER,              // Features
 925       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
 926       0x00000015,                           // regData
 927       0x000000FF,                           // regMask
 928     }}
 929   },
 930 // F3x144 - MCT to XCS Token Count
 931 // All non probe filter configs
 932 // bits[3:0] RspTok = 3
 933 // bits[7:4] ProbeTok = 3
 934   {
 935     ProfileFixup,
 936     {
 937       AMD_FAMILY_10,                      // CpuFamily
 938       AMD_F10_ALL                         // CpuRevision
 939     },
 940     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 941     {{
 942       PERFORMANCE_PROFILE_ALL,
 943       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
 944       0x00000033,                           // regData
 945       0x000000FF,                           // regMask
 946     }}
 947   },
 948 // F3x144 - MCT to XCS Token Count
 949 // bits[3:0] RspTok = 4
 950 // bits[7:4] ProbeTok = 1
 951   {
 952     TokenPciRegister,
 953     {
 954       AMD_FAMILY_10,                      // CpuFamily
 955       AMD_F10_ALL                         // CpuRevision
 956     },
 957     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 958     {{
 959       PERFORMANCE_PROBEFILTER,              // Features
 960       (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | DEGREE_RANGE_1 (4, COUNT_RANGE_HIGH)),     // 2 Socket, half populated, or 4 Socket, fully populated.
 961       PACKAGE_TYPE_ALL,
 962       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
 963       0x00000014,                           // regData
 964       0x000000FF,                           // regMask
 965     }}
 966   },
 967 // F3x144 - MCT to XCS Token Count
 968 // bits[3:0] RspTok = 5
 969 // bits[7:4] ProbeTok = 1
 970   {
 971     TokenPciRegister,
 972     {
 973       AMD_FAMILY_10,                      // CpuFamily
 974       AMD_F10_ALL                         // CpuRevision
 975     },
 976     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 977     {{
 978       PERFORMANCE_PROBEFILTER,              // Features
 979       (DEGREE_RANGE_0 (2, 2) | DEGREE_RANGE_1 (3, 3)),     // 2 Socket, fully populated, or 4 Socket, half populated.
 980       PACKAGE_TYPE_ALL,
 981       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
 982       0x00000015,                           // regData
 983       0x000000FF,                           // regMask
 984     }}
 985   },
 986 // F3x144 - MCT to XCS Token Count
 987 // bits[3:0] RspTok = 5
 988 // bits[7:4] ProbeTok = 1
 989   {
 990     ProfileFixup,
 991     {
 992       AMD_FAMILY_10,                      // CpuFamily
 993       AMD_F10_C32_ALL                     // CpuRevision
 994     },
 995     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
 996     {{
 997       PERFORMANCE_PROBEFILTER,
 998       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
 999       0x00000015,                           // regData
1000       0x000000FF,                           // regMask
1001     }}
1002   },
1003 // F3x148 - Link to XCS Token Count
1004 // bits[1:0] ReqTok0 = 2
1005 // bits[3:2] PReqTok0 = 2
1006 // bits[5:4] RspTok0 = 2
1007 // bits[7:6] ProbeTok0 = 2
1008 // bits[9:8] IsocReqTok0 = 0
1009 // bits[11:10] IsocPreqTok0 = 0
1010 // bits[13:12] IsocRspTok0 = 0
1011 // bits[15:14] FreeTok[1:0] = 0
1012 // bits[17:16] ReqTok1 = 0
1013 // bits[19:18] PReqTok1 = 0
1014 // bits[21:20] RspTok1 = 0
1015 // bits[23:22] ProbeTok1= 0
1016 // bits[24] IsocReqTok1 = 0
1017 // bits[25] IsocPreqTok1 = 0
1018 // bits[28] IsocRspTok1 = 0
1019 // bits[31:30] FreeTok[3:2] = 0
1020   {
1021     HtTokenPciRegister,
1022     {
1023       AMD_FAMILY_10,                      // CpuFamily
1024       AMD_F10_ALL                         // CpuRevision
1025     },
1026     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
1027     {{
1028       (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
1029       PERFORMANCE_PROFILE_ALL,
1030       HT_HOST_FEAT_GANGED,
1031       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1032       0x000000AA,                           // regData
1033       0xD5FFFFFF,                           // regMask
1034     }}
1035   },
1036 // F3x148 - Link to XCS Token Count
1037 // bits[1:0] ReqTok0 = 1
1038 // bits[3:2] PReqTok0 = 1
1039 // bits[5:4] RspTok0 = 1
1040 // bits[7:6] ProbeTok0 = 1
1041 // bits[9:8] IsocReqTok0 = 1
1042 // bits[11:10] IsocPreqTok0 = 0
1043 // bits[13:12] IsocRspTok0 = 0
1044 // bits[15:14] FreeTok[1:0] = 0
1045 // bits[17:16] ReqTok1 = 1
1046 // bits[19:18] PReqTok1 = 1
1047 // bits[21:20] RspTok1 = 1
1048 // bits[23:22] ProbeTok1= 1
1049 // bits[24] IsocReqTok1 = 0
1050 // bits[25] IsocPreqTok1 = 0
1051 // bits[28] IsocRspTok1 = 0
1052 // bits[31:30] FreeTok[3:2] = 0
1053   {
1054     HtTokenPciRegister,
1055     {
1056       AMD_FAMILY_10,                      // CpuFamily
1057       AMD_F10_ALL                         // CpuRevision
1058     },
1059     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
1060     {{
1061       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),
1062       PERFORMANCE_PROFILE_ALL,
1063       HT_HOST_FEAT_UNGANGED,
1064       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1065       0x00550055,                           // regData
1066       0xD5FFFFFF,                           // regMask
1067     }}
1068   },
1069 // F3x148 - Link to XCS Token Count
1070 // bits[1:0] ReqTok0 = 1
1071 // bits[3:2] PReqTok0 = 1
1072 // bits[5:4] RspTok0 = 1
1073 // bits[7:6] ProbeTok0 = 1
1074 // bits[9:8] IsocReqTok0 = 1
1075 // bits[11:10] IsocPreqTok0 = 0
1076 // bits[13:12] IsocRspTok0 = 0
1077 // bits[15:14] FreeTok[1:0] = 0
1078 // bits[17:16] ReqTok1 = 1
1079 // bits[19:18] PReqTok1 = 1
1080 // bits[21:20] RspTok1 = 1
1081 // bits[23:22] ProbeTok1= 1
1082 // bits[24] IsocReqTok1 = 0
1083 // bits[25] IsocPreqTok1 = 0
1084 // bits[28] IsocRspTok1 = 0
1085 // bits[31:30] FreeTok[3:2] = 0
1086   {
1087     HtTokenPciRegister,
1088     {
1089       AMD_FAMILY_10,                      // CpuFamily
1090       AMD_F10_ALL                         // CpuRevision
1091     },
1092     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
1093     {{
1094       (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
1095       PERFORMANCE_PROFILE_ALL,
1096       HT_HOST_FEAT_UNGANGED,
1097       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1098       0x00550055,                           // regData
1099       0xD5FFFFFF,                           // regMask
1100     }}
1101   },
1102 // F3x148 - Link to XCS Token Count
1103 // bits[1:0] ReqTok0 = 1
1104 // bits[3:2] PReqTok0 = 1
1105 // bits[5:4] RspTok0 = 1
1106 // bits[7:6] ProbeTok0 = 1
1107 // bits[9:8] IsocReqTok0 = 0
1108 // bits[11:10] IsocPreqTok0 = 0
1109 // bits[13:12] IsocRspTok0 = 0
1110 // bits[15:14] FreeTok[1:0] = 1
1111 // bits[17:16] ReqTok1 = 1
1112 // bits[19:18] PReqTok1 = 1
1113 // bits[21:20] RspTok1 = 1
1114 // bits[23:22] ProbeTok1= 1
1115 // bits[24] IsocReqTok1 = 0
1116 // bits[25] IsocPreqTok1 = 0
1117 // bits[28] IsocRspTok1 = 0
1118 // bits[31:30] FreeTok[3:2] = 0
1119   {
1120     HtTokenPciRegister,
1121     {
1122       AMD_FAMILY_10,                      // CpuFamily
1123       AMD_F10_ALL                         // CpuRevision
1124     },
1125     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
1126     {{
1127       (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
1128       PERFORMANCE_PROFILE_ALL,
1129       HT_HOST_FEAT_UNGANGED,
1130       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1131       0x00554055,                           // regData
1132       0xD5FFFFFF,                           // regMask
1133     }}
1134   },
1135 // F3x148 - Link to XCS Token Count
1136 // bits[1:0] ReqTok0 = 2
1137 // bits[3:2] PReqTok0 = 2
1138 // bits[5:4] RspTok0 = 2
1139 // bits[7:6] ProbeTok0 = 0
1140 // bits[9:8] IsocReqTok0 = 1
1141 // bits[11:10] IsocPreqTok0 = 0
1142 // bits[13:12] IsocRspTok0 = 0
1143 // bits[15:14] FreeTok[1:0] = 0
1144 // bits[17:16] ReqTok1 = 0
1145 // bits[19:18] PReqTok1 = 0
1146 // bits[21:20] RspTok1 = 0
1147 // bits[23:22] ProbeTok1= 0
1148 // bits[24] IsocReqTok1 = 0
1149 // bits[25] IsocPreqTok1 = 0
1150 // bits[28] IsocRspTok1 = 0
1151 // bits[31:30] FreeTok[3:2] = 0
1152   {
1153     HtTokenPciRegister,
1154     {
1155       AMD_FAMILY_10,                      // CpuFamily
1156       AMD_F10_ALL                         // CpuRevision
1157     },
1158     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1159     {{
1160       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
1161       PERFORMANCE_PROFILE_ALL,
1162       HT_HOST_FEAT_NONCOHERENT,
1163       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1164       0x0000012A,                           // regData
1165       0xD5FFFFFF,                           // regMask
1166     }}
1167   },
1168 // F3x148 - Link to XCS Token Count
1169 // bits[1:0] ReqTok0 = 2
1170 // bits[3:2] PReqTok0 = 1
1171 // bits[5:4] RspTok0 = 2
1172 // bits[7:6] ProbeTok0 = 2
1173 // bits[9:8] IsocReqTok0 = 1
1174 // bits[11:10] IsocPreqTok0 = 0
1175 // bits[13:12] IsocRspTok0 = 0
1176 // bits[15:14] FreeTok[1:0] = 0
1177 // bits[17:16] ReqTok1 = 0
1178 // bits[19:18] PReqTok1 = 0
1179 // bits[21:20] RspTok1 = 0
1180 // bits[23:22] ProbeTok1= 0
1181 // bits[24] IsocReqTok1 = 0
1182 // bits[25] IsocPreqTok1 = 0
1183 // bits[28] IsocRspTok1 = 0
1184 // bits[31:30] FreeTok[3:2] = 0
1185   {
1186     HtTokenPciRegister,
1187     {
1188       AMD_FAMILY_10,                      // CpuFamily
1189       AMD_F10_ALL                         // CpuRevision
1190     },
1191     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1192     {{
1193       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
1194       PERFORMANCE_PROFILE_ALL,
1195       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
1196       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1197       0x000001A6,                           // regData
1198       0xD5FFFFFF,                           // regMask
1199     }}
1200   },
1201 // F3x148 - Link to XCS Token Count
1202 // bits[1:0] ReqTok0 = 2
1203 // bits[3:2] PReqTok0 = 2
1204 // bits[5:4] RspTok0 = 2
1205 // bits[7:6] ProbeTok0 = 1
1206 // bits[9:8] IsocReqTok0 = 1
1207 // bits[11:10] IsocPreqTok0 = 0
1208 // bits[13:12] IsocRspTok0 = 0
1209 // bits[15:14] FreeTok[1:0] = 0
1210 // bits[17:16] ReqTok1 = 0
1211 // bits[19:18] PReqTok1 = 0
1212 // bits[21:20] RspTok1 = 0
1213 // bits[23:22] ProbeTok1= 0
1214 // bits[24] IsocReqTok1 = 0
1215 // bits[25] IsocPreqTok1 = 0
1216 // bits[28] IsocRspTok1 = 0
1217 // bits[31:30] FreeTok[3:2] = 0
1218   {
1219     HtTokenPciRegister,
1220     {
1221       AMD_FAMILY_10,                      // CpuFamily
1222       AMD_F10_ALL                         // CpuRevision
1223     },
1224     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1225     {{
1226       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
1227       PERFORMANCE_PROBEFILTER,
1228       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
1229       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1230       0x0000016A,                           // regData
1231       0xD5FFFFFF,                           // regMask
1232     }}
1233   },
1234 // F3x148 - Link to XCS Token Count
1235 // bits[1:0] ReqTok0 = 1
1236 // bits[3:2] PReqTok0 = 1
1237 // bits[5:4] RspTok0 = 1
1238 // bits[7:6] ProbeTok0 = 1
1239 // bits[9:8] IsocReqTok0 = 1
1240 // bits[11:10] IsocPreqTok0 = 1
1241 // bits[13:12] IsocRspTok0 = 0
1242 // bits[15:14] FreeTok[1:0] = 0
1243 // bits[17:16] ReqTok1 = 1
1244 // bits[19:18] PReqTok1 = 1
1245 // bits[21:20] RspTok1 = 1
1246 // bits[23:22] ProbeTok1= 1
1247 // bits[24] IsocReqTok1 = 1
1248 // bits[25] IsocPreqTok1 = 0
1249 // bits[28] IsocRspTok1 = 0
1250 // bits[31:30] FreeTok[3:2] = 0
1251   {
1252     HtTokenPciRegister,
1253     {
1254       AMD_FAMILY_10,                      // CpuFamily
1255       AMD_F10_ALL                         // CpuRevision
1256     },
1257     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1258     {{
1259       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),
1260       PERFORMANCE_PROFILE_ALL,
1261       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
1262       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1263       0x01550155,                           // regData
1264       0xD5FFFFFF,                           // regMask
1265     }}
1266   },
1267 // F3x148 - Link to XCS Token Count
1268 // bits[1:0] ReqTok0 = 1
1269 // bits[3:2] PReqTok0 = 1
1270 // bits[5:4] RspTok0 = 1
1271 // bits[7:6] ProbeTok0 = 1
1272 // bits[9:8] IsocReqTok0 = 1
1273 // bits[11:10] IsocPreqTok0 = 1
1274 // bits[13:12] IsocRspTok0 = 0
1275 // bits[15:14] FreeTok[1:0] = 0
1276 // bits[17:16] ReqTok1 = 1
1277 // bits[19:18] PReqTok1 = 1
1278 // bits[21:20] RspTok1 = 1
1279 // bits[23:22] ProbeTok1= 1
1280 // bits[24] IsocReqTok1 = 1
1281 // bits[25] IsocPreqTok1 = 0
1282 // bits[28] IsocRspTok1 = 0
1283 // bits[31:30] FreeTok[3:2] = 0
1284   {
1285     HtTokenPciRegister,
1286     {
1287       AMD_FAMILY_10,                      // CpuFamily
1288       AMD_F10_ALL                         // CpuRevision
1289     },
1290     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1291     {{
1292       (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
1293       PERFORMANCE_PROFILE_ALL,
1294       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
1295       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1296       0x01550155,                           // regData
1297       0xD5FFFFFF,                           // regMask
1298     }}
1299   },
1300 // F3x148 - Link to XCS Token Count
1301 // bits[1:0] ReqTok0 = 2
1302 // bits[3:2] PReqTok0 = 2
1303 // bits[5:4] RspTok0 = 2
1304 // bits[7:6] ProbeTok0 = 0
1305 // bits[9:8] IsocReqTok0 = 2
1306 // bits[11:10] IsocPreqTok0 = 0
1307 // bits[13:12] IsocRspTok0 = 0
1308 // bits[15:14] FreeTok[1:0] = 0
1309 // bits[17:16] ReqTok1 = 0
1310 // bits[19:18] PReqTok1 = 0
1311 // bits[21:20] RspTok1 = 0
1312 // bits[23:22] ProbeTok1= 0
1313 // bits[24] IsocReqTok1 = 0
1314 // bits[25] IsocPreqTok1 = 0
1315 // bits[28] IsocRspTok1 = 0
1316 // bits[31:30] FreeTok[3:2] = 0
1317   {
1318     HtTokenPciRegister,
1319     {
1320       AMD_FAMILY_10,                      // CpuFamily
1321       AMD_F10_ALL                         // CpuRevision
1322     },
1323     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1324     {{
1325       (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
1326       PERFORMANCE_PROFILE_ALL,
1327       HT_HOST_FEAT_NONCOHERENT,
1328       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1329       0x0000022A,                           // regData
1330       0xD5FFFFFF,                           // regMask
1331     }}
1332   },
1333 // F3x148 - Link to XCS Token Count
1334 // bits[1:0] ReqTok0 = 1
1335 // bits[3:2] PReqTok0 = 1
1336 // bits[5:4] RspTok0 = 1
1337 // bits[7:6] ProbeTok0 = 1
1338 // bits[9:8] IsocReqTok0 = 1
1339 // bits[11:10] IsocPreqTok0 = 0
1340 // bits[13:12] IsocRspTok0 = 0
1341 // bits[15:14] FreeTok[1:0] = 1
1342 // bits[17:16] ReqTok1 = 1
1343 // bits[19:18] PReqTok1 = 1
1344 // bits[21:20] RspTok1 = 1
1345 // bits[23:22] ProbeTok1= 1
1346 // bits[24] IsocReqTok1 = 1
1347 // bits[25] IsocPreqTok1 = 0
1348 // bits[28] IsocRspTok1 = 0
1349 // bits[31:30] FreeTok[3:2] = 0
1350   {
1351     HtTokenPciRegister,
1352     {
1353       AMD_FAMILY_10,                      // CpuFamily
1354       AMD_F10_ALL                         // CpuRevision
1355     },
1356     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1357     {{
1358       (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
1359       PERFORMANCE_PROFILE_ALL,
1360       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
1361       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1362       0x01554155,                           // regData
1363       0xD5FFFFFF,                           // regMask
1364     }}
1365   },
1366 // F3x148 - Link to XCS Token Count
1367 // bits[1:0] ReqTok0 = 2
1368 // bits[3:2] PReqTok0 = 1
1369 // bits[5:4] RspTok0 = 2
1370 // bits[7:6] ProbeTok0 = 2
1371 // bits[9:8] IsocReqTok0 = 1
1372 // bits[11:10] IsocPreqTok0 = 0
1373 // bits[13:12] IsocRspTok0 = 0
1374 // bits[15:14] FreeTok[1:0] = 0
1375 // bits[17:16] ReqTok1 = 0
1376 // bits[19:18] PReqTok1 = 0
1377 // bits[21:20] RspTok1 = 0
1378 // bits[23:22] ProbeTok1= 0
1379 // bits[24] IsocReqTok1 = 0
1380 // bits[25] IsocPreqTok1 = 0
1381 // bits[28] IsocRspTok1 = 0
1382 // bits[31:30] FreeTok[3:2] = 0
1383   {
1384     HtTokenPciRegister,
1385     {
1386       AMD_FAMILY_10,                      // CpuFamily
1387       AMD_F10_ALL                         // CpuRevision
1388     },
1389     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1390     {{
1391       (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
1392       PERFORMANCE_PROFILE_ALL,
1393       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
1394       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1395       0x000001A6,                           // regData
1396       0xD5FFFFFF,                           // regMask
1397     }}
1398   },
1399 // F3x148 - Link to XCS Token Count
1400 // bits[1:0] ReqTok0 = 2
1401 // bits[3:2] PReqTok0 = 1
1402 // bits[5:4] RspTok0 =1
1403 // bits[7:6] ProbeTok0 = 2
1404 // bits[9:8] IsocReqTok0 = 1
1405 // bits[11:10] IsocPreqTok0 = 0
1406 // bits[13:12] IsocRspTok0 = 0
1407 // bits[15:14] FreeTok[1:0] = 0
1408 // bits[17:16] ReqTok1 = 0
1409 // bits[19:18] PReqTok1 = 0
1410 // bits[21:20] RspTok1 = 0
1411 // bits[23:22] ProbeTok1= 0
1412 // bits[24] IsocReqTok1 = 0
1413 // bits[25] IsocPreqTok1 = 0
1414 // bits[28] IsocRspTok1 = 0
1415 // bits[31:30] FreeTok[3:2] = 0
1416   {
1417     HtTokenPciRegister,
1418     {
1419       AMD_FAMILY_10,                      // CpuFamily
1420       AMD_F10_ALL                         // CpuRevision
1421     },
1422     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1423     {{
1424       (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
1425       PERFORMANCE_PROBEFILTER,
1426       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
1427       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1428       0x00000196,                           // regData
1429       0xD5FFFFFF,                           // regMask
1430     }}
1431   },
1432 // F3x148 - Link to XCS Token Count
1433 // bits[1:0] ReqTok0 = 2
1434 // bits[3:2] PReqTok0 = 2
1435 // bits[5:4] RspTok0 = 2
1436 // bits[7:6] ProbeTok0 = 2
1437 // bits[9:8] IsocReqTok0 = 0
1438 // bits[11:10] IsocPreqTok0 = 0
1439 // bits[13:12] IsocRspTok0 = 0
1440 // bits[15:14] FreeTok[1:0] = 3
1441 // bits[17:16] ReqTok1 = 0
1442 // bits[19:18] PReqTok1 = 0
1443 // bits[21:20] RspTok1 = 0
1444 // bits[23:22] ProbeTok1= 0
1445 // bits[24] IsocReqTok1 = 0
1446 // bits[25] IsocPreqTok1 = 0
1447 // bits[28] IsocRspTok1 = 0
1448 // bits[31:30] FreeTok[3:2] = 0
1449   {
1450     HtTokenPciRegister,
1451     {
1452       AMD_FAMILY_10,                      // CpuFamily
1453       AMD_F10_C32_ALL                     // CpuRevision
1454     },
1455     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
1456     {{
1457       (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
1458       PERFORMANCE_PROFILE_ALL,
1459       HT_HOST_FEATURES_ALL,
1460       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1461       0x0000C0AA,                           // regData
1462       0xD5FFFFFF,                           // regMask
1463     }}
1464   },
1465 // F3x148 - Link to XCS Token Count
1466 // bits[1:0] ReqTok0 = 2
1467 // bits[3:2] PReqTok0 = 2
1468 // bits[5:4] RspTok0 = 2
1469 // bits[7:6] ProbeTok0 = 0
1470 // bits[9:8] IsocReqTok0 = 1
1471 // bits[11:10] IsocPreqTok0 = 0
1472 // bits[13:12] IsocRspTok0 = 0
1473 // bits[15:14] FreeTok[1:0] = 2
1474 // bits[17:16] ReqTok1 = 0
1475 // bits[19:18] PReqTok1 = 0
1476 // bits[21:20] RspTok1 = 0
1477 // bits[23:22] ProbeTok1= 0
1478 // bits[24] IsocReqTok1 = 0
1479 // bits[25] IsocPreqTok1 = 0
1480 // bits[28] IsocRspTok1 = 0
1481 // bits[31:30] FreeTok[3:2] = 0
1482   {
1483     HtTokenPciRegister,
1484     {
1485       AMD_FAMILY_10,                      // CpuFamily
1486       AMD_F10_C32_ALL                     // CpuRevision
1487     },
1488     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1489     {{
1490       (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
1491       PERFORMANCE_PROFILE_ALL,
1492       HT_HOST_FEAT_NONCOHERENT,
1493       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1494       0x0000812A,                           // regData
1495       0xD5FFFFFF,                           // regMask
1496     }}
1497   },
1498 // F3x148 - Link to XCS Token Count
1499 // bits[1:0] ReqTok0 = 2
1500 // bits[3:2] PReqTok0 = 2
1501 // bits[5:4] RspTok0 = 2
1502 // bits[7:6] ProbeTok0 = 2
1503 // bits[9:8] IsocReqTok0 = 1
1504 // bits[11:10] IsocPreqTok0 = 0
1505 // bits[13:12] IsocRspTok0 = 0
1506 // bits[15:14] FreeTok[1:0] = 2
1507 // bits[17:16] ReqTok1 = 0
1508 // bits[19:18] PReqTok1 = 0
1509 // bits[21:20] RspTok1 = 0
1510 // bits[23:22] ProbeTok1= 0
1511 // bits[24] IsocReqTok1 = 0
1512 // bits[25] IsocPreqTok1 = 0
1513 // bits[28] IsocRspTok1 = 0
1514 // bits[31:30] FreeTok[3:2] = 0
1515   {
1516     HtTokenPciRegister,
1517     {
1518       AMD_FAMILY_10,                      // CpuFamily
1519       AMD_F10_C32_ALL                     // CpuRevision
1520     },
1521     { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
1522     {{
1523       (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
1524       PERFORMANCE_PROFILE_ALL,
1525       HT_HOST_FEAT_COHERENT,
1526       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
1527       0x000081AA,                           // regData
1528       0xD5FFFFFF,                           // regMask
1529     }}
1530   },
1531 };
1532
1533 CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable = {
1534   PrimaryCores,
1535   (sizeof (F10MultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
1536   F10MultiLinkPciRegisters,
1537 };