1 ; ****************************************************************************
5 ; * Agesa structures and definitions
7 ; * Contains AMD AGESA core interface
9 ; * @xrefitem bom "File Content Label" "Release Content"
11 ; * @e sub-project: Include
12 ; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
14 ; ****************************************************************************
16 ; * Copyright (C) 2012 Advanced Micro Devices, Inc.
17 ; * All rights reserved.
19 ; * Redistribution and use in source and binary forms, with or without
20 ; * modification, are permitted provided that the following conditions are met:
21 ; * * Redistributions of source code must retain the above copyright
22 ; * notice, this list of conditions and the following disclaimer.
23 ; * * Redistributions in binary form must reproduce the above copyright
24 ; * notice, this list of conditions and the following disclaimer in the
25 ; * documentation and/or other materials provided with the distribution.
26 ; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 ; * its contributors may be used to endorse or promote products derived
28 ; * from this software without specific prior written permission.
30 ; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 ; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 ; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 ; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 ; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 ; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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39 ; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ; **************************************************************************
45 UINT64 TEXTEQU <QWORD>
46 UINT32 TEXTEQU <DWORD>
50 BOOLEAN TEXTEQU <BYTE>
51 POINTER TEXTEQU <DWORD>
53 ; AGESA Types and Definitions
55 AGESA_REVISION EQU "Arch2008"
58 LAST_ENTRY EQU 0FFFFFFFFh
59 IMAGE_SIGNATURE EQU 'DMA$'
63 ; The return status for all AGESA public services.
65 ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
66 ; will have log entries with more detail.
68 AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
69 AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
71 AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
72 ; < Example, memory address not installed, heap buffer handle not found.
74 ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
75 AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
76 ; < See log. Example, HT CRC.
77 AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
78 AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
79 AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
80 AGESA_FATAL EQU 7 ; < Halt booting. See Log.
81 AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
82 AGESA_STATUS TEXTEQU <DWORD>
84 ; For checking whether a status is at or above the mandatory log level.
85 AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
87 CALLOUT_ENTRY TEXTEQU <POINTER>
88 IMAGE_ENTRY TEXTEQU <POINTER>
89 MODULE_ENTRY TEXTEQU <POINTER>
91 ; This allocation type is used by the AmdCreateStruct entry point
92 PreMemHeap EQU 0 ; < Create heap in cache.
93 PostMemDram EQU 1 ; < Create heap in memory.
94 ByHost EQU 2 ; < Create heap by Host.
95 ALLOCATION_METHOD TEXTEQU <DWORD>
97 ; These width descriptors are used by the library function, and others, to specify the data size
98 AccessWidth8 EQU 1 ; < Access width is 8 bits.
99 AccessWidth16 EQU 2 ; < Access width is 16 bits.
100 AccessWidth32 EQU 3 ; < Access width is 32 bits.
101 AccessWidth64 EQU 4 ; < Access width is 64 bits.
103 AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
104 AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
105 AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
106 AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
107 ACCESS_WIDTH TEXTEQU <DWORD>
111 ; AGESA BASIC FUNCTIONS
112 AMD_INIT_RECOVERY EQU 00020000h
113 AMD_CREATE_STRUCT EQU 00020001h
114 AMD_INIT_EARLY EQU 00020002h
115 AMD_INIT_ENV EQU 00020003h
116 AMD_INIT_LATE EQU 00020004h
117 AMD_INIT_MID EQU 00020005h
118 AMD_INIT_POST EQU 00020006h
119 AMD_INIT_RESET EQU 00020007h
120 AMD_INIT_RESUME EQU 00020008h
121 AMD_RELEASE_STRUCT EQU 00020009h
122 AMD_S3LATE_RESTORE EQU 0002000Ah
123 AMD_S3_SAVE EQU 0002000Bh
124 AMD_GET_APIC_ID EQU 0002000Ch
125 AMD_GET_PCI_ADDRESS EQU 0002000Dh
126 AMD_IDENTIFY_CORE EQU 0002000Eh
127 AMD_READ_EVENT_LOG EQU 0002000Fh
128 AMD_GET_EXECACHE_SIZE EQU 00020010h
129 AMD_LATE_RUN_AP_TASK EQU 00020011h
130 AMD_IDENTIFY_DIMMS EQU 00020012h
131 AGESA_STRUCT_NAME TEXTEQU <DWORD>
134 ; ResetType constant values
135 WARM_RESET_WHENEVER EQU 1
136 COLD_RESET_WHENEVER EQU 2
137 WARM_RESET_IMMEDIATELY EQU 3
138 COLD_RESET_IMMEDIATELY EQU 4
143 ; The standard header for all AGESA services.
144 AMD_CONFIG_PARAMS STRUCT
145 ImageBasePtr UINT32 ? ; < The AGESA Image base address.
146 Func UINT32 ? ; < The service desired, @sa dispatch.h.
147 AltImageBasePtr UINT32 ? ; < Alternate Image location
148 CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
149 HeapStatus UINT8 ? ; < For heap status from boot time slide.
150 HeapBasePtr UINT64 ? ; < Location of the heap
151 Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
152 AMD_CONFIG_PARAMS ENDS
155 ; Create Struct Interface.
156 AMD_INTERFACE_PARAMS STRUCT
157 StdHeader AMD_CONFIG_PARAMS {} ; < Config header
158 AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
159 AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
160 NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
161 NewStructPtr POINTER ? ; < The struct for the service.
162 ; < The struct to init for ByHost allocation,
163 ; < the initialized struct on return.
164 AMD_INTERFACE_PARAMS ENDS
166 FUNC_0 EQU 0 ; bit-placed for PCI address creation
175 ; AGESA Binary module header structure
176 AMD_IMAGE_HEADER STRUCT
177 Signature UINT32 ? ; < Binary Signature
178 CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
179 Version CHAR8 (12) DUP (?) ; < 12 characters version
180 ModuleInfoOffset UINT32 ? ; < Offset of module
181 EntryPointAddress UINT32 ? ; < Entry address
182 ImageBase UINT32 ? ; < Image base
183 RelocTableOffset UINT32 ? ; < Relocate Table offset
184 ImageSize UINT32 ? ; < Size
185 Checksum UINT16 ? ; < Checksum
186 ImageType UINT8 ? ; < Type
187 V_Reserved UINT8 ? ; < Reserved
188 AMD_IMAGE_HEADER ENDS
189 ; AGESA Binary module header structure
190 AMD_MODULE_HEADER STRUCT
191 ModuleHeaderSignature UINT32 ? ; < Module signature
192 ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
193 ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
194 ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
195 NextBlock POINTER ? ; < Next module header link
196 AMD_MODULE_HEADER ENDS
198 ; AMD_CODE_HEADER Signatures.
199 AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
200 CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
201 CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
203 ; AGESA_CODE_SIGNATURE
204 AMD_CODE_HEADER STRUCT
205 Signature CHAR8 (8) DUP (?) ; < code header Signature
206 ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
207 Version CHAR8 (12) DUP (?) ; < 12 character version string
208 TerminatorNull CHAR8 ? ; < null terminated string
209 VerReserved CHAR8 (7) DUP (?) ; < reserved space
212 ; Extended PCI address format
215 ; IN OUT UINT32 Register:12; ; < Register offset
216 ; IN OUT UINT32 Function:3; ; < Function number
217 ; IN OUT UINT32 Device:5; ; < Device number
218 ; IN OUT UINT32 Bus:8; ; < Bus number
219 ; IN OUT UINT32 Segment:4; ; < Segment
222 ; Union type for PCI address
224 AddressValue UINT32 ? ; < Formal address
225 Address EXT_PCI_ADDR {} ; < Extended address
228 ; SBDFO - Segment Bus Device Function Offset
229 ; 31:28 Segment (4-bits)
231 ; 19:15 Device (5-bits)
232 ; 14:12 Function(3-bits)
233 ; 11:00 Offset (12-bits)
237 ILLEGAL_SBDFO EQU 0FFFFFFFFh
239 ; CPUID data received registers format
241 EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
242 EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
243 ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
244 EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
247 ; HT frequency for external callbacks
249 HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
250 HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
251 HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
252 HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
253 HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
254 HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
255 HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
256 HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
257 HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
258 HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
259 HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
260 HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
261 HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
262 HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
263 HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
264 HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
265 HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
266 HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
268 HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
271 BIT0 EQU 0000000000000001h
274 BIT1 EQU 0000000000000002h
277 BIT2 EQU 0000000000000004h
280 BIT3 EQU 0000000000000008h
283 BIT4 EQU 0000000000000010h
286 BIT5 EQU 0000000000000020h
289 BIT6 EQU 0000000000000040h
292 BIT7 EQU 0000000000000080h
295 BIT8 EQU 0000000000000100h
298 BIT9 EQU 0000000000000200h
301 BIT10 EQU 0000000000000400h
304 BIT11 EQU 0000000000000800h
307 BIT12 EQU 0000000000001000h
310 BIT13 EQU 0000000000002000h
313 BIT14 EQU 0000000000004000h
316 BIT15 EQU 0000000000008000h
319 BIT16 EQU 0000000000010000h
322 BIT17 EQU 0000000000020000h
325 BIT18 EQU 0000000000040000h
328 BIT19 EQU 0000000000080000h
331 BIT20 EQU 0000000000100000h
334 BIT21 EQU 0000000000200000h
337 BIT22 EQU 0000000000400000h
340 BIT23 EQU 0000000000800000h
343 BIT24 EQU 0000000001000000h
346 BIT25 EQU 0000000002000000h
349 BIT26 EQU 0000000004000000h
352 BIT27 EQU 0000000008000000h
355 BIT28 EQU 0000000010000000h
358 BIT29 EQU 0000000020000000h
361 BIT30 EQU 0000000040000000h
364 BIT31 EQU 0000000080000000h
367 BIT32 EQU 0000000100000000h
370 BIT33 EQU 0000000200000000h
373 BIT34 EQU 0000000400000000h
376 BIT35 EQU 0000000800000000h
379 BIT36 EQU 0000001000000000h
382 BIT37 EQU 0000002000000000h
385 BIT38 EQU 0000004000000000h
388 BIT39 EQU 0000008000000000h
391 BIT40 EQU 0000010000000000h
394 BIT41 EQU 0000020000000000h
397 BIT42 EQU 0000040000000000h
400 BIT43 EQU 0000080000000000h
403 BIT44 EQU 0000100000000000h
406 BIT45 EQU 0000200000000000h
409 BIT46 EQU 0000400000000000h
412 BIT47 EQU 0000800000000000h
415 BIT48 EQU 0001000000000000h
418 BIT49 EQU 0002000000000000h
421 BIT50 EQU 0004000000000000h
424 BIT51 EQU 0008000000000000h
427 BIT52 EQU 0010000000000000h
430 BIT53 EQU 0020000000000000h
433 BIT54 EQU 0040000000000000h
436 BIT55 EQU 0080000000000000h
439 BIT56 EQU 0100000000000000h
442 BIT57 EQU 0200000000000000h
445 BIT58 EQU 0400000000000000h
448 BIT59 EQU 0800000000000000h
451 BIT60 EQU 1000000000000000h
454 BIT61 EQU 2000000000000000h
457 BIT62 EQU 4000000000000000h
460 BIT63 EQU 8000000000000000h