src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * Install of build option: Memory
   6  *
   7  * Contains AMD AGESA install macros and test conditions. Output is the
   8  * defaults tables reflecting the User's build options selection.
   9  *
  10  * @xrefitem bom "File Content Label" "Release Content"
  11  * @e project:      AGESA
  12  * @e sub-project:  Options
  13  * @e \$Revision: 56315 $   @e \$Date: 2011-07-11 15:59:14 -0600 (Mon, 11 Jul 2011) $
  14  */
  15 /*****************************************************************************
  16  *
  17  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  18  * All rights reserved.
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions are met:
  22  *     * Redistributions of source code must retain the above copyright
  23  *       notice, this list of conditions and the following disclaimer.
  24  *     * Redistributions in binary form must reproduce the above copyright
  25  *       notice, this list of conditions and the following disclaimer in the
  26  *       documentation and/or other materials provided with the distribution.
  27  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  28  *       its contributors may be used to endorse or promote products derived
  29  *       from this software without specific prior written permission.
  30  *
  31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  32  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  33  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  34  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  35  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  37  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  38  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  40  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  *
  43  ***************************************************************************/
  44
  45 #ifndef _OPTION_MEMORY_INSTALL_H_
  46 #define _OPTION_MEMORY_INSTALL_H_
  47
  48 /* Memory Includes */
  49 #include "OptionMemory.h"
  50
  51 /*-------------------------------------------------------------------------------
  52  *  This option file is designed to be included into the platform solution install
  53  *  file. The platform solution install file will define the options status.
  54  *  Check to validate the definition
  55  */
  56
  57 /*----------------------------------------------------------------------------------
  58  * FEATURE BLOCK FUNCTIONS
  59  *
  60  *  This section defines function names that depend upon options that are selected
  61  *  in the platform solution install file.
  62  */
  63 BOOLEAN MemFDefRet (
  64   IN OUT   MEM_NB_BLOCK *NBPtr
  65   )
  66 {
  67   return FALSE;
  68 }
  69
  70 BOOLEAN MemMDefRet (
  71   IN   MEM_MAIN_DATA_BLOCK *MMPtr
  72   )
  73 {
  74   return TRUE;
  75 }
  76
  77 BOOLEAN MemMDefRetFalse (
  78   IN   MEM_MAIN_DATA_BLOCK *MMPtr
  79   )
  80 {
  81   return FALSE;
  82 }
  83
  84 /* -----------------------------------------------------------------------------*/
  85 /**
  86  *
  87  *
  88  *   This function initializes the northbridge block for dimm identification translator
  89  *
  90  *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
  91  *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
  92  *     @param[in,out]   NodeID   - ID of current node to construct
  93  *     @return          TRUE     - This is the correct constructor for the targeted node.
  94  *     @return          FALSE    - This isn't the correct constructor for the targeted node.
  95  */
  96 BOOLEAN MemNIdentifyDimmConstructorRetDef (
  97   IN OUT   MEM_NB_BLOCK *NBPtr,
  98   IN OUT   MEM_DATA_STRUCT *MemPtr,
  99   IN       UINT8 NodeID
 100   )
 101 {
 102   return FALSE;
 103 }
 104 /*----------------------------------------------------------------------------------
 105  * TABLE FEATURE BLOCK FUNCTIONS
 106  *
 107  *  This section defines function names that depend upon options that are selected
 108  *  in the platform solution install file.
 109  */
 110 UINT8 MemFTableDefRet (
 111   IN OUT   MEM_TABLE_ALIAS **MTPtr
 112   )
 113 {
 114   return 0;
 115 }
 116 /*----------------------------------------------------------------------------------
 117  * FEATURE S3 BLOCK FUNCTIONS
 118  *
 119  *  This section defines function names that depend upon options that are selected
 120  *  in the platform solution install file.
 121  */
 122 BOOLEAN MemFS3DefConstructorRet (
 123   IN OUT   VOID *S3NBPtr,
 124   IN OUT   MEM_DATA_STRUCT *MemPtr,
 125   IN       UINT8 NodeID
 126   )
 127 {
 128   return TRUE;
 129 }
 130
 131 #if (OPTION_MEMCTLR_DR == TRUE)
 132   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 133     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 134       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr;
 135       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr
 136     #else
 137       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
 138     #endif
 139   #else
 140     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
 141   #endif
 142   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 143     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr;
 144     #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr
 145   #else
 146     #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef
 147   #endif
 148 #endif
 149
 150 #if (OPTION_MEMCTLR_DA == TRUE  || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
 151   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 152     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 153       #if (OPTION_MEMCTLR_Ni == TRUE)
 154         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi;
 155         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi
 156       #else
 157         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
 158       #endif
 159       #if (OPTION_MEMCTLR_DA == TRUE)
 160         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA;
 161         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA
 162       #else
 163         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
 164       #endif
 165       #if (OPTION_MEMCTLR_PH == TRUE)
 166         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh;
 167         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh
 168       #else
 169         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
 170       #endif
 171       #if (OPTION_MEMCTLR_RB == TRUE)
 172         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb;
 173         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb
 174       #else
 175         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
 176       #endif
 177     #endif
 178   #else
 179     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
 180     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
 181     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
 182     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
 183   #endif
 184   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 185     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA;
 186     #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA
 187     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb;
 188     #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb
 189     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh;
 190     #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh
 191   #else
 192     #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef
 193     #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef
 194     #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef
 195   #endif
 196 #endif
 197
 198 #if (OPTION_MEMCTLR_OR == TRUE)
 199   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 200     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 201       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr;
 202       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr
 203     #else
 204       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
 205     #endif
 206   #else
 207     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
 208   #endif
 209   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 210     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr;
 211     #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr
 212   #else
 213     #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef
 214   #endif
 215 #endif
 216
 217 #if (OPTION_MEMCTLR_HY == TRUE)
 218   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 219     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 220       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy;
 221       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy
 222     #else
 223       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
 224     #endif
 225   #else
 226     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
 227   #endif
 228   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 229     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy;
 230     #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy
 231   #else
 232     #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef
 233   #endif
 234 #endif
 235
 236 #if (OPTION_MEMCTLR_C32 == TRUE)
 237   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 238     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 239       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32;
 240       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32
 241     #else
 242       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
 243     #endif
 244   #else
 245     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
 246   #endif
 247   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 248     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32;
 249     #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32
 250   #else
 251     #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef
 252   #endif
 253 #endif
 254
 255 /*----------------------------------------------------------------------------------
 256  * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
 257  *
 258  *----------------------------------------------------------------------------------
 259 */
 260 #define MEM_NB_SUPPORT_DR
 261 #define MEM_NB_SUPPORT_RB
 262 #define MEM_NB_SUPPORT_DA
 263 #define MEM_NB_SUPPORT_Ni
 264 #define MEM_NB_SUPPORT_PH
 265 #define MEM_NB_SUPPORT_HY
 266 #define MEM_NB_SUPPORT_OR
 267 #define MEM_NB_SUPPORT_C32
 268 #define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
 269
 270 #if (AGESA_ENTRY_INIT_POST == TRUE)
 271   /*----------------------------------------------------------------------------------
 272    * FLOW CONTROL FUNCTION
 273    *
 274    *  This section selects the function that controls the memory initialization sequence
 275    *  based upon the number of processor families that the BIOS will support.
 276    */
 277   extern MEM_FLOW_CFG MemMFlowDef;
 278   extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 279
 280
 281   #if (OPTION_MEMCTLR_DR == TRUE)
 282     extern MEM_FLOW_CFG MemMFlowDr;
 283     #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
 284   #else
 285     #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
 286   #endif
 287   #if (OPTION_MEMCTLR_DA == TRUE)
 288     extern MEM_FLOW_CFG MemMFlowDA;
 289     #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
 290   #else
 291     #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
 292   #endif
 293   #if (OPTION_MEMCTLR_HY == TRUE)
 294     extern MEM_FLOW_CFG MemMFlowHy;
 295     #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
 296   #else
 297     #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
 298   #endif
 299   #if (OPTION_MEMCTLR_OR == TRUE)
 300     extern MEM_FLOW_CFG MemMFlowOr;
 301     #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
 302   #else
 303     #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
 304   #endif
 305   #if (OPTION_MEMCTLR_C32 == TRUE)
 306     extern MEM_FLOW_CFG MemMFlowC32;
 307     #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
 308   #else
 309     #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
 310   #endif
 311   #if (OPTION_MEMCTLR_Ni == TRUE)
 312     extern MEM_FLOW_CFG MemMFlowDA;
 313     #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
 314   #else
 315     #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
 316   #endif
 317   #if (OPTION_MEMCTLR_RB == TRUE)
 318     extern MEM_FLOW_CFG MemMFlowRb;
 319     #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
 320   #else
 321     #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
 322   #endif
 323   #if (OPTION_MEMCTLR_PH == TRUE)
 324     extern MEM_FLOW_CFG MemMFlowPh;
 325     #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
 326   #else
 327     #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
 328   #endif
 329
 330   MEM_FLOW_CFG* memFlowControlInstalled[] = {
 331     MEM_MAIN_FLOW_CONTROL_PTR_Dr
 332     MEM_MAIN_FLOW_CONTROL_PTR_DA
 333     MEM_MAIN_FLOW_CONTROL_PTR_RB
 334     MEM_MAIN_FLOW_CONTROL_PTR_PH
 335     MEM_MAIN_FLOW_CONTROL_PTR_Hy
 336     MEM_MAIN_FLOW_CONTROL_PTR_OR
 337     MEM_MAIN_FLOW_CONTROL_PTR_C32
 338     MEM_MAIN_FLOW_CONTROL_PTR_Ni
 339     NULL
 340   };
 341
 342   #if (OPTION_ONLINE_SPARE == TRUE)
 343     extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
 344     #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
 345     extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
 346     #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
 347   #else
 348     #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
 349     #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
 350   #endif
 351
 352   #if (OPTION_MEM_RESTORE == TRUE)
 353     extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
 354     extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
 355     #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
 356     #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
 357   #else
 358     #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
 359     #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
 360   #endif
 361
 362   #if (OPTION_BANK_INTERLEAVE == TRUE)
 363     extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
 364     #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
 365     extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
 366     #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
 367   #else
 368     #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
 369     #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
 370   #endif
 371
 372   #if (OPTION_NODE_INTERLEAVE == TRUE)
 373     extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
 374     #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
 375     extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
 376     extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
 377     #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
 378     #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
 379   #else
 380     #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
 381     #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
 382     #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
 383   #endif
 384
 385   #if (OPTION_DCT_INTERLEAVE == TRUE)
 386     extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
 387     #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
 388   #else
 389     #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
 390   #endif
 391
 392   #if (OPTION_ECC == TRUE)
 393     extern OPTION_MEM_FEATURE_MAIN MemMEcc;
 394     #define MEM_MAIN_FEATURE_ECC  MemMEcc
 395     extern OPTION_MEM_FEATURE_NB MemFCheckECC;
 396     extern OPTION_MEM_FEATURE_NB MemFInitECC;
 397     #define MEM_FEATURE_CK_ECC   MemFCheckECC
 398     #define MEM_FEATURE_ECC   MemFInitECC
 399     #define MEM_FEATURE_ECCX8  MemMDefRet
 400   #else
 401     #define MEM_MAIN_FEATURE_ECC  MemMDefRet
 402     #define MEM_FEATURE_CK_ECC   MemFDefRet
 403     #define MEM_FEATURE_ECC   MemFDefRet
 404     #define MEM_FEATURE_ECCX8  MemMDefRet
 405   #endif
 406
 407     #define MEM_FEATURE_EMP   MemFDefRet
 408
 409   extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
 410   #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
 411
 412   #if (OPTION_DMI == TRUE)
 413     #if (OPTION_DDR3 == TRUE)
 414       extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
 415       #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
 416     #else
 417       extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
 418       #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
 419     #endif
 420   #else
 421     #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
 422   #endif
 423
 424   #if (OPTION_DDR3 == TRUE)
 425     extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
 426     extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
 427     extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
 428     #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
 429     #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
 430     #define MEM_FEATURE_LVDDR3 MemFLvDdr3
 431   #else
 432     #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
 433     #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
 434     #define MEM_FEATURE_LVDDR3 MemFDefRet
 435   #endif
 436
 437   extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
 438   #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
 439
 440   extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
 441   #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
 442
 443   #if (OPTION_PARALLEL_TRAINING == TRUE)
 444     extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
 445     #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
 446   #else
 447     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 448   #endif
 449
 450   #if (OPTION_DIMM_EXCLUDE == TRUE)
 451     extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
 452     #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
 453     extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
 454     #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
 455   #else
 456     #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
 457     #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
 458   #endif
 459
 460   /*----------------------------------------------------------------------------------
 461    * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
 462    *
 463    *----------------------------------------------------------------------------------
 464   */
 465   #if OPTION_DDR2 == TRUE
 466     extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
 467     #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
 468     #if (OPTION_HW_DRAM_INIT == TRUE)
 469       extern MEM_TECH_FEAT MemTDramInitHw;
 470       #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
 471     #else
 472       #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTFeatDef
 473     #endif
 474     #if (OPTION_SW_DRAM_INIT == TRUE)
 475       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
 476     #else
 477       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
 478     #endif
 479   #else
 480     #define MEM_TECH_CONSTRUCTOR_DDR2
 481   #endif
 482   #if OPTION_DDR3 == TRUE
 483     extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
 484     #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
 485     #if (OPTION_HW_DRAM_INIT == TRUE)
 486       extern MEM_TECH_FEAT MemTDramInitHw;
 487       #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
 488     #else
 489       #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
 490     #endif
 491     #if (OPTION_SW_DRAM_INIT == TRUE)
 492       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
 493     #else
 494       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
 495     #endif
 496   #else
 497     #define MEM_TECH_CONSTRUCTOR_DDR3
 498   #endif
 499
 500
 501   /*---------------------------------------------------------------------------------------------------
 502    * FEATURE BLOCKS
 503    *
 504    *  This section instantiates a feature block structure for each memory controller installed
 505    *  by the platform solution install file.
 506    *---------------------------------------------------------------------------------------------------
 507    */
 508
 509   #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 510     extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 511   #endif
 512   extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 513
 514   /*---------------------------------------------------------------------------------------------------
 515    * DEERHOUND FEATURE BLOCK
 516    *---------------------------------------------------------------------------------------------------
 517    */
 518   #if (OPTION_MEMCTLR_DR == TRUE)
 519     #if OPTION_DDR2
 520       #undef MEM_TECH_FEATURE_DRAMINIT
 521       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 522     #endif
 523     #if OPTION_DDR3
 524       #undef MEM_TECH_FEATURE_DRAMINIT
 525       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 526     #endif
 527
 528     #undef MEM_TECH_FEATURE_CPG
 529     #define MEM_TECH_FEATURE_CPG    MemFDefRet
 530
 531     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 532       #undef MEM_TECH_FEATURE_HWRXEN
 533       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 534     #else
 535       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 536       #undef MEM_TECH_FEATURE_HWRXEN
 537       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 538     #endif
 539
 540     #undef MEM_MAIN_FEATURE_TRAINING
 541     #undef MEM_FEATURE_TRAINING
 542     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 543     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 544
 545     MEM_FEAT_BLOCK_NB  MemFeatBlockDr = {
 546       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 547       MEM_FEATURE_ONLINE_SPARE,
 548       MEM_FEATURE_BANK_INTERLEAVE,
 549       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 550       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
 551       MEM_FEATURE_NODE_INTERLEAVE,
 552       MEM_FEATURE_CHANNEL_INTERLEAVE,
 553       MemFDefRet,
 554       MEM_FEATURE_CK_ECC,
 555       MEM_FEATURE_ECC,
 556       MEM_FEATURE_TRAINING,
 557       MEM_FEATURE_LVDDR3,
 558       MemFDefRet,
 559       MEM_TECH_FEATURE_DRAMINIT,
 560       MEM_FEATURE_DIMM_EXCLUDE,
 561       MemFDefRet,
 562       MEM_TECH_FEATURE_CPG,
 563       MEM_TECH_FEATURE_HWRXEN
 564     };
 565
 566     #undef MEM_NB_SUPPORT_DR
 567     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR;
 568     extern MEM_INITIALIZER MemNInitDefaultsDR;
 569
 570
 571     #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
 572   #endif // OPTION_MEMCTRL_DR
 573
 574   /*---------------------------------------------------------------------------------------------------
 575    * DASHOUND FEATURE BLOCK
 576    *---------------------------------------------------------------------------------------------------
 577    */
 578   #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
 579     #if OPTION_DDR2
 580       #undef MEM_TECH_FEATURE_DRAMINIT
 581       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 582     #endif
 583     #if OPTION_DDR3
 584       #undef MEM_TECH_FEATURE_DRAMINIT
 585       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 586     #endif
 587
 588     #undef MEM_TECH_FEATURE_CPG
 589     #define MEM_TECH_FEATURE_CPG    MemFDefRet
 590
 591     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 592       #undef MEM_TECH_FEATURE_HWRXEN
 593       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 594     #else
 595       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 596       #undef MEM_TECH_FEATURE_HWRXEN
 597       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 598     #endif
 599
 600     #undef MEM_MAIN_FEATURE_TRAINING
 601     #undef MEM_FEATURE_TRAINING
 602     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 603     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 604
 605     #if (OPTION_MEMCTLR_Ni == TRUE)
 606       MEM_FEAT_BLOCK_NB  MemFeatBlockNi = {
 607         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 608         MemFDefRet,
 609         MEM_FEATURE_BANK_INTERLEAVE,
 610         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 611         MemFDefRet,
 612         MemFDefRet,
 613         MEM_FEATURE_CHANNEL_INTERLEAVE,
 614         MEM_FEATURE_REGION_INTERLEAVE,
 615         MEM_FEATURE_CK_ECC,
 616         MEM_FEATURE_ECC,
 617         MEM_FEATURE_TRAINING,
 618         MEM_FEATURE_LVDDR3,
 619         MemFDefRet,
 620         MEM_TECH_FEATURE_DRAMINIT,
 621         MEM_FEATURE_DIMM_EXCLUDE,
 622         MemFDefRet,
 623         MEM_TECH_FEATURE_CPG,
 624         MEM_TECH_FEATURE_HWRXEN
 625       };
 626
 627       #undef MEM_NB_SUPPORT_Ni
 628       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi;
 629       extern MEM_INITIALIZER MemNInitDefaultsNi;
 630
 631       #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA },
 632     #endif
 633
 634     #if (OPTION_MEMCTLR_PH == TRUE)
 635       MEM_FEAT_BLOCK_NB  MemFeatBlockPh = {
 636         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 637         MemFDefRet,
 638         MEM_FEATURE_BANK_INTERLEAVE,
 639         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 640         MemFDefRet,
 641         MemFDefRet,
 642         MEM_FEATURE_CHANNEL_INTERLEAVE,
 643         MEM_FEATURE_REGION_INTERLEAVE,
 644         MEM_FEATURE_CK_ECC,
 645         MEM_FEATURE_ECC,
 646         MEM_FEATURE_TRAINING,
 647         MEM_FEATURE_LVDDR3,
 648         MemFDefRet,
 649         MEM_TECH_FEATURE_DRAMINIT,
 650         MEM_FEATURE_DIMM_EXCLUDE,
 651         MemFDefRet,
 652         MEM_TECH_FEATURE_CPG,
 653         MEM_TECH_FEATURE_HWRXEN
 654       };
 655
 656       #undef MEM_NB_SUPPORT_PH
 657       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh;
 658       extern MEM_INITIALIZER MemNInitDefaultsPh;
 659
 660       #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
 661     #endif
 662
 663     #if (OPTION_MEMCTLR_RB == TRUE)
 664       MEM_FEAT_BLOCK_NB  MemFeatBlockRb = {
 665         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 666         MemFDefRet,
 667         MEM_FEATURE_BANK_INTERLEAVE,
 668         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 669         MemFDefRet,
 670         MemFDefRet,
 671         MEM_FEATURE_CHANNEL_INTERLEAVE,
 672         MEM_FEATURE_REGION_INTERLEAVE,
 673         MEM_FEATURE_CK_ECC,
 674         MEM_FEATURE_ECC,
 675         MEM_FEATURE_TRAINING,
 676         MEM_FEATURE_LVDDR3,
 677         MemFDefRet,
 678         MEM_TECH_FEATURE_DRAMINIT,
 679         MEM_FEATURE_DIMM_EXCLUDE,
 680         MemFDefRet,
 681         MEM_TECH_FEATURE_CPG,
 682         MEM_TECH_FEATURE_HWRXEN
 683       };
 684
 685       #undef MEM_NB_SUPPORT_RB
 686       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb;
 687       extern MEM_INITIALIZER MemNInitDefaultsRb;
 688
 689       #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
 690     #endif
 691
 692     #if (OPTION_MEMCTLR_DA == TRUE)
 693       MEM_FEAT_BLOCK_NB  MemFeatBlockDA = {
 694         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 695         MemFDefRet,
 696         MEM_FEATURE_BANK_INTERLEAVE,
 697         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 698         MemFDefRet,
 699         MemFDefRet,
 700         MEM_FEATURE_CHANNEL_INTERLEAVE,
 701         MEM_FEATURE_REGION_INTERLEAVE,
 702         MEM_FEATURE_CK_ECC,
 703         MEM_FEATURE_ECC,
 704         MEM_FEATURE_TRAINING,
 705         MEM_FEATURE_LVDDR3,
 706         MemFDefRet,
 707         MEM_TECH_FEATURE_DRAMINIT,
 708         MEM_FEATURE_DIMM_EXCLUDE,
 709         MemFDefRet,
 710         MEM_TECH_FEATURE_CPG,
 711         MEM_TECH_FEATURE_HWRXEN
 712       };
 713
 714       #undef MEM_NB_SUPPORT_DA
 715       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA;
 716       extern MEM_INITIALIZER MemNInitDefaultsDA;
 717
 718       #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
 719     #endif
 720   #endif // OPTION_MEMCTRL_DA
 721
 722   /*---------------------------------------------------------------------------------------------------
 723    * HYDRA FEATURE BLOCK
 724    *---------------------------------------------------------------------------------------------------
 725    */
 726   #if (OPTION_MEMCTLR_HY == TRUE)
 727     #if OPTION_DDR2
 728       #undef MEM_TECH_FEATURE_DRAMINIT
 729       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 730     #endif
 731     #if OPTION_DDR3
 732       #undef MEM_TECH_FEATURE_DRAMINIT
 733       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 734     #endif
 735
 736     #undef MEM_TECH_FEATURE_CPG
 737     #define MEM_TECH_FEATURE_CPG    MemFDefRet
 738
 739     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 740       #undef MEM_TECH_FEATURE_HWRXEN
 741       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 742     #else
 743       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 744       #undef MEM_TECH_FEATURE_HWRXEN
 745       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 746     #endif
 747
 748
 749     #undef MEM_MAIN_FEATURE_TRAINING
 750     #undef MEM_FEATURE_TRAINING
 751     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 752     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 753
 754     MEM_FEAT_BLOCK_NB  MemFeatBlockHy = {
 755       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 756       MEM_FEATURE_ONLINE_SPARE,
 757       MEM_FEATURE_BANK_INTERLEAVE,
 758       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 759       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
 760       MEM_FEATURE_NODE_INTERLEAVE,
 761       MEM_FEATURE_CHANNEL_INTERLEAVE,
 762       MemFDefRet,
 763       MEM_FEATURE_CK_ECC,
 764       MEM_FEATURE_ECC,
 765       MEM_FEATURE_TRAINING,
 766       MEM_FEATURE_LVDDR3,
 767       MEM_FEATURE_ONDIMMTHERMAL,
 768       MEM_TECH_FEATURE_DRAMINIT,
 769       MEM_FEATURE_DIMM_EXCLUDE,
 770       MemFDefRet,
 771       MEM_TECH_FEATURE_CPG,
 772       MEM_TECH_FEATURE_HWRXEN
 773     };
 774
 775     #undef MEM_NB_SUPPORT_HY
 776     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY;
 777     extern MEM_INITIALIZER MemNInitDefaultsHY;
 778     #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
 779   #endif // OPTION_MEMCTRL_HY
 780   /*---------------------------------------------------------------------------------------------------
 781    * OROCHI FEATURE BLOCK
 782    *---------------------------------------------------------------------------------------------------
 783    */
 784   #if (OPTION_MEMCTLR_OR == TRUE)
 785     #if OPTION_DDR2
 786       #undef MEM_TECH_FEATURE_DRAMINIT
 787       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 788     #endif
 789     #if OPTION_DDR3
 790       #undef MEM_MAIN_FEATURE_LVDDR3
 791       extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
 792       #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
 793       #undef MEM_TECH_FEATURE_DRAMINIT
 794       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 795     #endif
 796
 797     #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT)
 798       #undef MEM_FEATURE_REGION_INTERLEAVE
 799       #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet
 800     #endif
 801
 802     #if (OPTION_EARLY_SAMPLES == TRUE)
 803       extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr;
 804       #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportOr
 805     #else
 806       #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
 807     #endif
 808
 809     #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
 810       extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
 811       #undef MEM_TECH_FEATURE_CPG
 812       #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
 813     #else
 814       #undef MEM_TECH_FEATURE_CPG
 815       #define MEM_TECH_FEATURE_CPG    MemFDefRet
 816     #endif
 817
 818     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 819       #undef MEM_TECH_FEATURE_HWRXEN
 820       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 821     #else
 822       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 823       #undef MEM_TECH_FEATURE_HWRXEN
 824       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 825     #endif
 826
 827
 828     #undef MEM_MAIN_FEATURE_TRAINING
 829     #undef MEM_FEATURE_TRAINING
 830     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 831     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 832
 833     MEM_FEAT_BLOCK_NB  MemFeatBlockOr = {
 834       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 835       MEM_FEATURE_ONLINE_SPARE,
 836       MEM_FEATURE_BANK_INTERLEAVE,
 837       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 838       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
 839       MEM_FEATURE_NODE_INTERLEAVE,
 840       MEM_FEATURE_CHANNEL_INTERLEAVE,
 841       MEM_FEATURE_REGION_INTERLEAVE,
 842       MEM_FEATURE_CK_ECC,
 843       MEM_FEATURE_ECC,
 844       MEM_FEATURE_TRAINING,
 845       MEM_FEATURE_LVDDR3,
 846       MEM_FEATURE_ONDIMMTHERMAL,
 847       MEM_TECH_FEATURE_DRAMINIT,
 848       MEM_FEATURE_DIMM_EXCLUDE,
 849       MEM_EARLY_SAMPLE_SUPPORT,
 850       MEM_TECH_FEATURE_CPG,
 851       MEM_TECH_FEATURE_HWRXEN
 852     };
 853
 854     #undef MEM_NB_SUPPORT_OR
 855     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR;
 856     extern MEM_INITIALIZER MemNInitDefaultsOR;
 857     #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
 858   #endif // OPTION_MEMCTRL_OR
 859
 860   /*---------------------------------------------------------------------------------------------------
 861    * C32 FEATURE BLOCK
 862    *---------------------------------------------------------------------------------------------------
 863    */
 864   #if (OPTION_MEMCTLR_C32 == TRUE)
 865     #if OPTION_DDR2
 866       #undef MEM_TECH_FEATURE_DRAMINIT
 867       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 868     #endif
 869     #if OPTION_DDR3
 870       #undef MEM_TECH_FEATURE_DRAMINIT
 871       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 872     #endif
 873
 874       #undef MEM_TECH_FEATURE_CPG
 875       #define MEM_TECH_FEATURE_CPG    MemFDefRet
 876
 877     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 878       #undef MEM_TECH_FEATURE_HWRXEN
 879       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 880     #else
 881       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 882       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 883     #endif
 884
 885     #undef MEM_MAIN_FEATURE_TRAINING
 886     #undef MEM_FEATURE_TRAINING
 887     #if (OPTION_MEMCTLR_OR == TRUE)
 888     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 889     #else
 890       #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 891     #endif
 892     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 893
 894     MEM_FEAT_BLOCK_NB  MemFeatBlockC32 = {
 895       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 896       MEM_FEATURE_ONLINE_SPARE,
 897       MEM_FEATURE_BANK_INTERLEAVE,
 898       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 899       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
 900       MEM_FEATURE_NODE_INTERLEAVE,
 901       MEM_FEATURE_CHANNEL_INTERLEAVE,
 902       MemFDefRet,
 903       MEM_FEATURE_CK_ECC,
 904       MEM_FEATURE_ECC,
 905       MEM_FEATURE_TRAINING,
 906       MEM_FEATURE_LVDDR3,
 907       MEM_FEATURE_ONDIMMTHERMAL,
 908       MEM_TECH_FEATURE_DRAMINIT,
 909       MEM_FEATURE_DIMM_EXCLUDE,
 910       MemFDefRet,
 911       MEM_TECH_FEATURE_CPG,
 912       MEM_TECH_FEATURE_HWRXEN
 913     };
 914
 915     #undef MEM_NB_SUPPORT_C32
 916     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32;
 917     extern MEM_INITIALIZER MemNInitDefaultsC32;
 918     #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
 919   #endif // OPTION_MEMCTRL_C32
 920
 921   /*---------------------------------------------------------------------------------------------------
 922    * MAIN FEATURE BLOCK
 923    *---------------------------------------------------------------------------------------------------
 924    */
 925   MEM_FEAT_BLOCK_MAIN MemFeatMain = {
 926     MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
 927     MEM_MAIN_FEATURE_TRAINING,
 928     MEM_MAIN_FEATURE_DIMM_EXCLUDE,
 929     MEM_MAIN_FEATURE_ONLINE_SPARE,
 930     MEM_MAIN_FEATURE_NODE_INTERLEAVE,
 931     MEM_MAIN_FEATURE_ECC,
 932     MEM_MAIN_FEATURE_MEM_CLEAR,
 933     MEM_MAIN_FEATURE_MEM_DMI,
 934     MEM_MAIN_FEATURE_LVDDR3,
 935     MEM_MAIN_FEATURE_UMAALLOC,
 936     MEM_MAIN_FEATURE_MEM_SAVE,
 937     MEM_MAIN_FEATURE_MEM_RESTORE
 938   };
 939
 940
 941   /*---------------------------------------------------------------------------------------------------
 942    * Technology Training SPECIFIC CONFIGURATION
 943    *
 944    *
 945    *---------------------------------------------------------------------------------------------------
 946    */
 947   #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
 948   #if OPTION_MEMCTLR_DR
 949     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
 950     #if OPTION_DDR2
 951       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
 952       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
 953       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
 954       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
 955       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
 956       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 957         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
 958         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
 959         #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTTrainDQSEdgeDetect
 960       #else
 961         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
 962         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
 963         #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
 964           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
 965         #else
 966           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTFeatDef
 967     #endif
 968     #endif
 969       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
 970         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
 971     #else
 972         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
 973     #endif
 974       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
 975         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
 976     #else
 977         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
 978     #endif
 979       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
 980         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
 981     #else
 982         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
 983     #endif
 984       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
 985         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
 986       #else
 987         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
 988     #endif
 989       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
 990         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
 991       #else
 992         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
 993     #endif
 994       #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
 995       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Dr = {
 996         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
 997         TECH_TRAIN_ENTER_HW_TRN_DDR2,
 998         TECH_TRAIN_SW_WL_DDR2,
 999         TECH_TRAIN_HW_WL_P1_DDR2,
1000         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1001         TECH_TRAIN_HW_WL_P2_DDR2,
1002         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1003         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1004         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1005         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1006         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1007         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1008         TECH_TRAIN_MAX_RD_LAT_DDR2,
1009         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
1010         TECH_TRAIN_DQS____DDR2
1011       };
1012       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1013       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1014       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1015       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr },
1016     #else
1017       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1018       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1019       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1020       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1021       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1022       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1023       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1024       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1025       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1026       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1027       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1028       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1029       #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
1030       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1031       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1032     #endif
1033     #if OPTION_DDR3
1034       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1035       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1036       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1037       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1038       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1039         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1040         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1041     #else
1042         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1043         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1044     #endif
1045       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1046         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1047     #else
1048         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1049     #endif
1050     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1051         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
1052         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
1053         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
1054           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1055           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
1056     #else
1057           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1058             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1059     #else
1060             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1061     #endif
1062     #endif
1063     #else
1064         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1065         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1066         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1067           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1068       #else
1069           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1070       #endif
1071     #endif
1072       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1073         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1074       #else
1075         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1076     #endif
1077       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1078         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1079       #else
1080         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1081     #endif
1082       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1083         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1084     #else
1085         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1086     #endif
1087       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1088         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1089     #else
1090         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1091     #endif
1092       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1093         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1094     #else
1095         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1096     #endif
1097       #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
1098       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1099       extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
1100       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Dr = {
1101         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1102         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1103         TECH_TRAIN_SW_WL_DDR3,
1104         TECH_TRAIN_HW_WL_P1_DDR3,
1105         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1106         TECH_TRAIN_HW_WL_P2_DDR3,
1107         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1108         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1109         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1110         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1111         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1112         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1113         TECH_TRAIN_MAX_RD_LAT_DDR3,
1114         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
1115         TECH_TRAIN_DQS____DDR3
1116     };
1117       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr },
1118     #else
1119       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1120       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1121       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1122       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1123       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1124       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1125       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1126       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1127       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1128       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1129       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1130       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1131       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1132       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1133       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1134       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1135     #endif
1136     #else
1137     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1138     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1139     #endif
1140
1141   #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB)
1142     #if OPTION_DDR2
1143       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1144       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1145       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1146       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1147       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1148       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1149         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1150         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1151         #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTTrainDQSEdgeDetect
1152       #else
1153         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1154         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1155         #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1156           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1157         #else
1158           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTFeatDef
1159         #endif
1160       #endif
1161       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1162         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1163       #else
1164         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1165       #endif
1166       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1167         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1168       #else
1169         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1170       #endif
1171       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1172         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1173       #else
1174         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1175       #endif
1176       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1177         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1178       #else
1179         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1180       #endif
1181       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1182         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1183       #else
1184         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1185       #endif
1186       #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
1187       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2DA = {
1188         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1189         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1190         TECH_TRAIN_SW_WL_DDR2,
1191         TECH_TRAIN_HW_WL_P1_DDR2,
1192         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1193         TECH_TRAIN_HW_WL_P2_DDR2,
1194         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1195         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1196         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1197         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1198         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1199         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1200         TECH_TRAIN_MAX_RD_LAT_DDR2,
1201         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
1202         TECH_TRAIN_DQS____DDR2
1203       };
1204       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2PH = {
1205         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1206         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1207         TECH_TRAIN_SW_WL_DDR2,
1208         TECH_TRAIN_HW_WL_P1_DDR2,
1209         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1210         TECH_TRAIN_HW_WL_P2_DDR2,
1211         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1212         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1213         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1214         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1215         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1216         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1217         TECH_TRAIN_MAX_RD_LAT_DDR2,
1218         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
1219         TECH_TRAIN_DQS____DDR2
1220       };
1221       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Rb = {
1222         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1223         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1224         TECH_TRAIN_SW_WL_DDR2,
1225         TECH_TRAIN_HW_WL_P1_DDR2,
1226         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1227         TECH_TRAIN_HW_WL_P2_DDR2,
1228         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1229         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1230         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1231         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1232         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1233         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1234         TECH_TRAIN_MAX_RD_LAT_DDR2,
1235         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
1236         TECH_TRAIN_DQS____DDR2
1237       };
1238       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Ni = {
1239         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1240         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1241         TECH_TRAIN_SW_WL_DDR2,
1242         TECH_TRAIN_HW_WL_P1_DDR2,
1243         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1244         TECH_TRAIN_HW_WL_P2_DDR2,
1245         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1246         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1247         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1248         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1249         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1250         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1251         TECH_TRAIN_MAX_RD_LAT_DDR2,
1252         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
1253         TECH_TRAIN_DQS____DDR2
1254       };
1255       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1256       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1257       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1258       #if (OPTION_MEMCTLR_DA)
1259         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA
1260         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA },
1261       #else
1262         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1263       #endif
1264       #if (OPTION_MEMCTLR_PH)
1265         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh
1266         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH },
1267       #else
1268         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1269       #endif
1270       #if (OPTION_MEMCTLR_RB)
1271         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb
1272         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb },
1273       #else
1274         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1275       #endif
1276
1277       #if (OPTION_MEMCTLR_Ni)
1278         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi
1279         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni },
1280       #else
1281         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1282       #endif
1283     #else
1284       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1285       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1286       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1287       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1288       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1289       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1290       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1291       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1292       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1293       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1294       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1295       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1296       #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
1297       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1298       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1299       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1300       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1301       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1302     #endif
1303     #if OPTION_DDR3
1304       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1305       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1306       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1307       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1308       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1309         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1310         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1311       #else
1312         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1313         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1314       #endif
1315       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1316         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1317       #else
1318         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1319       #endif
1320       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1321         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1322           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1323         #endif
1324         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
1325         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1326           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1327         #endif
1328         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
1329         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
1330           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1331           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1332         #else
1333           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1334             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1335           #else
1336             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1337           #endif
1338         #endif
1339       #else
1340         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1341         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1342         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1343           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1344           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1345         #else
1346           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1347         #endif
1348       #endif
1349       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1350         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1351       #else
1352         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1353       #endif
1354       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1355         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1356       #else
1357         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1358       #endif
1359       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1360         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1361       #else
1362         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1363       #endif
1364       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1365         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1366       #else
1367         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1368       #endif
1369       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1370         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1371       #else
1372         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1373       #endif
1374       #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
1375       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3DA = {
1376         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1377         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1378         TECH_TRAIN_SW_WL_DDR3,
1379         TECH_TRAIN_HW_WL_P1_DDR3,
1380         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1381         TECH_TRAIN_HW_WL_P2_DDR3,
1382         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1383         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1384         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1385         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1386         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1387         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1388         TECH_TRAIN_MAX_RD_LAT_DDR3,
1389         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
1390         TECH_TRAIN_DQS____DDR3
1391       };
1392       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ph = {
1393         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1394         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1395         TECH_TRAIN_SW_WL_DDR3,
1396         TECH_TRAIN_HW_WL_P1_DDR3,
1397         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1398         TECH_TRAIN_HW_WL_P2_DDR3,
1399         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1400         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1401         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1402         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1403         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1404         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1405         TECH_TRAIN_MAX_RD_LAT_DDR3,
1406         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
1407         TECH_TRAIN_DQS____DDR3
1408       };
1409       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Rb = {
1410         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1411         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1412         TECH_TRAIN_SW_WL_DDR3,
1413         TECH_TRAIN_HW_WL_P1_DDR3,
1414         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1415         TECH_TRAIN_HW_WL_P2_DDR3,
1416         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1417         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1418         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1419         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1420         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1421         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1422         TECH_TRAIN_MAX_RD_LAT_DDR3,
1423         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
1424         TECH_TRAIN_DQS____DDR3
1425       };
1426       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ni = {
1427         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1428         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1429         TECH_TRAIN_SW_WL_DDR3,
1430         TECH_TRAIN_HW_WL_P1_DDR3,
1431         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1432         TECH_TRAIN_HW_WL_P2_DDR3,
1433         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1434         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1435         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1436         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1437         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1438         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1439         TECH_TRAIN_MAX_RD_LAT_DDR3,
1440         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
1441         TECH_TRAIN_DQS____DDR3
1442       };
1443       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1444       #if (OPTION_MEMCTLR_DA)
1445         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA;
1446         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA },
1447       #else
1448         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1449       #endif
1450       #if (OPTION_MEMCTLR_PH)
1451         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh;
1452         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph },
1453       #else
1454         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1455       #endif
1456       #if (OPTION_MEMCTLR_RB)
1457         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb;
1458         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb },
1459       #else
1460         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1461       #endif
1462       #if (OPTION_MEMCTLR_Ni)
1463         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi;
1464         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni },
1465       #else
1466         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1467       #endif
1468     #else
1469       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1470       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1471       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1472       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1473       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1474       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1475       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1476       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1477       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1478       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1479       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1480       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1481       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1482       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1483       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1484       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1485       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1486       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1487       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1488     #endif
1489   #else
1490     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1491     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1492     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1493     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1494     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1495     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1496     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1497     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1498   #endif
1499
1500   #if OPTION_MEMCTLR_HY
1501     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy;
1502     #if OPTION_DDR2
1503       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1504       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1505       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1506       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1507       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1508       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1509         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1510         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1511         #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1512       #else
1513         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1514         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1515         #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1516           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1517         #else
1518           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTFeatDef
1519         #endif
1520       #endif
1521       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1522         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1523       #else
1524         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1525       #endif
1526       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1527         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1528       #else
1529         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1530       #endif
1531       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1532         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1533       #else
1534         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1535       #endif
1536       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1537         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1538       #else
1539         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1540       #endif
1541       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1542         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1543       #else
1544         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1545       #endif
1546       #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
1547       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Hy = {
1548         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1549         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1550         TECH_TRAIN_SW_WL_DDR2,
1551         TECH_TRAIN_HW_WL_P1_DDR2,
1552         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1553         TECH_TRAIN_HW_WL_P2_DDR2,
1554         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1555         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1556         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1557         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1558         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1559         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1560         TECH_TRAIN_MAX_RD_LAT_DDR2,
1561         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
1562         TECH_TRAIN_DQS____DDR2
1563       };
1564       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1565       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1566       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1567       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy },
1568     #else
1569       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1570       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1571       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1572       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1573       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1574       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1575       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1576       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1577       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1578       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1579       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1580       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1581       #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
1582       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1583       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1584     #endif
1585     #if OPTION_DDR3
1586       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1587       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1588       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1589       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1590       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1591         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1592         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1593       #else
1594         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1595         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1596       #endif
1597       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1598         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1599       #else
1600         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1601       #endif
1602       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1603         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1604           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1605         #endif
1606         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
1607         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1608           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1609         #endif
1610         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
1611         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
1612           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1613           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1614         #else
1615           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1616             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1617           #else
1618             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1619           #endif
1620         #endif
1621       #else
1622         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1623         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1624         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1625           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1626         #else
1627           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1628         #endif
1629       #endif
1630       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1631         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1632       #else
1633         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1634       #endif
1635       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1636         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1637       #else
1638         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1639       #endif
1640       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1641         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1642       #else
1643         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1644       #endif
1645       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1646         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1647       #else
1648         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1649       #endif
1650       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1651         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1652       #else
1653         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1654       #endif
1655       #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
1656       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Hy = {
1657         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1658         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1659         TECH_TRAIN_SW_WL_DDR3,
1660         TECH_TRAIN_HW_WL_P1_DDR3,
1661         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1662         TECH_TRAIN_HW_WL_P2_DDR3,
1663         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1664         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1665         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1666         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1667         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1668         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1669         TECH_TRAIN_MAX_RD_LAT_DDR3,
1670         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
1671         TECH_TRAIN_DQS____DDR3
1672       };
1673       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1674       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy },
1675     #else
1676       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1677       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1678       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1679       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1680       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1681       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1682       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1683       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1684       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1685       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1686       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1687       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1688       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1689       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1690       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1691       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1692     #endif
1693   #else
1694     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1695     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1696   #endif
1697
1698   #if OPTION_MEMCTLR_C32
1699     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32;
1700     #if OPTION_DDR2
1701       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1702       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1703       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1704       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1705       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1706       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1707         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1708         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1709         #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1710       #else
1711         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1712         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1713         #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1714           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1715         #else
1716           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1717         #endif
1718       #endif
1719       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1720         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1721       #else
1722         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1723       #endif
1724       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1725         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1726       #else
1727         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1728       #endif
1729       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1730         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1731       #else
1732         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1733       #endif
1734       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1735         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1736       #else
1737         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1738       #endif
1739       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1740         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1741       #else
1742         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1743       #endif
1744       #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
1745       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2C32 = {
1746         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1747         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1748         TECH_TRAIN_SW_WL_DDR2,
1749         TECH_TRAIN_HW_WL_P1_DDR2,
1750         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1751         TECH_TRAIN_HW_WL_P2_DDR2,
1752         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1753         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1754         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1755         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1756         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1757         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1758         TECH_TRAIN_MAX_RD_LAT_DDR2,
1759         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
1760         TECH_TRAIN_DQS____DDR2
1761       };
1762       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1763       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1764       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1765       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 },
1766     #else
1767       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1768       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1769       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1770       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1771       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1772       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1773       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1774       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1775       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1776       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1777       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1778       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1779       #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
1780       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1781       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1782     #endif
1783     #if OPTION_DDR3
1784       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1785       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1786       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1787       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1788       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1789         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1790         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1791       #else
1792         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1793         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1794       #endif
1795       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1796         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1797       #else
1798         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1799       #endif
1800       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1801         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1802           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1803         #endif
1804         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
1805         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1806           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1807         #endif
1808         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
1809         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
1810           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1811         #else
1812           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1813             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1814           #else
1815             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1816           #endif
1817         #endif
1818       #else
1819         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1820         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1821         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1822           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1823         #else
1824           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1825         #endif
1826       #endif
1827       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1828         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1829       #else
1830         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1831       #endif
1832       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1833         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1834       #else
1835         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1836       #endif
1837       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1838         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1839       #else
1840         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1841       #endif
1842       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1843         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1844       #else
1845         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1846       #endif
1847       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1848         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1849       #else
1850         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1851       #endif
1852       #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
1853       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3C32 = {
1854         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1855         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1856         TECH_TRAIN_SW_WL_DDR3,
1857         TECH_TRAIN_HW_WL_P1_DDR3,
1858         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1859         TECH_TRAIN_HW_WL_P2_DDR3,
1860         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1861         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1862         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1863         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1864         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1865         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1866         TECH_TRAIN_MAX_RD_LAT_DDR3,
1867         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
1868         TECH_TRAIN_DQS____DDR3
1869       };
1870       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1871       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 },
1872     #else
1873       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1874       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1875       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1876       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1877       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1878       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1879       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1880       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1881       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1882       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1883       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1884       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1885       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1886       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1887       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1888       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1889     #endif
1890   #else
1891     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1892     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1893   #endif
1894
1895
1896   #if OPTION_MEMCTLR_OR
1897     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr;
1898     #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1899     #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1900     #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1901     #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1902     #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1903     #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1904     #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1905     #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1906     #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1907     #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1908     #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1909     #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1910     #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
1911     #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1912     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1913     #if OPTION_DDR3
1914       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1915       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1916       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1917       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1918       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1919         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1920         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1921       #else
1922         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1923         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1924       #endif
1925       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1926         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1927       #else
1928       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1929       #endif
1930       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1931         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1932           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1933         #endif
1934         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
1935         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1936           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1937         #endif
1938         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
1939         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
1940           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1941           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
1942         #else
1943           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1944             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1945           #else
1946             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1947           #endif
1948         #endif
1949       #else
1950         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1951         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1952         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1953           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1954         #else
1955           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1956         #endif
1957       #endif
1958       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1959         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
1960       #else
1961         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1962       #endif
1963       #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
1964       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1965         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
1966       #else
1967         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1968       #endif
1969       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1970         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1971       #else
1972         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1973       #endif
1974       #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
1975       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1976         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1977       #else
1978         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1979       #endif
1980       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1981         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1982       #else
1983         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1984       #endif
1985       #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
1986       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3OR = {
1987         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1988         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1989         TECH_TRAIN_SW_WL_DDR3,
1990         TECH_TRAIN_HW_WL_P1_DDR3,
1991         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1992         TECH_TRAIN_HW_WL_P2_DDR3,
1993         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1994         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1995         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1996         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1997         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1998         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1999         TECH_TRAIN_MAX_RD_LAT_DDR3,
2000         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
2001         TECH_TRAIN_DQS____DDR3
2002       };
2003       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
2004       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR },
2005     #else
2006       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2007       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
2008       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2009       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
2010       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2011       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2012       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2013       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2014       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2015       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2016       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2017       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2018       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2019       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2020       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2021       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2022     #endif
2023   #else
2024     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2025     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2026   #endif
2027
2028   #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
2029   MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
2030     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR
2031     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA
2032     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY
2033     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32
2034     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni
2035     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR
2036     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH
2037     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB
2038     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
2039   };
2040
2041   MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
2042     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR
2043     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA
2044     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY
2045     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32
2046     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni
2047     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR
2048     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH
2049     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB
2050     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
2051   };
2052   /*---------------------------------------------------------------------------------------------------
2053    * NB TRAINING FLOW CONTROL
2054    *
2055    *
2056    *---------------------------------------------------------------------------------------------------
2057    */
2058   OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
2059     NB_TRAIN_FLOW_DDR2,
2060     NB_TRAIN_FLOW_DDR3,
2061   };
2062   /*---------------------------------------------------------------------------------------------------
2063    * TECHNOLOGY BLOCK
2064    *
2065    *
2066    *---------------------------------------------------------------------------------------------------
2067    */
2068   MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
2069     MEM_TECH_CONSTRUCTOR_DDR2
2070     MEM_TECH_CONSTRUCTOR_DDR3
2071     NULL
2072   };
2073    /*---------------------------------------------------------------------------------------------------
2074    * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
2075    *
2076    *
2077    *---------------------------------------------------------------------------------------------------
2078    */
2079   #if  OPTION_MEMCTLR_HY
2080     #if OPTION_UDIMMS
2081       #if OPTION_DDR2
2082         #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2083       #else
2084         #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2085       #endif
2086       #if OPTION_DDR3
2087         #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUHy3,
2088       #else
2089         #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
2090         #endif
2091           #else
2092       #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2093       #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
2094         #endif
2095     #if OPTION_RDIMMS
2096       #if OPTION_DDR2
2097         #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2098       #else
2099         #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2100       #endif
2101       #if OPTION_DDR3
2102         #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsRHy3,
2103         #else
2104         #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
2105         #endif
2106     #else
2107       #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2108       #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
2109       #endif
2110     #if OPTION_SODIMMS
2111       #if OPTION_DDR2
2112         #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2113       #else
2114         #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2115       #endif
2116       #if OPTION_DDR3
2117         #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsSHy3,
2118       #else
2119         #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
2120       #endif
2121       #else
2122       #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2123       #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
2124       #endif
2125       #else
2126     #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2127     #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2128     #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2129     #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
2130     #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
2131     #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
2132       #endif
2133   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
2134     PLAT_SP_HY_FF_UDIMM2
2135     PLAT_SP_HY_FF_RDIMM2
2136     PLAT_SP_HY_FF_SDIMM2
2137     PLAT_SP_HY_FF_UDIMM3
2138     PLAT_SP_HY_FF_RDIMM3
2139     PLAT_SP_HY_FF_SDIMM3
2140   };
2141
2142   #if OPTION_MEMCTLR_DR
2143     #if OPTION_UDIMMS
2144       #if OPTION_DDR2
2145         extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2;
2146         #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDr2,
2147       #else
2148         #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
2149       #endif
2150       #if OPTION_DDR3
2151         #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDr3,
2152       #else
2153         #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
2154       #endif
2155     #else
2156       #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
2157       #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
2158     #endif
2159     #if OPTION_RDIMMS
2160       #if OPTION_DDR2
2161         extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2;
2162         #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsRDr2,
2163   #else
2164         #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
2165   #endif
2166     #if OPTION_DDR3
2167         #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsRDr3,
2168       #else
2169         #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
2170       #endif
2171           #else
2172       #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
2173       #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
2174           #endif
2175     #if OPTION_SODIMMS
2176       #if OPTION_DDR2
2177         #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2178       #else
2179         #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2180         #endif
2181       #if OPTION_DDR3
2182         #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsSDr3,
2183       #else
2184         #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
2185       #endif
2186         #else
2187       #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2188       #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
2189         #endif
2190       #else
2191     #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2192     #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
2193     #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
2194     #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
2195     #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
2196     #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
2197       #endif
2198   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = {
2199     PLAT_SP_DR_FF_UDIMM2
2200     PLAT_SP_DR_FF_RDIMM2
2201     PLAT_SP_DR_FF_SDIMM2
2202     PLAT_SP_DR_FF_UDIMM3
2203     PLAT_SP_DR_FF_RDIMM3
2204     PLAT_SP_DR_FF_SDIMM3
2205   };
2206
2207   #if (OPTION_MEMCTLR_DA == TRUE)
2208     #if OPTION_UDIMMS
2209       #if OPTION_DDR2
2210         #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2211       #else
2212         #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2213       #endif
2214       #if OPTION_DDR3
2215         #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDA3,
2216       #else
2217         #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
2218       #endif
2219       #else
2220       #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2221       #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
2222       #endif
2223     #if OPTION_RDIMMS
2224       #if OPTION_DDR2
2225         #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2226       #else
2227         #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2228       #endif
2229       #if OPTION_DDR3
2230         #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2231       #else
2232         #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2233       #endif
2234     #else
2235       #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2236       #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2237     #endif
2238     #if OPTION_SODIMMS
2239       #if OPTION_DDR2
2240         #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsSDA2,
2241   #else
2242         #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
2243   #endif
2244     #if OPTION_DDR3
2245         #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsSDA3,
2246       #else
2247         #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
2248       #endif
2249       #else
2250       #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
2251       #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
2252         #endif
2253           #else
2254     #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
2255     #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2256     #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2257     #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
2258     #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2259     #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
2260         #endif
2261   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
2262     PLAT_SP_DA_FF_UDIMM2
2263     PLAT_SP_DA_FF_RDIMM2
2264     PLAT_SP_DA_FF_SDIMM2
2265     PLAT_SP_DA_FF_UDIMM3
2266     PLAT_SP_DA_FF_RDIMM3
2267     PLAT_SP_DA_FF_SDIMM3
2268   };
2269
2270   #if (OPTION_MEMCTLR_Ni == TRUE)
2271     #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
2272     #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
2273     #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
2274     #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsSNi3,
2275     #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
2276     #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUNi3,
2277       #else
2278     #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
2279     #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
2280     #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
2281     #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsUDef,
2282     #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
2283     #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUDef,
2284   #endif
2285   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
2286     PLAT_SP_NI_FF_UDIMM2
2287     PLAT_SP_NI_FF_RDIMM2
2288     PLAT_SP_NI_FF_SDIMM2
2289     PLAT_SP_NI_FF_UDIMM3
2290     PLAT_SP_NI_FF_RDIMM3
2291     PLAT_SP_NI_FF_SDIMM3
2292   };
2293
2294   #if (OPTION_MEMCTLR_PH == TRUE)
2295     #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
2296     #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
2297     #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
2298     #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsSPh3,
2299     #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
2300     #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUPh3,
2301         #else
2302     #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
2303     #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
2304     #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
2305     #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsUDef,
2306     #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
2307     #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUDef,
2308         #endif
2309   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
2310     PLAT_SP_PH_FF_UDIMM2
2311     PLAT_SP_PH_FF_RDIMM2
2312     PLAT_SP_PH_FF_SDIMM2
2313     PLAT_SP_PH_FF_UDIMM3
2314     PLAT_SP_PH_FF_RDIMM3
2315     PLAT_SP_PH_FF_SDIMM3
2316   };
2317
2318   #if (OPTION_MEMCTLR_RB == TRUE)
2319     #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
2320     #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
2321     #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
2322     #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsSRb3,
2323     #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
2324     #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsURb3,
2325   #else
2326     #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
2327     #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
2328     #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
2329     #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsUDef,
2330     #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
2331     #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsUDef,
2332       #endif
2333   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
2334     PLAT_SP_RB_FF_UDIMM2
2335     PLAT_SP_RB_FF_RDIMM2
2336     PLAT_SP_RB_FF_SDIMM2
2337     PLAT_SP_RB_FF_UDIMM3
2338     PLAT_SP_RB_FF_RDIMM3
2339     PLAT_SP_RB_FF_SDIMM3
2340   };
2341
2342   #if  OPTION_MEMCTLR_C32
2343     #if OPTION_UDIMMS
2344       #if OPTION_DDR2
2345         #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2346       #else
2347         #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2348       #endif
2349       #if OPTION_DDR3
2350         #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUC32_3,
2351       #else
2352         #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
2353       #endif
2354       #else
2355       #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2356       #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
2357       #endif
2358     #if OPTION_RDIMMS
2359       #if OPTION_DDR2
2360         #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2361       #else
2362         #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2363       #endif
2364       #if OPTION_DDR3
2365         #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsRC32_3,
2366       #else
2367         #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
2368       #endif
2369       #else
2370       #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2371       #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
2372       #endif
2373     #if OPTION_SODIMMS
2374       #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
2375       #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
2376     #endif
2377   #else
2378     #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
2379     #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2380     #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2381     #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
2382     #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
2383     #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
2384   #endif
2385   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
2386     PLAT_SP_C32_FF_UDIMM2
2387     PLAT_SP_C32_FF_RDIMM2
2388     PLAT_SP_C32_FF_SDIMM2
2389     PLAT_SP_C32_FF_UDIMM3
2390     PLAT_SP_C32_FF_RDIMM3
2391     PLAT_SP_C32_FF_SDIMM3
2392       };
2393
2394   /*---------------------------------------------------------------------------------------------------
2395    * PLATFORM-SPECIFIC CONFIGURATION
2396    *
2397    *
2398    *---------------------------------------------------------------------------------------------------
2399    */
2400
2401   #if OPTION_MEMCTLR_DR
2402     #if OPTION_UDIMMS
2403       #if OPTION_DDR2
2404         #define PSC_DR_UDIMM_DDR2     //MemAGetPsCfgUDr2
2405     #else
2406         #define PSC_DR_UDIMM_DDR2
2407       #endif
2408       #if OPTION_DDR3
2409         #define PSC_DR_UDIMM_DDR3    MemAGetPsCfgUDr3,
2410       #else
2411         #define PSC_DR_UDIMM_DDR3
2412       #endif
2413     #endif
2414     #if OPTION_RDIMMS
2415       #if OPTION_DDR2
2416         #define PSC_DR_RDIMM_DDR2    MemAGetPsCfgRDr2,
2417   #else
2418         #define PSC_DR_RDIMM_DDR2
2419   #endif
2420     #if OPTION_DDR3
2421         #define PSC_DR_RDIMM_DDR3    MemAGetPsCfgRDr3,
2422       #else
2423         #define PSC_DR_RDIMM_DDR3
2424       #endif
2425     #endif
2426     #if OPTION_SODIMMS
2427       #if OPTION_DDR2
2428         #define PSC_DR_SODIMM_DDR2    //MemAGetPsCfgSDr2
2429       #else
2430         #define PSC_DR_SODIMM_DDR2
2431       #endif
2432       #if OPTION_DDR3
2433         #define PSC_DR_SODIMM_DDR3    //MemAGetPsCfgSDr3
2434       #else
2435         #define PSC_DR_SODIMM_DDR3
2436         #endif
2437         #endif
2438   #endif
2439
2440   #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
2441     #if OPTION_MEMCTLR_Ni
2442       #define PSC_NI_UDIMM_DDR2
2443       #define PSC_NI_UDIMM_DDR3     MemAGetPsCfgUNi3,
2444       #define PSC_NI_RDIMM_DDR2
2445       #define PSC_NI_RDIMM_DDR3
2446       #define PSC_NI_SODIMM_DDR2
2447       #define PSC_NI_SODIMM_DDR3    MemAGetPsCfgSNi3,
2448     #endif
2449     #if OPTION_MEMCTLR_PH
2450       #define PSC_PH_UDIMM_DDR2
2451       #define PSC_PH_UDIMM_DDR3     MemAGetPsCfgUPh3,
2452       #define PSC_PH_RDIMM_DDR2
2453       #define PSC_PH_RDIMM_DDR3
2454       #define PSC_PH_SODIMM_DDR2
2455       #define PSC_PH_SODIMM_DDR3    MemAGetPsCfgSPh3,
2456     #endif
2457     #if OPTION_MEMCTLR_RB
2458       #define PSC_RB_UDIMM_DDR2
2459       #define PSC_RB_UDIMM_DDR3     MemAGetPsCfgURb3,
2460       #define PSC_RB_RDIMM_DDR2
2461       #define PSC_RB_RDIMM_DDR3
2462       #define PSC_RB_SODIMM_DDR2
2463       #define PSC_RB_SODIMM_DDR3    MemAGetPsCfgSRb3,
2464     #endif
2465     #if OPTION_MEMCTLR_DA
2466       #if OPTION_UDIMMS
2467         #if OPTION_DDR2
2468           #define PSC_DA_UDIMM_DDR2     //MemAGetPsCfgUDr2
2469         #else
2470           #define PSC_DA_UDIMM_DDR2
2471         #endif
2472         #if OPTION_DDR3
2473           #define PSC_DA_UDIMM_DDR3    MemAGetPsCfgUDA3,
2474           #else
2475           #define PSC_DA_UDIMM_DDR3
2476           #endif
2477         #endif
2478       #if OPTION_RDIMMS
2479         #if OPTION_DDR2
2480           #define PSC_DA_RDIMM_DDR2
2481       #else
2482           #define PSC_DA_RDIMM_DDR2
2483         #endif
2484         #if OPTION_DDR3
2485           #define PSC_DA_RDIMM_DDR3
2486         #else
2487           #define PSC_DA_RDIMM_DDR3
2488         #endif
2489       #endif
2490       #if OPTION_SODIMMS
2491         #if OPTION_DDR2
2492           #define PSC_DA_SODIMM_DDR2    MemAGetPsCfgSDA2,
2493       #else
2494           #define PSC_DA_SODIMM_DDR2
2495       #endif
2496         #if OPTION_DDR3
2497           #define PSC_DA_SODIMM_DDR3    MemAGetPsCfgSDA3,
2498       #else
2499           #define PSC_DA_SODIMM_DDR3
2500       #endif
2501       #endif
2502     #endif
2503   #endif
2504
2505   #if OPTION_MEMCTLR_HY
2506     #if OPTION_UDIMMS
2507       #if OPTION_DDR2
2508         #define PSC_HY_UDIMM_DDR2     //MemAGetPsCfgUDr2,
2509       #else
2510         #define PSC_HY_UDIMM_DDR2
2511       #endif
2512       #if OPTION_DDR3
2513         #define PSC_HY_UDIMM_DDR3    MemAGetPsCfgUHy3,
2514       #else
2515         #define PSC_HY_UDIMM_DDR3
2516       #endif
2517     #endif
2518     #if OPTION_RDIMMS
2519       #if OPTION_DDR2
2520         #define PSC_HY_RDIMM_DDR2
2521       #else
2522         #define PSC_HY_RDIMM_DDR2
2523       #endif
2524       #if OPTION_DDR3
2525         #define PSC_HY_RDIMM_DDR3    MemAGetPsCfgRHy3,
2526       #else
2527         #define PSC_HY_RDIMM_DDR3
2528       #endif
2529     #endif
2530     #if OPTION_SODIMMS
2531       #if OPTION_DDR2
2532         #define PSC_HY_SODIMM_DDR2    //MemAGetPsCfgSHy2,
2533     #else
2534         #define PSC_HY_SODIMM_DDR2
2535     #endif
2536       #if OPTION_DDR3
2537         #define PSC_HY_SODIMM_DDR3    //MemAGetPsCfgSHy3,
2538   #else
2539         #define PSC_HY_SODIMM_DDR3
2540       #endif
2541     #endif
2542   #endif
2543
2544   #if OPTION_MEMCTLR_C32
2545     #if OPTION_UDIMMS
2546       #if OPTION_DDR2
2547         #define PSC_C32_UDIMM_DDR2     //MemAGetPsCfgUDr2,
2548       #else
2549         #define PSC_C32_UDIMM_DDR2
2550       #endif
2551       #if OPTION_DDR3
2552         #define PSC_C32_UDIMM_DDR3    MemAGetPsCfgUC32_3,
2553       #else
2554         #define PSC_C32_UDIMM_DDR3
2555       #endif
2556     #endif
2557     #if OPTION_RDIMMS
2558       #if OPTION_DDR2
2559         #define PSC_C32_RDIMM_DDR2
2560       #else
2561         #define PSC_C32_RDIMM_DDR2
2562       #endif
2563       #if OPTION_DDR3
2564         #define PSC_C32_RDIMM_DDR3    MemAGetPsCfgRC32_3,
2565       #else
2566         #define PSC_C32_RDIMM_DDR3
2567       #endif
2568     #endif
2569     #if OPTION_SODIMMS
2570       #if OPTION_DDR2
2571         #define PSC_C32_SODIMM_DDR2    //MemAGetPsCfgSC32_2,
2572       #else
2573         #define PSC_C32_SODIMM_DDR2
2574       #endif
2575       #if OPTION_DDR3
2576         #define PSC_C32_SODIMM_DDR3    //MemAGetPsCfgSC32_3,
2577       #else
2578         #define PSC_C32_SODIMM_DDR3
2579       #endif
2580     #endif
2581   #endif
2582
2583   #if OPTION_MEMCTLR_OR
2584     #if OPTION_UDIMMS
2585       #if OPTION_DDR2
2586         #define PSC_OR_UDIMM_DDR2     //MemAGetPsCfgUOr2,
2587       #else
2588         #define PSC_OR_UDIMM_DDR2
2589       #endif
2590       #if OPTION_DDR3
2591         #define PSC_OR_UDIMM_DDR3     //MemAGetPsCfgUOr3,
2592       #else
2593         #define PSC_OR_UDIMM_DDR3
2594       #endif
2595     #endif
2596     #if OPTION_RDIMMS
2597       #if OPTION_DDR2
2598         #define PSC_OR_RDIMM_DDR2
2599       #else
2600         #define PSC_OR_RDIMM_DDR2
2601       #endif
2602       #if OPTION_DDR3
2603         #define PSC_OR_RDIMM_DDR3     //MemAGetPsCfgROr3,
2604       #else
2605         #define PSC_OR_RDIMM_DDR3
2606       #endif
2607     #endif
2608     #if OPTION_SODIMMS
2609       #if OPTION_DDR2
2610         #define PSC_OR_SODIMM_DDR2    //MemAGetPsCfgSOr2,
2611       #else
2612         #define PSC_OR_SODIMM_DDR2
2613       #endif
2614       #if OPTION_DDR3
2615         #define PSC_OR_SODIMM_DDR3    //MemAGetPsCfgSOr3,
2616       #else
2617         #define PSC_OR_SODIMM_DDR3
2618       #endif
2619     #endif
2620   #endif
2621
2622   /*----------------------------------------------------------------------
2623    * DEFAULT PSCFG DEFINITIONS
2624    *
2625    *----------------------------------------------------------------------
2626    */
2627
2628   #ifndef PSC_DR_UDIMM_DDR2
2629     #define PSC_DR_UDIMM_DDR2
2630       #endif
2631   #ifndef PSC_DR_RDIMM_DDR2
2632     #define PSC_DR_RDIMM_DDR2
2633     #endif
2634   #ifndef PSC_DR_SODIMM_DDR2
2635     #define PSC_DR_SODIMM_DDR2
2636       #endif
2637   #ifndef PSC_DR_UDIMM_DDR3
2638     #define PSC_DR_UDIMM_DDR3
2639       #endif
2640   #ifndef PSC_DR_RDIMM_DDR3
2641     #define PSC_DR_RDIMM_DDR3
2642     #endif
2643   #ifndef PSC_DR_SODIMM_DDR3
2644     #define PSC_DR_SODIMM_DDR3
2645       #endif
2646   #ifndef PSC_RB_UDIMM_DDR2
2647     #define PSC_RB_UDIMM_DDR2
2648       #endif
2649   #ifndef PSC_RB_RDIMM_DDR2
2650     #define PSC_RB_RDIMM_DDR2
2651     #endif
2652   #ifndef PSC_RB_SODIMM_DDR2
2653     #define PSC_RB_SODIMM_DDR2
2654   #endif
2655   #ifndef PSC_RB_UDIMM_DDR3
2656     #define PSC_RB_UDIMM_DDR3
2657   #endif
2658   #ifndef PSC_RB_RDIMM_DDR3
2659     #define PSC_RB_RDIMM_DDR3
2660   #endif
2661   #ifndef PSC_RB_SODIMM_DDR3
2662     #define PSC_RB_SODIMM_DDR3
2663   #endif
2664   #ifndef PSC_DA_UDIMM_DDR2
2665     #define PSC_DA_UDIMM_DDR2
2666       #endif
2667   #ifndef PSC_DA_RDIMM_DDR2
2668     #define PSC_DA_RDIMM_DDR2
2669     #endif
2670   #ifndef PSC_DA_SODIMM_DDR2
2671     #define PSC_DA_SODIMM_DDR2
2672       #endif
2673   #ifndef PSC_DA_UDIMM_DDR3
2674     #define PSC_DA_UDIMM_DDR3
2675     #endif
2676   #ifndef PSC_DA_RDIMM_DDR3
2677     #define PSC_DA_RDIMM_DDR3
2678   #endif
2679   #ifndef PSC_DA_SODIMM_DDR3
2680     #define PSC_DA_SODIMM_DDR3
2681       #endif
2682   #ifndef PSC_NI_UDIMM_DDR2
2683     #define PSC_NI_UDIMM_DDR2
2684       #endif
2685   #ifndef PSC_NI_RDIMM_DDR2
2686     #define PSC_NI_RDIMM_DDR2
2687     #endif
2688   #ifndef PSC_NI_SODIMM_DDR2
2689     #define PSC_NI_SODIMM_DDR2
2690       #endif
2691   #ifndef PSC_NI_UDIMM_DDR3
2692     #define PSC_NI_UDIMM_DDR3
2693       #endif
2694   #ifndef PSC_NI_RDIMM_DDR3
2695     #define PSC_NI_RDIMM_DDR3
2696     #endif
2697   #ifndef PSC_NI_SODIMM_DDR3
2698     #define PSC_NI_SODIMM_DDR3
2699     #endif
2700   #ifndef PSC_PH_UDIMM_DDR2
2701     #define PSC_PH_UDIMM_DDR2
2702   #endif
2703   #ifndef PSC_PH_RDIMM_DDR2
2704     #define PSC_PH_RDIMM_DDR2
2705       #endif
2706   #ifndef PSC_PH_SODIMM_DDR2
2707     #define PSC_PH_SODIMM_DDR2
2708     #endif
2709   #ifndef PSC_PH_UDIMM_DDR3
2710     #define PSC_PH_UDIMM_DDR3
2711       #endif
2712   #ifndef PSC_PH_RDIMM_DDR3
2713       #define PSC_PH_RDIMM_DDR3
2714     #endif
2715   #ifndef PSC_PH_SODIMM_DDR3
2716     #define PSC_PH_SODIMM_DDR3
2717   #endif
2718   #ifndef PSC_HY_UDIMM_DDR2
2719         #define PSC_HY_UDIMM_DDR2
2720       #endif
2721   #ifndef PSC_HY_RDIMM_DDR2
2722         #define PSC_HY_RDIMM_DDR2
2723       #endif
2724   #ifndef PSC_HY_SODIMM_DDR2
2725         #define PSC_HY_SODIMM_DDR2
2726       #endif
2727   #ifndef PSC_HY_UDIMM_DDR3
2728     #define PSC_HY_UDIMM_DDR3
2729       #endif
2730   #ifndef PSC_HY_RDIMM_DDR3
2731     #define PSC_HY_RDIMM_DDR3
2732     #endif
2733   #ifndef PSC_HY_SODIMM_DDR3
2734     #define PSC_HY_SODIMM_DDR3
2735   #endif
2736   #ifndef PSC_LN_UDIMM_DDR2
2737     #define PSC_LN_UDIMM_DDR2
2738       #endif
2739   #ifndef PSC_LN_RDIMM_DDR2
2740     #define PSC_LN_RDIMM_DDR2
2741       #endif
2742   #ifndef PSC_LN_SODIMM_DDR2
2743     #define PSC_LN_SODIMM_DDR2
2744     #endif
2745   #ifndef PSC_LN_UDIMM_DDR3
2746     #define PSC_LN_UDIMM_DDR3
2747       #endif
2748   #ifndef PSC_LN_RDIMM_DDR3
2749     #define PSC_LN_RDIMM_DDR3
2750       #endif
2751   #ifndef PSC_LN_SODIMM_DDR3
2752     #define PSC_LN_SODIMM_DDR3
2753     #endif
2754   #ifndef PSC_OR_UDIMM_DDR2
2755     #define PSC_OR_UDIMM_DDR2
2756       #endif
2757   #ifndef PSC_OR_RDIMM_DDR2
2758     #define PSC_OR_RDIMM_DDR2
2759       #endif
2760   #ifndef PSC_OR_SODIMM_DDR2
2761     #define PSC_OR_SODIMM_DDR2
2762     #endif
2763   #ifndef PSC_OR_UDIMM_DDR3
2764     #define PSC_OR_UDIMM_DDR3
2765   #endif
2766   #ifndef PSC_OR_RDIMM_DDR3
2767     #define PSC_OR_RDIMM_DDR3
2768       #endif
2769   #ifndef PSC_OR_SODIMM_DDR3
2770     #define PSC_OR_SODIMM_DDR3
2771       #endif
2772   #ifndef PSC_C32_UDIMM_DDR3
2773     #define PSC_C32_UDIMM_DDR3
2774     #endif
2775   #ifndef PSC_C32_RDIMM_DDR3
2776     #define PSC_C32_RDIMM_DDR3
2777       #endif
2778   #ifndef PSC_ON_UDIMM_DDR2
2779     #define PSC_ON_UDIMM_DDR2
2780       #endif
2781   #ifndef PSC_ON_RDIMM_DDR2
2782     #define PSC_ON_RDIMM_DDR2
2783     #endif
2784   #ifndef PSC_ON_SODIMM_DDR2
2785     #define PSC_ON_SODIMM_DDR2
2786       #endif
2787   #ifndef PSC_ON_UDIMM_DDR3
2788     #define PSC_ON_UDIMM_DDR3
2789       #endif
2790   #ifndef PSC_ON_RDIMM_DDR3
2791     #define PSC_ON_RDIMM_DDR3
2792     #endif
2793   #ifndef PSC_ON_SODIMM_DDR3
2794     #define PSC_ON_SODIMM_DDR3
2795   #endif
2796
2797   MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
2798     PSC_DR_UDIMM_DDR2
2799     PSC_DR_RDIMM_DDR2
2800     PSC_DR_SODIMM_DDR2
2801     PSC_DR_UDIMM_DDR3
2802     PSC_DR_RDIMM_DDR3
2803     PSC_DR_SODIMM_DDR3
2804     PSC_RB_UDIMM_DDR3
2805     PSC_RB_SODIMM_DDR3
2806     PSC_DA_SODIMM_DDR2
2807     PSC_DA_UDIMM_DDR3
2808     PSC_DA_SODIMM_DDR3
2809     PSC_NI_UDIMM_DDR3
2810     PSC_NI_SODIMM_DDR3
2811     PSC_PH_UDIMM_DDR3
2812     PSC_PH_SODIMM_DDR3
2813     PSC_HY_UDIMM_DDR3
2814     PSC_HY_RDIMM_DDR3
2815     PSC_HY_SODIMM_DDR3
2816     PSC_LN_UDIMM_DDR3
2817     PSC_LN_RDIMM_DDR3
2818     PSC_LN_SODIMM_DDR3
2819     PSC_OR_UDIMM_DDR3
2820     PSC_OR_RDIMM_DDR3
2821     PSC_OR_SODIMM_DDR3
2822     PSC_C32_UDIMM_DDR3
2823     PSC_C32_RDIMM_DDR3
2824     PSC_ON_UDIMM_DDR3
2825     PSC_ON_RDIMM_DDR3
2826     PSC_ON_SODIMM_DDR3
2827     NULL
2828   };
2829   CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
2830 //  #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
2831 //    #error   Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
2832 //  #endif
2833
2834   /*---------------------------------------------------------------------------------------------------
2835    * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
2836    *
2837    *
2838    *---------------------------------------------------------------------------------------------------
2839    */
2840   #define MEM_PSC_FLOW_BLOCK_END NULL
2841   #define PSC_TBL_END NULL
2842   #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
2843
2844   #if OPTION_MEMCTLR_OR
2845     #if OPTION_UDIMMS
2846       #if OPTION_AM3_SOCKET_SUPPORT
2847         extern PSC_TBL_ENTRY MaxFreqTblEntUAM3;
2848         #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3  &MaxFreqTblEntUAM3,
2849         extern PSC_TBL_ENTRY DramTermTblEntUAM3;
2850         #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3  &DramTermTblEntUAM3,
2851         extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3;
2852         #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3  &OdtPat1DTblEntUAM3,
2853         extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3;
2854         #define PSC_TBL_OR_UDIMM3_ODT_PAT____AM3  &OdtPat2DTblEntUAM3,
2855         extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3;
2856         #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3  &OdtPat3DTblEntUAM3,
2857         extern PSC_TBL_ENTRY SAOTblEntUAM3;
2858         #define PSC_TBL_OR_UDIMM3_SAO_AM3  &SAOTblEntUAM3,
2859         extern PSC_TBL_ENTRY ClkDisMapEntUAM3;
2860         #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3,
2861         extern PSC_TBL_ENTRY S__TblEntUAM3;
2862         #define PSC_TBL_OR_UDIMM3_S___AM3  &S__TblEntUAM3,
2863         extern PSC_TBL_ENTRY WLPass1SeedEntUAM3;
2864         #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3  &WLPass1SeedEntUAM3,
2865         extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUAM3;
2866         #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3  &HWRxEnPass1SeedEntUAM3,
2867       #endif
2868       #if OPTION_C32_SOCKET_SUPPORT
2869         extern PSC_TBL_ENTRY MaxFreqTblEntUC32;
2870         #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32  &MaxFreqTblEntUC32,
2871         extern PSC_TBL_ENTRY DramTermTblEntUC32;
2872         #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32  &DramTermTblEntUC32,
2873         extern PSC_TBL_ENTRY OdtPat1DTblEntUC32;
2874         #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntUC32,
2875         extern PSC_TBL_ENTRY OdtPat2DTblEntUC32;
2876         #define PSC_TBL_OR_UDIMM3_ODT_PAT____C32  &OdtPat2DTblEntUC32,
2877         extern PSC_TBL_ENTRY OdtPat3DTblEntUC32;
2878         #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntUC32,
2879         extern PSC_TBL_ENTRY SAOTblEntUC32;
2880         #define PSC_TBL_OR_UDIMM3_SAO_C32  &SAOTblEntUC32,
2881         extern PSC_TBL_ENTRY ClkDisMapEntUC32;
2882         #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32,
2883         extern PSC_TBL_ENTRY ClkDisMap3DEntUC32;
2884         #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32,
2885         extern PSC_TBL_ENTRY S__TblEntUC32;
2886         #define PSC_TBL_OR_UDIMM3_S___C32  &S__TblEntUC32,
2887         extern PSC_TBL_ENTRY WLPass1SeedEntUC32;
2888         #define PSC_TBL_OR_UDIMM3_WL_SEED_C32  &WLPass1SeedEntUC32,
2889         extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUC32;
2890         #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32  &HWRxEnPass1SeedEntUC32,
2891       #endif
2892       #if OPTION_G34_SOCKET_SUPPORT
2893         extern PSC_TBL_ENTRY MaxFreqTblEntUG34;
2894         #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34  &MaxFreqTblEntUG34,
2895         extern PSC_TBL_ENTRY DramTermTblEntUG34;
2896         #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34  &DramTermTblEntUG34,
2897         extern PSC_TBL_ENTRY OdtPat1DTblEntUG34;
2898         #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntUG34,
2899         extern PSC_TBL_ENTRY OdtPat2DTblEntUG34;
2900         #define PSC_TBL_OR_UDIMM3_ODT_PAT____G34  &OdtPat2DTblEntUG34,
2901         extern PSC_TBL_ENTRY OdtPat3DTblEntUG34;
2902         #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntUG34,
2903         extern PSC_TBL_ENTRY SAOTblEntUG34;
2904         #define PSC_TBL_OR_UDIMM3_SAO_G34  &SAOTblEntUG34,
2905         extern PSC_TBL_ENTRY ClkDisMapEntUG34;
2906         #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34,
2907         extern PSC_TBL_ENTRY S__TblEntUG34;
2908         #define PSC_TBL_OR_UDIMM3_S___G34  &S__TblEntUG34,
2909         extern PSC_TBL_ENTRY WLPass1SeedEntUG34;
2910         #define PSC_TBL_OR_UDIMM3_WL_SEED_G34  &WLPass1SeedEntUG34,
2911         extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUG34;
2912         #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34  &HWRxEnPass1SeedEntUG34,
2913     #endif
2914     #endif
2915     #if OPTION_RDIMMS
2916       #if OPTION_C32_SOCKET_SUPPORT
2917         extern PSC_TBL_ENTRY MaxFreqTblEntRC32;
2918         #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32  &MaxFreqTblEntRC32,
2919         extern PSC_TBL_ENTRY DramTermTblEntRC32;
2920         #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32  &DramTermTblEntRC32,
2921         extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
2922         #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntRC32,
2923         extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
2924         #define PSC_TBL_OR_RDIMM3_ODT_PAT____C32  &OdtPat2DTblEntRC32,
2925         extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
2926         #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntRC32,
2927         extern PSC_TBL_ENTRY SAOTblEntRC32;
2928         #define PSC_TBL_OR_RDIMM3_SAO_C32  &SAOTblEntRC32,
2929         extern PSC_TBL_ENTRY RC2IBTTblEntRC32;
2930         #define PSC_TBL_OR_RDIMM3_RC2IBT_C32  &RC2IBTTblEntRC32,
2931         extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32;
2932         #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32  &RC10OpSpdTblEntRC32,
2933         extern PSC_TBL_ENTRY ClkDisMapEntRC32;
2934         #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32,
2935         extern PSC_TBL_ENTRY S__TblEntRC32;
2936         #define PSC_TBL_OR_RDIMM3_S___C32  &S__TblEntRC32,
2937         extern PSC_TBL_ENTRY WLPass1SeedEntRC32;
2938         #define PSC_TBL_OR_RDIMM3_WL_SEED_C32  &WLPass1SeedEntRC32,
2939         extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRC32;
2940         #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32  &HWRxEnPass1SeedEntRC32,
2941     #endif
2942       #if OPTION_G34_SOCKET_SUPPORT
2943         extern PSC_TBL_ENTRY MaxFreqTblEntRG34;
2944         #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34  &MaxFreqTblEntRG34,
2945         extern PSC_TBL_ENTRY DramTermTblEntRG34;
2946         #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34  &DramTermTblEntRG34,
2947         extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
2948         #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntRG34,
2949         extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
2950         #define PSC_TBL_OR_RDIMM3_ODT_PAT____G34  &OdtPat2DTblEntRG34,
2951         extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
2952         #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntRG34,
2953         extern PSC_TBL_ENTRY SAOTblEntRG34;
2954         #define PSC_TBL_OR_RDIMM3_SAO_G34  &SAOTblEntRG34,
2955         extern PSC_TBL_ENTRY RC2IBTTblEntRG34;
2956         #define PSC_TBL_OR_RDIMM3_RC2IBT_G34  &RC2IBTTblEntRG34,
2957         extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34;
2958         #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34  &RC10OpSpdTblEntRG34,
2959         extern PSC_TBL_ENTRY ClkDisMapEntRG34;
2960         #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34,
2961         extern PSC_TBL_ENTRY S__TblEntRG34;
2962         #define PSC_TBL_OR_RDIMM3_S___G34  &S__TblEntRG34,
2963         extern PSC_TBL_ENTRY WLPass1SeedEntRG34;
2964         #define PSC_TBL_OR_RDIMM3_WL_SEED_G34  &WLPass1SeedEntRG34,
2965         extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRG34;
2966         #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34  &HWRxEnPass1SeedEntRG34,
2967     #endif
2968     #endif
2969     //#if OPTION_SODIMMS
2970     //#endif
2971     #if OPTION_LRDIMMS
2972       #if OPTION_C32_SOCKET_SUPPORT
2973         extern PSC_TBL_ENTRY MaxFreqTblEntLRC32;
2974         #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32  &MaxFreqTblEntLRC32,
2975         extern PSC_TBL_ENTRY DramTermTblEntLRC32;
2976         #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32  &DramTermTblEntLRC32,
2977         extern PSC_TBL_ENTRY OdtPat1DTblEntLRC32;
2978         #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntLRC32,
2979         extern PSC_TBL_ENTRY OdtPat2DTblEntLRC32;
2980         #define PSC_TBL_OR_LRDIMM3_ODT_PAT____C32  &OdtPat2DTblEntLRC32,
2981         extern PSC_TBL_ENTRY OdtPat3DTblEntLRC32;
2982         #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntLRC32,
2983         extern PSC_TBL_ENTRY SAOTblEntLRC32;
2984         #define PSC_TBL_OR_LRDIMM3_SAO_C32  &SAOTblEntLRC32,
2985         extern PSC_TBL_ENTRY IBTTblEntLRC32;
2986         #define PSC_TBL_OR_LRDIMM3_IBT_C32  &IBTTblEntLRC32,
2987         extern PSC_TBL_ENTRY ClkDisMapEntLRC32;
2988         #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32,
2989         extern PSC_TBL_ENTRY S__TblEntLRC32;
2990         #define PSC_TBL_OR_LRDIMM3_S___C32  &S__TblEntLRC32,
2991         extern PSC_TBL_ENTRY WLPass1SeedEntLRC32;
2992         #define PSC_TBL_OR_LRDIMM3_WL_SEED_C32  &WLPass1SeedEntLRC32,
2993         extern PSC_TBL_ENTRY HWRxEnPass1SeedEntLRC32;
2994         #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntLRC32,
2995     #endif
2996       #if OPTION_G34_SOCKET_SUPPORT
2997         extern PSC_TBL_ENTRY MaxFreqTblEntLRG34;
2998         #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34  &MaxFreqTblEntLRG34,
2999         extern PSC_TBL_ENTRY DramTermTblEntLRG34;
3000         #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34  &DramTermTblEntLRG34,
3001         extern PSC_TBL_ENTRY OdtPat1DTblEntLRG34;
3002         #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntLRG34,
3003         extern PSC_TBL_ENTRY OdtPat2DTblEntLRG34;
3004         #define PSC_TBL_OR_LRDIMM3_ODT_PAT____G34  &OdtPat2DTblEntLRG34,
3005         extern PSC_TBL_ENTRY OdtPat3DTblEntLRG34;
3006         #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntLRG34,
3007         extern PSC_TBL_ENTRY SAOTblEntLRG34;
3008         #define PSC_TBL_OR_LRDIMM3_SAO_G34  &SAOTblEntLRG34,
3009         extern PSC_TBL_ENTRY IBTTblEntLRG34;
3010         #define PSC_TBL_OR_LRDIMM3_IBT_G34  &IBTTblEntLRG34,
3011         extern PSC_TBL_ENTRY ClkDisMapEntLRG34;
3012         #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34,
3013         extern PSC_TBL_ENTRY S__TblEntLRG34;
3014         #define PSC_TBL_OR_LRDIMM3_S___G34  &S__TblEntLRG34,
3015         extern PSC_TBL_ENTRY WLPass1SeedEntLRG34;
3016         #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34  &WLPass1SeedEntLRG34,
3017         extern PSC_TBL_ENTRY HWRxEnPass1SeedEntLRG34;
3018         #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntLRG34,
3019     #endif
3020     #endif
3021     extern PSC_TBL_ENTRY MR0WrTblEntry;
3022     #define PSC_TBL_OR_MR0_WR  &MR0WrTblEntry,
3023     extern PSC_TBL_ENTRY MR0CLTblEntry;
3024     #define PSC_TBL_OR_MR0_CL  &MR0CLTblEntry,
3025     extern PSC_TBL_ENTRY OrDdr3CKETriEnt;
3026     #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt,
3027     extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt;
3028     #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt,
3029     extern PSC_TBL_ENTRY OrDdr3ODTTriEnt;
3030     #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt,
3031     extern PSC_TBL_ENTRY OrUDdr3CSTriEnt;
3032     #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt,
3033     extern PSC_TBL_ENTRY OrDdr3CSTriEnt;
3034     #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt,
3035     extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt;
3036     #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt,
3037     extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt;
3038     #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt,
3039
3040     #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
3041       #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
3042     #endif
3043     #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
3044       #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
3045     #endif
3046     #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
3047       #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
3048     #endif
3049     #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
3050       #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
3051     #endif
3052     #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
3053       #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
3054     #endif
3055     #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
3056       #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
3057     #endif
3058     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
3059       #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
3060     #endif
3061     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
3062       #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
3063     #endif
3064     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
3065       #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
3066     #endif
3067     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____AM3
3068       #define PSC_TBL_OR_UDIMM3_ODT_PAT____AM3
3069     #endif
3070     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____C32
3071       #define PSC_TBL_OR_UDIMM3_ODT_PAT____C32
3072     #endif
3073     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____G34
3074       #define PSC_TBL_OR_UDIMM3_ODT_PAT____G34
3075   #endif
3076     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
3077       #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
3078       #endif
3079     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
3080       #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
3081     #endif
3082     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
3083       #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
3084       #endif
3085     #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3
3086       #define PSC_TBL_OR_UDIMM3_SAO_AM3
3087     #endif
3088     #ifndef PSC_TBL_OR_UDIMM3_SAO_C32
3089       #define PSC_TBL_OR_UDIMM3_SAO_C32
3090       #endif
3091     #ifndef PSC_TBL_OR_UDIMM3_SAO_G34
3092       #define PSC_TBL_OR_UDIMM3_SAO_G34
3093     #endif
3094     #ifndef PSC_TBL_OR_UDIMM3_S___AM3
3095       #define PSC_TBL_OR_UDIMM3_S___AM3
3096     #endif
3097     #ifndef PSC_TBL_OR_UDIMM3_S___C32
3098       #define PSC_TBL_OR_UDIMM3_S___C32
3099     #endif
3100     #ifndef PSC_TBL_OR_UDIMM3_S___G34
3101       #define PSC_TBL_OR_UDIMM3_S___G34
3102     #endif
3103     #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_AM3
3104       #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3
3105     #endif
3106     #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_C32
3107       #define PSC_TBL_OR_UDIMM3_WL_SEED_C32
3108     #endif
3109     #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_G34
3110       #define PSC_TBL_OR_UDIMM3_WL_SEED_G34
3111     #endif
3112     #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3
3113       #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3
3114     #endif
3115     #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32
3116       #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32
3117     #endif
3118     #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34
3119       #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34
3120     #endif
3121     #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
3122       #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
3123     #endif
3124     #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
3125       #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
3126     #endif
3127     #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
3128       #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
3129     #endif
3130     #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
3131       #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
3132     #endif
3133     #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
3134       #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
3135     #endif
3136     #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
3137       #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
3138     #endif
3139     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
3140       #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
3141     #endif
3142     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
3143       #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
3144     #endif
3145     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
3146       #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
3147     #endif
3148     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT____AM3
3149       #define PSC_TBL_OR_RDIMM3_ODT_PAT____AM3
3150     #endif
3151     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT____C32
3152       #define PSC_TBL_OR_RDIMM3_ODT_PAT____C32
3153     #endif
3154     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT____G34
3155       #define PSC_TBL_OR_RDIMM3_ODT_PAT____G34
3156     #endif
3157     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
3158       #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
3159     #endif
3160     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
3161       #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
3162     #endif
3163     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
3164       #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
3165     #endif
3166     #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3
3167       #define PSC_TBL_OR_RDIMM3_SAO_AM3
3168     #endif
3169     #ifndef PSC_TBL_OR_RDIMM3_SAO_C32
3170       #define PSC_TBL_OR_RDIMM3_SAO_C32
3171     #endif
3172     #ifndef PSC_TBL_OR_RDIMM3_SAO_G34
3173       #define PSC_TBL_OR_RDIMM3_SAO_G34
3174     #endif
3175     #ifndef PSC_TBL_OR_RDIMM3_S___AM3
3176       #define PSC_TBL_OR_RDIMM3_S___AM3
3177     #endif
3178     #ifndef PSC_TBL_OR_RDIMM3_S___C32
3179       #define PSC_TBL_OR_RDIMM3_S___C32
3180     #endif
3181     #ifndef PSC_TBL_OR_RDIMM3_S___G34
3182       #define PSC_TBL_OR_RDIMM3_S___G34
3183     #endif
3184     #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3
3185       #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3
3186     #endif
3187     #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32
3188       #define PSC_TBL_OR_RDIMM3_RC2IBT_C32
3189     #endif
3190     #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34
3191       #define PSC_TBL_OR_RDIMM3_RC2IBT_G34
3192     #endif
3193     #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
3194       #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
3195     #endif
3196     #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
3197       #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
3198     #endif
3199     #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
3200       #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
3201     #endif
3202     #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_AM3
3203       #define PSC_TBL_OR_RDIMM3_WL_SEED_AM3
3204     #endif
3205     #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_C32
3206       #define PSC_TBL_OR_RDIMM3_WL_SEED_C32
3207     #endif
3208     #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_G34
3209       #define PSC_TBL_OR_RDIMM3_WL_SEED_G34
3210     #endif
3211     #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3
3212       #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3
3213     #endif
3214     #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32
3215       #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32
3216     #endif
3217     #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34
3218       #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34
3219     #endif
3220     #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
3221       #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
3222     #endif
3223     #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
3224       #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
3225     #endif
3226     #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
3227       #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
3228     #endif
3229     #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
3230       #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
3231     #endif
3232     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
3233       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
3234     #endif
3235     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
3236       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
3237     #endif
3238     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT____C32
3239       #define PSC_TBL_OR_LRDIMM3_ODT_PAT____C32
3240     #endif
3241     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT____G34
3242       #define PSC_TBL_OR_LRDIMM3_ODT_PAT____G34
3243     #endif
3244     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
3245       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
3246     #endif
3247     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
3248       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
3249     #endif
3250     #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32
3251       #define PSC_TBL_OR_LRDIMM3_SAO_C32
3252     #endif
3253     #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34
3254       #define PSC_TBL_OR_LRDIMM3_SAO_G34
3255     #endif
3256     #ifndef PSC_TBL_OR_LRDIMM3_S___C32
3257       #define PSC_TBL_OR_LRDIMM3_S___C32
3258     #endif
3259     #ifndef PSC_TBL_OR_LRDIMM3_S___G34
3260       #define PSC_TBL_OR_LRDIMM3_S___G34
3261     #endif
3262     #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32
3263       #define PSC_TBL_OR_LRDIMM3_IBT_C32
3264     #endif
3265     #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34
3266       #define PSC_TBL_OR_LRDIMM3_IBT_G34
3267     #endif
3268     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
3269       #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
3270     #endif
3271     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32
3272       #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32
3273     #endif
3274     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
3275       #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
3276     #endif
3277     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34
3278       #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34
3279     #endif
3280     #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32
3281       #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32
3282     #endif
3283     #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34
3284       #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34
3285     #endif
3286     #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
3287       #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
3288     #endif
3289     #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
3290       #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
3291     #endif
3292     #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_AM3
3293       #define PSC_TBL_OR_LRDIMM3_WL_SEED_AM3
3294     #endif
3295     #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_C32
3296       #define PSC_TBL_OR_LRDIMM3_WL_SEED_C32
3297     #endif
3298     #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_G34
3299       #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34
3300     #endif
3301     #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3
3302       #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3
3303     #endif
3304     #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32
3305       #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32
3306     #endif
3307     #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34
3308       #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34
3309     #endif
3310
3311
3312     PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = {
3313       PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
3314       PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
3315       PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
3316       PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
3317       PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
3318       PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
3319       PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
3320       PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
3321       PSC_TBL_END
3322     };
3323
3324     PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = {
3325       PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
3326       PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
3327       PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
3328       PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
3329       PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
3330       PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
3331       PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
3332       PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
3333       PSC_TBL_END
3334     };
3335
3336     PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = {
3337       PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
3338       PSC_TBL_OR_UDIMM3_ODT_PAT____AM3
3339       PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
3340       PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
3341       PSC_TBL_OR_RDIMM3_ODT_PAT____AM3
3342       PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
3343       PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
3344       PSC_TBL_OR_UDIMM3_ODT_PAT____C32
3345       PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
3346       PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
3347       PSC_TBL_OR_RDIMM3_ODT_PAT____C32
3348       PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
3349       PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
3350       PSC_TBL_OR_LRDIMM3_ODT_PAT____C32
3351       PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
3352       PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
3353       PSC_TBL_OR_UDIMM3_ODT_PAT____G34
3354       PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
3355       PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
3356       PSC_TBL_OR_RDIMM3_ODT_PAT____G34
3357       PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
3358       PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
3359       PSC_TBL_OR_LRDIMM3_ODT_PAT____G34
3360       PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
3361       PSC_TBL_END
3362     };
3363
3364     PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = {
3365       PSC_TBL_OR_UDIMM3_SAO_AM3
3366       PSC_TBL_OR_UDIMM3_SAO_C32
3367       PSC_TBL_OR_UDIMM3_SAO_G34
3368       PSC_TBL_OR_RDIMM3_SAO_AM3
3369       PSC_TBL_OR_RDIMM3_SAO_C32
3370       PSC_TBL_OR_RDIMM3_SAO_G34
3371       PSC_TBL_OR_LRDIMM3_SAO_C32
3372       PSC_TBL_OR_LRDIMM3_SAO_G34
3373       PSC_TBL_END
3374     };
3375
3376     PSC_TBL_ENTRY* memPSCTblS__ArrayOR[] = {
3377       PSC_TBL_OR_UDIMM3_S___AM3
3378       PSC_TBL_OR_UDIMM3_S___C32
3379       PSC_TBL_OR_UDIMM3_S___G34
3380       PSC_TBL_OR_RDIMM3_S___AM3
3381       PSC_TBL_OR_RDIMM3_S___C32
3382       PSC_TBL_OR_RDIMM3_S___G34
3383       PSC_TBL_OR_LRDIMM3_S___C32
3384       PSC_TBL_OR_LRDIMM3_S___G34
3385       PSC_TBL_END
3386     };
3387
3388     PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = {
3389       PSC_TBL_OR_MR0_WR
3390       PSC_TBL_END
3391     };
3392
3393     PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = {
3394       PSC_TBL_OR_MR0_CL
3395       PSC_TBL_END
3396     };
3397
3398     PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = {
3399       PSC_TBL_OR_RDIMM3_RC2IBT_AM3
3400       PSC_TBL_OR_RDIMM3_RC2IBT_C32
3401       PSC_TBL_OR_RDIMM3_RC2IBT_G34
3402       PSC_TBL_END
3403     };
3404
3405     PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = {
3406       PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
3407       PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
3408       PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
3409       PSC_TBL_END
3410     };
3411
3412     PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = {
3413       PSC_TBL_OR_LRDIMM3_IBT_C32
3414       PSC_TBL_OR_LRDIMM3_IBT_G34
3415       PSC_TBL_END
3416     };
3417
3418     PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = {
3419       PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
3420       PSC_TBL_OR_UDIMM3_CLK_DIS_C32
3421       PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
3422       PSC_TBL_OR_UDIMM3_CLK_DIS_G34
3423       PSC_TBL_OR_RDIMM3_CLK_DIS_C32
3424       PSC_TBL_OR_RDIMM3_CLK_DIS_G34
3425       PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
3426       PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
3427       PSC_TBL_OR_CKE_TRI
3428       PSC_TBL_OR_ODT_TRI_3D
3429       PSC_TBL_OR_ODT_TRI
3430       PSC_TBL_OR_LRDIMM3_ODT_TRI_3D
3431       PSC_TBL_OR_LRDIMM3_ODT_TRI
3432       PSC_TBL_OR_UDIMM3_CS_TRI
3433       PSC_TBL_OR_CS_TRI
3434       PSC_TBL_END
3435     };
3436
3437     PSC_TBL_ENTRY* memPSCTblWLSeedArrayOR[] = {
3438       PSC_TBL_OR_UDIMM3_WL_SEED_AM3
3439       PSC_TBL_OR_UDIMM3_WL_SEED_C32
3440       PSC_TBL_OR_UDIMM3_WL_SEED_G34
3441       PSC_TBL_OR_RDIMM3_WL_SEED_AM3
3442       PSC_TBL_OR_RDIMM3_WL_SEED_C32
3443       PSC_TBL_OR_RDIMM3_WL_SEED_G34
3444       PSC_TBL_OR_LRDIMM3_WL_SEED_AM3
3445       PSC_TBL_OR_LRDIMM3_WL_SEED_C32
3446       PSC_TBL_OR_LRDIMM3_WL_SEED_G34
3447       PSC_TBL_END
3448     };
3449
3450     PSC_TBL_ENTRY* memPSCTblHWRxEnSeedArrayOR[] = {
3451       PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3
3452       PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32
3453       PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34
3454       PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3
3455       PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32
3456       PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34
3457       PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3
3458       PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32
3459       PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34
3460       PSC_TBL_END
3461     };
3462
3463     MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = {
3464       (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR,
3465       (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR,
3466       (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR,
3467       (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR,
3468       (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR,
3469       (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR,
3470       (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR,
3471       (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR,
3472       (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR,
3473       NULL,
3474       NULL,
3475       (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR,
3476       (PSC_TBL_ENTRY **)&memPSCTblS__ArrayOR,
3477       (PSC_TBL_ENTRY **)&memPSCTblWLSeedArrayOR,
3478       (PSC_TBL_ENTRY **)&memPSCTblHWRxEnSeedArrayOR
3479     };
3480
3481     extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
3482     #define PSC_FLOW_OR_MAX_FREQ   MemPGetMaxFreqSupported
3483     extern MEM_PSC_FLOW MemPGetRttNomWr;
3484     #define PSC_FLOW_OR_DRAM_TERM   MemPGetRttNomWr
3485     extern MEM_PSC_FLOW MemPGetODTPattern;
3486     #define PSC_FLOW_OR_ODT_PATTERN   MemPGetODTPattern
3487     extern MEM_PSC_FLOW MemPGetSAO;
3488     #define PSC_FLOW_OR_SAO   MemPGetSAO
3489     extern MEM_PSC_FLOW MemPGetMR0WrCL;
3490     #define PSC_FLOW_OR_MR0_WRCL   MemPGetMR0WrCL
3491     extern MEM_PSC_FLOW MemPGetS__;
3492     #define PSC_FLOW_OR_S__   MemPGetS__
3493     extern MEM_PSC_FLOW MemPGetTrainingSeeds;
3494     #define PSC_FLOW_OR_SEED MemPGetTrainingSeeds
3495     #if OPTION_RDIMMS
3496       extern MEM_PSC_FLOW MemPGetRC2IBT;
3497       #define PSC_FLOW_OR_RC2_IBT    MemPGetRC2IBT
3498       extern MEM_PSC_FLOW MemPGetRC10OpSpd;
3499       #define PSC_FLOW_OR_RC10_OPSPD   MemPGetRC10OpSpd
3500     #endif
3501     #if OPTION_LRDIMMS
3502       extern MEM_PSC_FLOW MemPGetLRIBT;
3503       #define PSC_FLOW_OR_LR_IBT   MemPGetLRIBT
3504       extern MEM_PSC_FLOW MemPGetLRNPR;
3505       #define PSC_FLOW_OR_LR_NPR   MemPGetLRNPR
3506       extern MEM_PSC_FLOW MemPGetLRNLR;
3507       #define PSC_FLOW_OR_LR_NLR  MemPGetLRNLR
3508     #endif
3509     #ifndef PSC_FLOW_OR_MAX_FREQ
3510       #define PSC_FLOW_OR_MAX_FREQ   MEM_PSC_FLOW_DEFTRUE
3511     #endif
3512     #ifndef PSC_FLOW_OR_DRAM_TERM
3513       #define PSC_FLOW_OR_DRAM_TERM   MEM_PSC_FLOW_DEFTRUE
3514     #endif
3515     #ifndef PSC_FLOW_OR_ODT_PATTERN
3516       #define PSC_FLOW_OR_ODT_PATTERN   MEM_PSC_FLOW_DEFTRUE
3517     #endif
3518     #ifndef PSC_FLOW_OR_SAO
3519       #define PSC_FLOW_OR_SAO   MEM_PSC_FLOW_DEFTRUE
3520     #endif
3521     #ifndef PSC_FLOW_OR_MR0_WRCL
3522       #define PSC_FLOW_OR_MR0_WRCL   MEM_PSC_FLOW_DEFTRUE
3523     #endif
3524     #ifndef PSC_FLOW_OR_RC2_IBT
3525       #define PSC_FLOW_OR_RC2_IBT   MEM_PSC_FLOW_DEFTRUE
3526     #endif
3527     #ifndef PSC_FLOW_OR_RC10_OPSPD
3528       #define PSC_FLOW_OR_RC10_OPSPD   MEM_PSC_FLOW_DEFTRUE
3529     #endif
3530     #ifndef PSC_FLOW_OR_LR_IBT
3531       #define PSC_FLOW_OR_LR_IBT   MEM_PSC_FLOW_DEFTRUE
3532     #endif
3533     #ifndef PSC_FLOW_OR_LR_NPR
3534       #define PSC_FLOW_OR_LR_NPR   MEM_PSC_FLOW_DEFTRUE
3535     #endif
3536     #ifndef PSC_FLOW_OR_LR_NLR
3537       #define PSC_FLOW_OR_LR_NLR   MEM_PSC_FLOW_DEFTRUE
3538   #endif
3539     #ifndef PSC_FLOW_OR_S__
3540       #define PSC_FLOW_OR_S__   MEM_PSC_FLOW_DEFTRUE
3541     #endif
3542     #ifndef PSC_FLOW_OR_SEED
3543       #define PSC_FLOW_OR_SEED   MEM_PSC_FLOW_DEFTRUE
3544     #endif
3545
3546     MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = {
3547       &memPSCTblBlockOr,
3548       PSC_FLOW_OR_MAX_FREQ,
3549       PSC_FLOW_OR_DRAM_TERM,
3550       PSC_FLOW_OR_ODT_PATTERN,
3551       PSC_FLOW_OR_SAO,
3552       PSC_FLOW_OR_MR0_WRCL,
3553       PSC_FLOW_OR_RC2_IBT,
3554       PSC_FLOW_OR_RC10_OPSPD,
3555       PSC_FLOW_OR_LR_IBT,
3556       PSC_FLOW_OR_LR_NPR,
3557       PSC_FLOW_OR_LR_NLR,
3558       PSC_FLOW_OR_S__,
3559       PSC_FLOW_OR_SEED
3560     };
3561     #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR,
3562   #else
3563     #define MEM_PSC_FLOW_BLOCK_OR
3564   #endif
3565
3566   MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
3567     MEM_PSC_FLOW_BLOCK_OR
3568     MEM_PSC_FLOW_BLOCK_END
3569   };
3570
3571   /*---------------------------------------------------------------------------------------------------
3572   *
3573   *  LRDIMM CONTROL
3574   *
3575   *---------------------------------------------------------------------------------------------------
3576   */
3577   #if (OPTION_LRDIMMS == TRUE)
3578     #if ((OPTION_MEMCTLR_OR == TRUE))
3579       #define MEM_TECH_FEATURE_LRDIMM_INIT  &MemTLrdimmConstructor3
3580     #else //#if ((OPTION_MEMCTLR_OR == FALSE))
3581       #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
3582     #endif
3583   #else //#if (OPTION_LRDIMMS == FALSE)
3584     #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
3585   #endif
3586   MEM_TECH_LRDIMM memLrdimmSupported = {
3587     MEM_TECH_LRDIMM_STRUCT_VERSION,
3588     MEM_TECH_FEATURE_LRDIMM_INIT
3589   };
3590 #else
3591   /*---------------------------------------------------------------------------------------------------
3592    * MAIN FLOW CONTROL
3593    *
3594    *
3595    *---------------------------------------------------------------------------------------------------
3596    */
3597   MEM_FLOW_CFG* memFlowControlInstalled[] = {
3598     NULL
3599   };
3600   /*---------------------------------------------------------------------------------------------------
3601    * NB TRAINING FLOW CONTROL
3602    *
3603    *
3604    *---------------------------------------------------------------------------------------------------
3605    */
3606   OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
3607     NULL
3608   };
3609   /*---------------------------------------------------------------------------------------------------
3610    * DEFAULT TECHNOLOGY BLOCK
3611    *
3612    *
3613    *---------------------------------------------------------------------------------------------------
3614    */
3615   MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
3616     NULL
3617   };
3618
3619   /*---------------------------------------------------------------------------------------------------
3620    * DEFAULT TECHNOLOGY MAP
3621    *
3622    *
3623    *---------------------------------------------------------------------------------------------------
3624    */
3625   UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
3626
3627   /*---------------------------------------------------------------------------------------------------
3628    * DEFAULT MAIN FEATURE BLOCK
3629    *---------------------------------------------------------------------------------------------------
3630    */
3631   MEM_FEAT_BLOCK_MAIN MemFeatMain = {
3632     NULL
3633   };
3634
3635   /*---------------------------------------------------------------------------------------------------
3636    * DEFAULT NORTHBRIDGE SUPPORT LIST
3637    *
3638    *
3639    *---------------------------------------------------------------------------------------------------
3640    */
3641   #if (OPTION_MEMCTLR_DR == TRUE)
3642     #undef MEM_NB_SUPPORT_DR
3643     #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
3644   #endif
3645   #if (OPTION_MEMCTLR_RB == TRUE)
3646     #undef MEM_NB_SUPPORT_RB
3647     #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
3648   #endif
3649   #if (OPTION_MEMCTLR_DA == TRUE)
3650     #undef MEM_NB_SUPPORT_DA
3651     #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
3652   #endif
3653   #if (OPTION_MEMCTLR_PH == TRUE)
3654     #undef MEM_NB_SUPPORT_PH
3655     #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
3656   #endif
3657   #if (OPTION_MEMCTLR_HY == TRUE)
3658     #undef MEM_NB_SUPPORT_HY
3659     #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
3660   #endif
3661   #if (OPTION_MEMCTLR_C32 == TRUE)
3662     #undef MEM_NB_SUPPORT_C32
3663     #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
3664   #endif
3665   #if (OPTION_MEMCTLR_OR == TRUE)
3666     #undef MEM_NB_SUPPORT_OR
3667     #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
3668   #endif
3669   /*---------------------------------------------------------------------------------------------------
3670    * DEFAULT Technology Training
3671    *
3672    *
3673    *---------------------------------------------------------------------------------------------------
3674    */
3675   #if OPTION_DDR2
3676     MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
3677       NULL
3678     };
3679     MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
3680       NULL
3681     };
3682   #endif
3683   #if OPTION_DDR3
3684     MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
3685       NULL
3686     };
3687     MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
3688       NULL
3689     };
3690   #endif
3691     /*---------------------------------------------------------------------------------------------------
3692      * DEFAULT Platform Specific list
3693      *
3694      *
3695      *---------------------------------------------------------------------------------------------------
3696      */
3697   #if (OPTION_MEMCTLR_DR == TRUE)
3698     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = {
3699       NULL
3700     };
3701   #endif
3702   #if (OPTION_MEMCTLR_RB == TRUE)
3703     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
3704       NULL
3705     };
3706   #endif
3707   #if (OPTION_MEMCTLR_DA == TRUE)
3708     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
3709       NULL
3710     };
3711   #endif
3712   #if (OPTION_MEMCTLR_Ni == TRUE)
3713     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
3714       NULL
3715     };
3716   #endif
3717   #if (OPTION_MEMCTLR_PH == TRUE)
3718     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
3719       NULL
3720     };
3721   #endif
3722   #if (OPTION_MEMCTLR_HY == TRUE)
3723     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
3724       NULL
3725     };
3726   #endif
3727   #if (OPTION_MEMCTLR_OR == TRUE)
3728     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = {
3729       NULL
3730     };
3731   #endif
3732   #if (OPTION_MEMCTLR_C32 == TRUE)
3733     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
3734       NULL
3735     };
3736   #endif
3737   /*----------------------------------------------------------------------
3738    * DEFAULT PSCFG DEFINITIONS
3739    *
3740    *----------------------------------------------------------------------
3741    */
3742   MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
3743     NULL
3744   };
3745
3746   /*----------------------------------------------------------------------
3747    * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
3748    *
3749    *----------------------------------------------------------------------
3750    */
3751   MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
3752     NULL
3753   };
3754
3755   MEM_TECH_LRDIMM memLrdimmSupported = {
3756     MEM_TECH_LRDIMM_STRUCT_VERSION,
3757     NULL
3758   };
3759 #endif
3760
3761 /*---------------------------------------------------------------------------------------------------
3762  * NORTHBRIDGE SUPPORT LIST
3763  *
3764  *
3765  *---------------------------------------------------------------------------------------------------
3766  */
3767 MEM_NB_SUPPORT memNBInstalled[] = {
3768   MEM_NB_SUPPORT_RB
3769   MEM_NB_SUPPORT_DA
3770   MEM_NB_SUPPORT_Ni
3771   MEM_NB_SUPPORT_PH
3772   MEM_NB_SUPPORT_HY
3773   MEM_NB_SUPPORT_OR
3774   MEM_NB_SUPPORT_C32
3775   MEM_NB_SUPPORT_END
3776 };
3777
3778 #endif  // _OPTION_MEMORY_INSTALL_H_