src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * Install of family 15h support
   6  *
   7  * This file generates the defaults tables for family 15h processors.
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      AGESA
  11  * @e sub-project:  Core
  12  * @e \$Revision: 60770 $   @e \$Date: 2011-10-21 15:51:10 -0600 (Fri, 21 Oct 2011) $
  13  */
  14 /*****************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *
  42  ***************************************************************************/
  43
  44 #ifndef _OPTION_FAMILY_15H_INSTALL_H_
  45 #define _OPTION_FAMILY_15H_INSTALL_H_
  46
  47 #include "OptionFamily15hEarlySample.h"
  48
  49 /*
  50  * Pull in family specific services based on entry point
  51  */
  52
  53 /*
  54  * Common Family 15h routines
  55  */
  56 extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
  57
  58 /*
  59  * Install family 15h model 0 support
  60  */
  61 #ifdef OPTION_FAMILY15H_OR
  62   #if OPTION_FAMILY15H_OR == TRUE
  63     extern F_CPU_GET_IDD_MAX F15OrGetProcIddMax;
  64     extern F_CPU_GET_NB_PSTATE_INFO F15OrGetNbPstateInfo;
  65     extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
  66     extern F_CPU_DISABLE_PSTATE F15DisablePstate;
  67     extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
  68     extern F_CPU_GET_TSC_RATE F15GetTscRate;
  69     extern F_CPU_GET_NB_FREQ F15OrGetCurrentNbFrequency;
  70     extern F_CPU_GET_MIN_MAX_NB_FREQ F15OrGetMinMaxNbFrequency;
  71     extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
  72     extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15OrGetNumberOfPhysicalCores;
  73     extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15OrGetApMailboxFromHardware;
  74     extern F_CPU_SET_AP_CORE_NUMBER F15OrSetApCoreNumber;
  75     extern F_CPU_GET_AP_CORE_NUMBER F15OrGetApCoreNumber;
  76     extern F_CPU_TRANSFER_AP_CORE_NUMBER F15OrTransferApCoreNumber;
  77     extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
  78     extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
  79     extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
  80     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
  81     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrSysPmTable;
  82     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
  83     extern F_CPU_SET_CFOH_REG SetF15OrCacheFlushOnHaltRegister;
  84     extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
  85     extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
  86     extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
  87     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
  88     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
  89     extern F_GET_EARLY_INIT_TABLE GetF15OrEarlyInitOnCoreTable;
  90     extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
  91     extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
  92     extern CONST REGISTER_TABLE ROMDATA F15OrAM3MsrWorkaroundTable;
  93     extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
  94     extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable;
  95     extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable;
  96     extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
  97     extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
  98     extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
  99     extern CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable;
 100     extern CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable;
 101     extern CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable;
 102     extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
 103
 104     #if OPTION_EARLY_SAMPLES == TRUE
 105       extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleWorkaroundsTable;
 106       extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrWorkaroundTable;
 107       extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrRegisterTable;
 108       extern CONST REGISTER_TABLE ROMDATA F15OrEarlySamplePciRegisterTable;
 109       extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleMsrRegisterTable;
 110     #endif
 111     /**
 112      * Core Pair and core pair primary determination table.
 113      *
 114      * The two fields from the core pair hardware register can be used to determine whether
 115      * even number cores are primary or all cores are primary.  It can be extended if it is
 116      * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
 117      * but they are currently not supported by the processor.
 118      */
 119     CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
 120     {
 121       {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
 122       {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
 123       {7, 7, EvenCoresMapping},                                     ///< 3 Compute Units all with 2 Cores
 124       {0xF, 0xF, EvenCoresMapping},                                 ///< 4 Compute Units all with 2 Cores
 125       {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
 126       {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
 127       {7, 0, AllCoresMapping},                                      ///< 3 Compute Units all with 1 Core
 128       {0xF, 0, AllCoresMapping},                                    ///< 4 Compute Units all with 1 Core
 129       {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
 130     };
 131
 132
 133     #if USES_REGISTER_TABLES == TRUE
 134       CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
 135       {
 136         #if BASE_FAMILY_PCI == TRUE
 137           &F15PciRegisterTable,
 138         #endif
 139         #if MODEL_SPECIFIC_PCI == TRUE
 140           &F15OrMultiLinkPciRegisterTable,
 141           &F15OrSingleLinkPciRegisterTable,
 142         #endif
 143         #if MODEL_SPECIFIC_PCI == TRUE
 144           &F15OrPciRegisterTable,
 145           #if OPTION_EARLY_SAMPLES == TRUE
 146             &F15OrEarlySamplePciRegisterTable,
 147           #endif
 148         #endif
 149         #if BASE_FAMILY_MSR == TRUE
 150           &F15MsrRegisterTable,
 151         #endif
 152         #if MODEL_SPECIFIC_MSR == TRUE
 153           &F15OrMsrRegisterTable,
 154           #if (OPTION_AM3_SOCKET_SUPPORT == TRUE) && (CFG_FORCE_MICROSERVER == FALSE)
 155             &F15OrAM3MsrWorkaroundTable,
 156           #endif
 157           #if OPTION_EARLY_SAMPLES == TRUE
 158             &F15OrEarlySampleMsrRegisterTable,
 159           #endif
 160         #endif
 161         #if MODEL_SPECIFIC_MSR == TRUE
 162           &F15OrSharedMsrRegisterTable,
 163           &F15OrSharedMsrCuRegisterTable,
 164           &F15OrSharedMsrWorkaroundTable,
 165           #if OPTION_EARLY_SAMPLES == TRUE
 166             &F15OrEarlySampleSharedMsrRegisterTable,
 167             &F15OrEarlySampleSharedMsrWorkaroundTable,
 168           #endif
 169         #endif
 170         #if MODEL_SPECIFIC_HT_PCI == TRUE
 171           &F15OrHtPhyRegisterTable,
 172         #endif
 173         #if BASE_FAMILY_WORKAROUNDS == TRUE
 174           &F15OrWorkaroundsTable,
 175           #if OPTION_EARLY_SAMPLES == TRUE
 176             &F15OrEarlySampleWorkaroundsTable,
 177           #endif
 178         #endif
 179         // the end.
 180         NULL
 181       };
 182     #endif
 183
 184     #if USES_REGISTER_TABLES == TRUE
 185       CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
 186       {
 187         {MsrRegister, SetRegisterForMsrEntry},
 188         {PciRegister, SetRegisterForPciEntry},
 189         {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
 190         {HtPhyRegister, SetRegisterForHtPhyEntry},
 191         {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
 192         {DeemphasisRegister, SetRegisterForDeemphasisEntry},
 193         {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
 194         {ProfileFixup, SetRegisterForPerformanceProfileEntry},
 195         {HtHostPciRegister, SetRegisterForHtHostEntry},
 196         {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
 197         {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
 198         {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
 199         {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
 200         {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
 201         {TokenPciRegister, SetRegisterForTokenPciEntry},
 202         {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
 203         {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
 204         {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
 205         // End
 206         {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
 207       };
 208     #endif
 209
 210     CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
 211     {
 212       0,
 213       #if DISABLE_PSTATE == TRUE
 214         F15DisablePstate,
 215       #else
 216         (PF_CPU_DISABLE_PSTATE) CommonAssert,
 217       #endif
 218       #if TRANSITION_PSTATE == TRUE
 219         F15TransitionPstate,
 220       #else
 221         (PF_CPU_TRANSITION_PSTATE) CommonAssert,
 222       #endif
 223       #if PROC_IDD_MAX == TRUE
 224         F15OrGetProcIddMax,
 225       #else
 226         (PF_CPU_GET_IDD_MAX) CommonAssert,
 227       #endif
 228       #if GET_TSC_RATE == TRUE
 229         F15GetTscRate,
 230       #else
 231         (PF_CPU_GET_TSC_RATE) CommonAssert,
 232       #endif
 233       #if GET_NB_FREQ == TRUE
 234         F15OrGetCurrentNbFrequency,
 235       #else
 236         (PF_CPU_GET_NB_FREQ) CommonAssert,
 237       #endif
 238       #if GET_NB_FREQ == TRUE
 239         F15OrGetMinMaxNbFrequency,
 240       #else
 241         (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
 242       #endif
 243       #if GET_NB_FREQ == TRUE
 244         F15OrGetNbPstateInfo,
 245       #else
 246         (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
 247       #endif
 248       #if IS_NBCOF_INIT_NEEDED == TRUE
 249         F15CommonGetNbCofVidUpdate,
 250       #else
 251         (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
 252       #endif
 253       #if GET_NB_IDD_MAX == TRUE
 254         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
 255       #else
 256         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
 257       #endif
 258       #if AP_INITIAL_LAUNCH == TRUE
 259         F15LaunchApCore,
 260       #else
 261         (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
 262       #endif
 263       #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
 264         F15OrGetNumberOfPhysicalCores,
 265       #else
 266         (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
 267       #endif
 268       #if GET_AP_MAILBOX_FROM_HW == TRUE
 269         F15OrGetApMailboxFromHardware,
 270       #else
 271         (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
 272       #endif
 273       #if SET_AP_CORE_NUMBER == TRUE
 274         F15OrSetApCoreNumber,
 275       #else
 276         (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
 277       #endif
 278       #if GET_AP_CORE_NUMBER == TRUE
 279         F15OrGetApCoreNumber,
 280       #else
 281         (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
 282       #endif
 283       #if TRANSFER_AP_CORE_NUMBER == TRUE
 284         F15OrTransferApCoreNumber,
 285       #else
 286         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
 287       #endif
 288       #if ID_POSITION_INITIAL_APICID == TRUE
 289         F15CpuAmdCoreIdPositionInInitialApicId,
 290       #else
 291         (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
 292       #endif
 293       #if SAVE_FEATURES == TRUE
 294         // F15OrSaveFeatures,
 295         (PF_CPU_SAVE_FEATURES) CommonVoid,
 296       #else
 297         (PF_CPU_SAVE_FEATURES) CommonAssert,
 298       #endif
 299       #if WRITE_FEATURES == TRUE
 300         // F15OrWriteFeatures,
 301         (PF_CPU_WRITE_FEATURES) CommonVoid,
 302       #else
 303         (PF_CPU_WRITE_FEATURES) CommonAssert,
 304       #endif
 305       #if SET_WARM_RESET_FLAG == TRUE
 306         F15SetAgesaWarmResetFlag,
 307       #else
 308         (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
 309       #endif
 310       #if GET_WARM_RESET_FLAG == TRUE
 311         F15GetAgesaWarmResetFlag,
 312       #else
 313         (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
 314       #endif
 315       #if BRAND_STRING1 == TRUE
 316         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
 317       #else
 318         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 319       #endif
 320       #if BRAND_STRING2 == TRUE
 321         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
 322       #else
 323         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 324       #endif
 325       #if GET_PATCHES == TRUE
 326         GetF15OrMicroCodePatchesStruct,
 327       #else
 328         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 329       #endif
 330       #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
 331         GetF15OrMicrocodeEquivalenceTable,
 332       #else
 333         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 334       #endif
 335       #if GET_CACHE_INFO == TRUE
 336         GetF15CacheInfo,
 337       #else
 338         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 339       #endif
 340       #if GET_SYSTEM_PM_TABLE == TRUE
 341         GetF15OrSysPmTable,
 342       #else
 343         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 344       #endif
 345       #if GET_WHEA_INIT == TRUE
 346         GetF15WheaInitData,
 347       #else
 348         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 349       #endif
 350       #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
 351         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
 352       #else
 353         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
 354       #endif
 355       #if IS_NB_PSTATE_ENABLED == TRUE
 356         F15IsNbPstateEnabled,
 357       #else
 358         (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
 359       #endif
 360       #if (BASE_FAMILY_HT_PCI == TRUE)
 361         F15NextLinkHasHtPhyFeats,
 362       #else
 363         (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
 364       #endif
 365       #if (BASE_FAMILY_HT_PCI == TRUE)
 366         F15SetHtPhyRegister,
 367       #else
 368         (PF_SET_HT_PHY_REGISTER) CommonAssert,
 369       #endif
 370       #if BASE_FAMILY_PCI == TRUE
 371         F15GetNextHtLinkFeatures,
 372       #else
 373         (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
 374       #endif
 375       #if USES_REGISTER_TABLES == TRUE
 376         (REGISTER_TABLE **) F15OrRegisterTables,
 377       #else
 378         NULL,
 379       #endif
 380       #if USES_REGISTER_TABLES == TRUE
 381         (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
 382       #else
 383         NULL,
 384       #endif
 385       #if MODEL_SPECIFIC_HT_PCI == TRUE
 386         (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
 387       #else
 388         NULL,
 389       #endif
 390       (CORE_PAIR_MAP *) &HtFam15CorePairMapping,
 391       InitCacheEnabled,
 392       #if AGESA_ENTRY_INIT_EARLY == TRUE
 393         GetF15OrEarlyInitOnCoreTable
 394       #else
 395         (PF_GET_EARLY_INIT_TABLE) CommonVoid
 396       #endif
 397     };
 398
 399     #define OR_SOCKETS 8
 400     #define OR_MODULES 2
 401     #define OR_RECOVERY_SOCKETS 1
 402     #define OR_RECOVERY_MODULES 1
 403     extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
 404     #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
 405     #ifndef ADVCFG_PLATFORM_SOCKETS
 406       #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
 407     #else
 408       #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
 409         #undef ADVCFG_PLATFORM_SOCKETS
 410         #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
 411       #endif
 412     #endif
 413     #ifndef ADVCFG_PLATFORM_MODULES
 414       #define ADVCFG_PLATFORM_MODULES OR_MODULES
 415     #else
 416       #if ADVCFG_PLATFORM_MODULES < OR_MODULES
 417         #undef ADVCFG_PLATFORM_MODULES
 418         #define ADVCFG_PLATFORM_MODULES OR_MODULES
 419       #endif
 420     #endif
 421
 422     #if GET_PATCHES == TRUE
 423       #define F15_OR_UCODE_17_UNENC
 424       #define F15_OR_UCODE_11F_UNENC
 425       #define F15_OR_UCODE_425
 426       #define F15_OR_UCODE_50D
 427       #define F15_OR_UCODE_624
 428
 429       #if AGESA_ENTRY_INIT_EARLY == TRUE
 430         #if OPTION_EARLY_SAMPLES == TRUE
 431           extern  CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000425 [];
 432           #undef F15_OR_UCODE_425
 433           #define F15_OR_UCODE_425 CpuF15OrMicrocodePatch06000425,
 434
 435           extern  CONST UINT8 ROMDATA CpuF15OrMicrocodePatch0600050D_Enc [];
 436           #undef F15_OR_UCODE_50D
 437           #define F15_OR_UCODE_50D CpuF15OrMicrocodePatch0600050D_Enc,
 438         #endif
 439         extern  CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000624_Enc [];
 440         #undef F15_OR_UCODE_624
 441         #define F15_OR_UCODE_624 CpuF15OrMicrocodePatch06000624_Enc,
 442       #endif
 443
 444       CONST UINT8 ROMDATA *CpuF15OrMicroCodePatchArray[] =
 445       {
 446         F15_OR_UCODE_624
 447         F15_OR_UCODE_50D
 448         F15_OR_UCODE_425
 449         NULL
 450       };
 451
 452       CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
 453     #endif
 454
 455     #if OPTION_EARLY_SAMPLES == TRUE
 456       extern F_F15_OR_ES_AVOID_NB_CYCLES_START F15OrEarlySamplesAvoidNbCyclesStart;
 457       extern F_F15_OR_ES_AVOID_NB_CYCLES_END F15OrEarlySamplesAvoidNbCyclesEnd;
 458       extern F_F15_OR_ES_LOAD_MCU_PATCH F15OrEarlySamplesLoadMicrocodePatch;
 459       extern F_F15_OR_ES_AFTER_PATCH_LOADED F15OrEarlySamplesAfterPatchLoaded;
 460
 461       CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
 462       {
 463         F15OrEarlySamplesAvoidNbCyclesStart,
 464         F15OrEarlySamplesAvoidNbCyclesEnd,
 465         F15OrEarlySamplesLoadMicrocodePatch,
 466         F15OrEarlySamplesAfterPatchLoaded
 467       };
 468     #else
 469       CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
 470       {
 471         (PF_F15_OR_ES_AVOID_NB_CYCLES_START)  CommonVoid,
 472         (PF_F15_OR_ES_AVOID_NB_CYCLES_END)    CommonVoid,
 473         (PF_F15_OR_ES_LOAD_MCU_PATCH)         LoadMicrocodePatch,
 474         (PF_F15_OR_ES_AFTER_PATCH_LOADED)     CommonVoid
 475       };
 476     #endif
 477
 478     #if OPTION_EARLY_SAMPLES == TRUE
 479       extern F_F15_OR_ES_HTC_INIT_HOOK F15OrHtcInitEarlySampleHook;
 480
 481       CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
 482       {
 483         #if AGESA_ENTRY_INIT_EARLY == TRUE
 484           F15OrHtcInitEarlySampleHook,
 485         #else
 486           (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
 487         #endif
 488       };
 489     #else
 490       CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
 491       {
 492         #if AGESA_ENTRY_INIT_EARLY == TRUE
 493           (PF_F15_OR_ES_HTC_INIT_HOOK) CommonVoid,
 494         #else
 495           (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
 496         #endif
 497       };
 498     #endif
 499
 500     #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
 501
 502   #else  //  OPTION_FAMILY15H_OR == TRUE
 503     #define OPT_F15_OR_CPU
 504     #define OPT_F15_OR_ID
 505   #endif  //  OPTION_FAMILY15H_OR == TRUE
 506 #else  //  defined (OPTION_FAMILY15H_OR)
 507   #define OPT_F15_OR_CPU
 508   #define OPT_F15_OR_ID
 509 #endif  //  defined (OPTION_FAMILY15H_OR)
 510
 511
 512 /*
 513  * Install family 15h model 10h - 1Fh support
 514  */
 515 #ifdef OPTION_FAMILY15H_TN
 516   #if OPTION_FAMILY15H_TN == TRUE
 517     extern F_CPU_GET_IDD_MAX F15TnGetProcIddMax;
 518     extern F_CPU_GET_NB_PSTATE_INFO F15TnGetNbPstateInfo;
 519     extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
 520     extern F_CPU_GET_NB_IDD_MAX F15TnGetNbIddMax;
 521     extern F_CPU_DISABLE_PSTATE F15DisablePstate;
 522     extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
 523     extern F_CPU_GET_TSC_RATE F15GetTscRate;
 524     extern F_CPU_GET_NB_FREQ F15TnGetCurrentNbFrequency;
 525     extern F_CPU_GET_MIN_MAX_NB_FREQ F15TnGetMinMaxNbFrequency;
 526     extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
 527     extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15TnGetNumberOfPhysicalCores;
 528     extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15TnGetApMailboxFromHardware;
 529     extern F_CPU_GET_AP_CORE_NUMBER F15TnGetApCoreNumber;
 530     extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
 531     extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
 532     extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
 533     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
 534     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnSysPmTable;
 535     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
 536     extern F_CPU_SET_CFOH_REG SetF15TnCacheFlushOnHaltRegister;
 537     extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
 538     extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
 539     extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
 540     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicroCodePatchesStruct;
 541     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicrocodeEquivalenceTable;
 542     extern F_GET_EARLY_INIT_TABLE GetF15TnEarlyInitOnCoreTable;
 543     extern CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable;
 544     extern CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable;
 545     extern CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable;
 546     extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable;
 547     extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable;
 548     extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable;
 549     extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
 550     extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
 551
 552     /**
 553      * Core Pair and core pair primary determination table.
 554      *
 555      * The two fields from the core pair hardware register can be used to determine whether
 556      * even number cores are primary or all cores are primary.  It can be extended if it is
 557      * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
 558      * but they are currently not supported by the processor.
 559      */
 560     CONST CORE_PAIR_MAP ROMDATA HtFam15TnCorePairMapping[] =
 561     {
 562       {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
 563       {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
 564       {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
 565       {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
 566       {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
 567     };
 568
 569
 570     #if USES_REGISTER_TABLES == TRUE
 571       CONST REGISTER_TABLE ROMDATA *F15TnRegisterTables[] =
 572       {
 573         #if BASE_FAMILY_PCI == TRUE
 574           &F15PciRegisterTable,
 575         #endif
 576         #if MODEL_SPECIFIC_PCI == TRUE
 577           &F15TnPciRegisterTable,
 578           &F15TnPciWorkaroundTable,
 579         #endif
 580         #if BASE_FAMILY_MSR == TRUE
 581           &F15MsrRegisterTable,
 582         #endif
 583         #if MODEL_SPECIFIC_MSR == TRUE
 584           &F15TnMsrRegisterTable,
 585           &F15TnSharedMsrRegisterTable,
 586           &F15TnSharedMsrCuRegisterTable,
 587           &F15TnSharedMsrWorkaroundTable,
 588         #endif
 589         // the end.
 590         NULL
 591       };
 592     #endif
 593
 594     #if USES_REGISTER_TABLES == TRUE
 595       CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15TnTableEntryTypeDescriptors[] =
 596       {
 597         {MsrRegister, SetRegisterForMsrEntry},
 598         {PciRegister, SetRegisterForPciEntry},
 599         {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
 600         {ProfileFixup, SetRegisterForPerformanceProfileEntry},
 601         {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
 602         {HtPhyRegister, SetRegisterForHtPhyEntry},
 603         {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
 604         {DeemphasisRegister, SetRegisterForDeemphasisEntry},
 605         {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
 606         {HtHostPciRegister, SetRegisterForHtHostEntry},
 607         {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
 608         {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
 609         {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
 610         {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
 611         {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
 612         {TokenPciRegister, SetRegisterForTokenPciEntry},
 613         {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
 614         {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
 615         // End
 616         {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
 617       };
 618     #endif
 619
 620     CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15TnServices =
 621     {
 622       0,
 623       #if DISABLE_PSTATE == TRUE
 624         F15DisablePstate,
 625       #else
 626         (PF_CPU_DISABLE_PSTATE) CommonAssert,
 627       #endif
 628       #if TRANSITION_PSTATE == TRUE
 629         F15TransitionPstate,
 630       #else
 631         (PF_CPU_TRANSITION_PSTATE) CommonAssert,
 632       #endif
 633       #if PROC_IDD_MAX == TRUE
 634         F15TnGetProcIddMax,
 635       #else
 636         (PF_CPU_GET_IDD_MAX) CommonAssert,
 637       #endif
 638       #if GET_TSC_RATE == TRUE
 639         F15GetTscRate,
 640       #else
 641         (PF_CPU_GET_TSC_RATE) CommonAssert,
 642       #endif
 643       #if GET_NB_FREQ == TRUE
 644         F15TnGetCurrentNbFrequency,
 645       #else
 646         (PF_CPU_GET_NB_FREQ) CommonAssert,
 647       #endif
 648       #if GET_NB_FREQ == TRUE
 649         F15TnGetMinMaxNbFrequency,
 650       #else
 651         (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
 652       #endif
 653       #if GET_NB_FREQ == TRUE
 654         F15TnGetNbPstateInfo,
 655       #else
 656         (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
 657       #endif
 658       #if IS_NBCOF_INIT_NEEDED == TRUE
 659         F15CommonGetNbCofVidUpdate,
 660       #else
 661         (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
 662       #endif
 663       #if GET_NB_IDD_MAX == TRUE
 664         (PF_CPU_GET_NB_IDD_MAX) F15TnGetNbIddMax,
 665       #else
 666         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
 667       #endif
 668       #if AP_INITIAL_LAUNCH == TRUE
 669         F15LaunchApCore,
 670       #else
 671         (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
 672       #endif
 673       #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
 674         F15TnGetNumberOfPhysicalCores,
 675       #else
 676         (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
 677       #endif
 678       #if GET_AP_MAILBOX_FROM_HW == TRUE
 679         F15TnGetApMailboxFromHardware,
 680       #else
 681         (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
 682       #endif
 683       #if SET_AP_CORE_NUMBER == TRUE
 684         (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
 685       #else
 686         (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
 687       #endif
 688       #if GET_AP_CORE_NUMBER == TRUE
 689         F15TnGetApCoreNumber,
 690       #else
 691         (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
 692       #endif
 693       #if TRANSFER_AP_CORE_NUMBER == TRUE
 694         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
 695       #else
 696         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
 697       #endif
 698       #if ID_POSITION_INITIAL_APICID == TRUE
 699         F15CpuAmdCoreIdPositionInInitialApicId,
 700       #else
 701         (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
 702       #endif
 703       #if SAVE_FEATURES == TRUE
 704         (PF_CPU_SAVE_FEATURES) CommonVoid,
 705       #else
 706         (PF_CPU_SAVE_FEATURES) CommonAssert,
 707       #endif
 708       #if WRITE_FEATURES == TRUE
 709         (PF_CPU_WRITE_FEATURES) CommonVoid,
 710       #else
 711         (PF_CPU_WRITE_FEATURES) CommonAssert,
 712       #endif
 713       #if SET_WARM_RESET_FLAG == TRUE
 714         F15SetAgesaWarmResetFlag,
 715       #else
 716         (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
 717       #endif
 718       #if GET_WARM_RESET_FLAG == TRUE
 719         F15GetAgesaWarmResetFlag,
 720       #else
 721         (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
 722       #endif
 723       #if BRAND_STRING1 == TRUE
 724         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
 725       #else
 726         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 727       #endif
 728       #if BRAND_STRING2 == TRUE
 729         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
 730       #else
 731         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 732       #endif
 733       #if GET_PATCHES == TRUE
 734         GetF15TnMicroCodePatchesStruct,
 735       #else
 736         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 737       #endif
 738       #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
 739         GetF15TnMicrocodeEquivalenceTable,
 740       #else
 741         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 742       #endif
 743       #if GET_CACHE_INFO == TRUE
 744         GetF15CacheInfo,
 745       #else
 746         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 747       #endif
 748       #if GET_SYSTEM_PM_TABLE == TRUE
 749         GetF15TnSysPmTable,
 750       #else
 751         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 752       #endif
 753       #if GET_WHEA_INIT == TRUE
 754         GetF15WheaInitData,
 755       #else
 756         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 757       #endif
 758       #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
 759         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
 760       #else
 761         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
 762       #endif
 763       #if IS_NB_PSTATE_ENABLED == TRUE
 764         F15IsNbPstateEnabled,
 765       #else
 766         (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
 767       #endif
 768       #if (BASE_FAMILY_HT_PCI == TRUE)
 769         F15NextLinkHasHtPhyFeats,
 770       #else
 771         (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
 772       #endif
 773       #if (BASE_FAMILY_HT_PCI == TRUE)
 774         F15SetHtPhyRegister,
 775       #else
 776         (PF_SET_HT_PHY_REGISTER) CommonAssert,
 777       #endif
 778       #if BASE_FAMILY_PCI == TRUE
 779         F15GetNextHtLinkFeatures,
 780       #else
 781         (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
 782       #endif
 783       #if USES_REGISTER_TABLES == TRUE
 784         (REGISTER_TABLE **) F15TnRegisterTables,
 785       #else
 786         NULL,
 787       #endif
 788       #if USES_REGISTER_TABLES == TRUE
 789         (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15TnTableEntryTypeDescriptors,
 790       #else
 791         NULL,
 792       #endif
 793       #if MODEL_SPECIFIC_HT_PCI == TRUE
 794         NULL,
 795       #else
 796         NULL,
 797       #endif
 798       (CORE_PAIR_MAP *) &HtFam15TnCorePairMapping,
 799       InitCacheEnabled,
 800       #if AGESA_ENTRY_INIT_EARLY == TRUE
 801         GetF15TnEarlyInitOnCoreTable
 802       #else
 803         (PF_GET_EARLY_INIT_TABLE) CommonVoid
 804       #endif
 805     };
 806
 807     #define TN_SOCKETS 1
 808     #define TN_MODULES 1
 809     #define TN_RECOVERY_SOCKETS 1
 810     #define TN_RECOVERY_MODULES 1
 811     extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15TnLogicalIdAndRev;
 812     #define OPT_F15_TN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15TnLogicalIdAndRev,
 813     #ifndef ADVCFG_PLATFORM_SOCKETS
 814       #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
 815     #else
 816       #if ADVCFG_PLATFORM_SOCKETS < TN_SOCKETS
 817         #undef ADVCFG_PLATFORM_SOCKETS
 818         #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
 819       #endif
 820     #endif
 821     #ifndef ADVCFG_PLATFORM_MODULES
 822       #define ADVCFG_PLATFORM_MODULES TN_MODULES
 823     #else
 824       #if ADVCFG_PLATFORM_MODULES < TN_MODULES
 825         #undef ADVCFG_PLATFORM_MODULES
 826         #define ADVCFG_PLATFORM_MODULES TN_MODULES
 827       #endif
 828     #endif
 829
 830     #if GET_PATCHES == TRUE
 831       #define F15_TN_UCODE_04
 832       #define F15_TN_UCODE_04_UNENC
 833
 834       #if AGESA_ENTRY_INIT_EARLY == TRUE
 835         #if OPTION_EARLY_SAMPLES == TRUE
 836           extern  CONST UINT8 ROMDATA CpuF15TnMicrocodePatch06001004_Unenc [];
 837           #undef F15_TN_UCODE_04_UNENC
 838           #define F15_TN_UCODE_04_UNENC CpuF15TnMicrocodePatch06001004_Unenc,
 839
 840           extern  CONST UINT8 ROMDATA CpuF15TnMicrocodePatch06001004 [];
 841           #undef F15_TN_UCODE_04
 842           #define F15_TN_UCODE_04 CpuF15TnMicrocodePatch06001004,
 843         #endif
 844       #endif
 845
 846       CONST UINT8 ROMDATA *CpuF15TnMicroCodePatchArray[] =
 847       {
 848         F15_TN_UCODE_04
 849         F15_TN_UCODE_04_UNENC
 850         NULL
 851       };
 852
 853       CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15TnMicroCodePatchArray) / sizeof (CpuF15TnMicroCodePatchArray[0])) - 1);
 854     #endif
 855
 856     #if OPTION_EARLY_SAMPLES == TRUE
 857       extern F_F15_TN_ES_LOAD_MCU_PATCH F15TnEarlySamplesLoadMicrocodePatch;
 858
 859       CONST F15_TN_ES_MCU_PATCH ROMDATA F15TnEarlySampleLoadMcuPatch =
 860       {
 861         F15TnEarlySamplesLoadMicrocodePatch
 862       };
 863     #else
 864       CONST F15_TN_ES_MCU_PATCH ROMDATA F15TnEarlySampleLoadMcuPatch =
 865       {
 866         (PF_F15_TN_ES_LOAD_MCU_PATCH) LoadMicrocodePatch
 867       };
 868     #endif
 869
 870     #define OPT_F15_TN_CPU {AMD_FAMILY_15_TN, &cpuF15TnServices},
 871
 872   #else  //  OPTION_FAMILY15H_TN == TRUE
 873     #define OPT_F15_TN_CPU
 874     #define OPT_F15_TN_ID
 875   #endif  //  OPTION_FAMILY15H_TN == TRUE
 876 #else  //  defined (OPTION_FAMILY15H_TN)
 877   #define OPT_F15_TN_CPU
 878   #define OPT_F15_TN_ID
 879 #endif  //  defined (OPTION_FAMILY15H_TN)
 880
 881 /*
 882  * Install family 15h model 20h - 2Fh support
 883  */
 884 #ifdef OPTION_FAMILY15H_KM
 885   #if OPTION_FAMILY15H_KM == TRUE
 886     extern F_CPU_GET_IDD_MAX F15KmGetProcIddMax;
 887     extern F_CPU_GET_NB_PSTATE_INFO F15KmGetNbPstateInfo;
 888     extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
 889     extern F_CPU_DISABLE_PSTATE F15DisablePstate;
 890     extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
 891     extern F_CPU_GET_TSC_RATE F15GetTscRate;
 892     extern F_CPU_GET_NB_FREQ F15KmGetCurrentNbFrequency;
 893     extern F_CPU_GET_MIN_MAX_NB_FREQ F15KmGetMinMaxNbFrequency;
 894     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
 895     extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
 896     extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15KmGetNumberOfPhysicalCores;
 897     extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15KmGetApMailboxFromHardware;
 898     extern F_CPU_SET_AP_CORE_NUMBER F15KmSetApCoreNumber;
 899     extern F_CPU_GET_AP_CORE_NUMBER F15KmGetApCoreNumber;
 900     extern F_CPU_TRANSFER_AP_CORE_NUMBER F15KmTransferApCoreNumber;
 901     extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
 902     extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
 903     extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
 904     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmSysPmTable;
 905     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
 906     extern F_CPU_SET_CFOH_REG SetF15KmCacheFlushOnHaltRegister;
 907     extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
 908     extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
 909     extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
 910     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmMicroCodePatchesStruct;
 911     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmMicrocodeEquivalenceTable;
 912     extern F_GET_EARLY_INIT_TABLE GetF15KmEarlyInitOnCoreTable;
 913     extern CONST REGISTER_TABLE ROMDATA F15KmPciRegisterTable;
 914     extern CONST REGISTER_TABLE ROMDATA F15KmMsrRegisterTable;
 915     extern CONST REGISTER_TABLE ROMDATA F15KmSharedMsrRegisterTable;
 916     extern CONST REGISTER_TABLE ROMDATA F15KmSharedMsrCuRegisterTable;
 917     extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
 918     extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
 919     extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15Mod2xPackageLinkMap[];
 920     /**
 921      * Core Pair and core pair primary determination table.
 922      *
 923      * The two fields from the core pair hardware register can be used to determine whether
 924      * even number cores are primary or all cores are primary.  It can be extended if it is
 925      * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
 926      * but they are currently not supported by the processor.
 927      */
 928     CONST CORE_PAIR_MAP ROMDATA HtFam15KmCorePairMapping[] =
 929     {
 930       {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
 931       {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
 932       {7, 7, EvenCoresMapping},                                     ///< 3 Compute Units all with 2 Cores
 933       {0xF, 0xF, EvenCoresMapping},                                 ///< 4 Compute Units all with 2 Cores
 934       {0x1F, 0x1F, EvenCoresMapping},                               ///< 5 Compute Units all with 2 Cores
 935       {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
 936       {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
 937       {7, 0, AllCoresMapping},                                      ///< 3 Compute Units all with 1 Core
 938       {0xF, 0, AllCoresMapping},                                    ///< 4 Compute Units all with 1 Core
 939       {0x1F, 0, AllCoresMapping},                                   ///< 5 Compute Units all with 1 Core
 940       {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
 941     };
 942
 943
 944     #if USES_REGISTER_TABLES == TRUE
 945       CONST REGISTER_TABLE ROMDATA *F15KmRegisterTables[] =
 946       {
 947         #if BASE_FAMILY_PCI == TRUE
 948           &F15PciRegisterTable,
 949         #endif
 950         #if MODEL_SPECIFIC_PCI == TRUE
 951           &F15KmPciRegisterTable,
 952         #endif
 953         #if BASE_FAMILY_MSR == TRUE
 954           &F15MsrRegisterTable,
 955         #endif
 956         #if MODEL_SPECIFIC_MSR == TRUE
 957           &F15KmMsrRegisterTable,
 958         #endif
 959         #if MODEL_SPECIFIC_MSR == TRUE
 960           &F15KmSharedMsrRegisterTable,
 961           &F15KmSharedMsrCuRegisterTable,
 962         #endif
 963         // the end.
 964         NULL
 965       };
 966     #endif
 967
 968     #if USES_REGISTER_TABLES == TRUE
 969       CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15KmTableEntryTypeDescriptors[] =
 970       {
 971         {MsrRegister, SetRegisterForMsrEntry},
 972         {PciRegister, SetRegisterForPciEntry},
 973         {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
 974         {HtPhyRegister, SetRegisterForHtPhyEntry},
 975         {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
 976         {DeemphasisRegister, SetRegisterForDeemphasisEntry},
 977         {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
 978         {ProfileFixup, SetRegisterForPerformanceProfileEntry},
 979         {HtHostPciRegister, SetRegisterForHtHostEntry},
 980         {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
 981         {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
 982         {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
 983         {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
 984         {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
 985         {TokenPciRegister, SetRegisterForTokenPciEntry},
 986         {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
 987         {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
 988         {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
 989         // End
 990         {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
 991       };
 992     #endif
 993
 994     CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15KmServices =
 995     {
 996       0,
 997       #if DISABLE_PSTATE == TRUE
 998         F15DisablePstate,
 999       #else
1000         (PF_CPU_DISABLE_PSTATE) CommonAssert,
1001       #endif
1002       #if TRANSITION_PSTATE == TRUE
1003         F15TransitionPstate,
1004       #else
1005         (PF_CPU_TRANSITION_PSTATE) CommonAssert,
1006       #endif
1007       #if PROC_IDD_MAX == TRUE
1008         F15KmGetProcIddMax,
1009       #else
1010         (PF_CPU_GET_IDD_MAX) CommonAssert,
1011       #endif
1012       #if GET_TSC_RATE == TRUE
1013         F15GetTscRate,
1014       #else
1015         (PF_CPU_GET_TSC_RATE) CommonAssert,
1016       #endif
1017       #if GET_NB_FREQ == TRUE
1018         F15KmGetCurrentNbFrequency,
1019       #else
1020         (PF_CPU_GET_NB_FREQ) CommonAssert,
1021       #endif
1022       #if GET_NB_FREQ == TRUE
1023         F15KmGetMinMaxNbFrequency,
1024       #else
1025         (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
1026       #endif
1027       #if GET_NB_FREQ == TRUE
1028         F15KmGetNbPstateInfo,
1029       #else
1030         (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
1031       #endif
1032       #if IS_NBCOF_INIT_NEEDED == TRUE
1033         F15CommonGetNbCofVidUpdate,
1034       #else
1035         (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
1036       #endif
1037       #if GET_NB_IDD_MAX == TRUE
1038         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1039       #else
1040         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1041       #endif
1042       #if AP_INITIAL_LAUNCH == TRUE
1043         F15LaunchApCore,
1044       #else
1045         (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
1046       #endif
1047       #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
1048         F15KmGetNumberOfPhysicalCores,
1049       #else
1050         (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
1051       #endif
1052       #if GET_AP_MAILBOX_FROM_HW == TRUE
1053         F15KmGetApMailboxFromHardware,
1054       #else
1055         (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
1056       #endif
1057       #if SET_AP_CORE_NUMBER == TRUE
1058         F15KmSetApCoreNumber,
1059       #else
1060         (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
1061       #endif
1062       #if GET_AP_CORE_NUMBER == TRUE
1063         F15KmGetApCoreNumber,
1064       #else
1065         (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
1066       #endif
1067       #if TRANSFER_AP_CORE_NUMBER == TRUE
1068         F15KmTransferApCoreNumber,
1069       #else
1070         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
1071       #endif
1072       #if ID_POSITION_INITIAL_APICID == TRUE
1073         F15CpuAmdCoreIdPositionInInitialApicId,
1074       #else
1075         (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
1076       #endif
1077       #if SAVE_FEATURES == TRUE
1078         (PF_CPU_SAVE_FEATURES) CommonVoid,
1079       #else
1080         (PF_CPU_SAVE_FEATURES) CommonAssert,
1081       #endif
1082       #if WRITE_FEATURES == TRUE
1083         (PF_CPU_WRITE_FEATURES) CommonVoid,
1084       #else
1085         (PF_CPU_WRITE_FEATURES) CommonAssert,
1086       #endif
1087       #if SET_WARM_RESET_FLAG == TRUE
1088         F15SetAgesaWarmResetFlag,
1089       #else
1090         (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
1091       #endif
1092       #if GET_WARM_RESET_FLAG == TRUE
1093         F15GetAgesaWarmResetFlag,
1094       #else
1095         (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
1096       #endif
1097       #if BRAND_STRING1 == TRUE
1098         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
1099       #else
1100         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1101       #endif
1102       #if BRAND_STRING2 == TRUE
1103         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
1104       #else
1105         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1106       #endif
1107       #if GET_PATCHES == TRUE
1108         GetF15KmMicroCodePatchesStruct,
1109       #else
1110         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1111       #endif
1112       #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
1113         GetF15KmMicrocodeEquivalenceTable,
1114       #else
1115         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1116       #endif
1117       #if GET_CACHE_INFO == TRUE
1118         GetF15CacheInfo,
1119       #else
1120         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1121       #endif
1122       #if GET_SYSTEM_PM_TABLE == TRUE
1123         GetF15KmSysPmTable,
1124       #else
1125         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1126       #endif
1127       #if GET_WHEA_INIT == TRUE
1128         GetF15WheaInitData,
1129       #else
1130         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1131       #endif
1132       #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
1133         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
1134       #else
1135         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
1136       #endif
1137       #if IS_NB_PSTATE_ENABLED == TRUE
1138         F15IsNbPstateEnabled,
1139       #else
1140         (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
1141       #endif
1142       #if (BASE_FAMILY_HT_PCI == TRUE)
1143         F15NextLinkHasHtPhyFeats,
1144       #else
1145         (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
1146       #endif
1147       #if (BASE_FAMILY_HT_PCI == TRUE)
1148         F15SetHtPhyRegister,
1149       #else
1150         (PF_SET_HT_PHY_REGISTER) CommonAssert,
1151       #endif
1152       #if BASE_FAMILY_PCI == TRUE
1153         F15GetNextHtLinkFeatures,
1154       #else
1155         (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
1156       #endif
1157       #if USES_REGISTER_TABLES == TRUE
1158         (REGISTER_TABLE **) F15KmRegisterTables,
1159       #else
1160         NULL,
1161       #endif
1162       #if USES_REGISTER_TABLES == TRUE
1163         (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15KmTableEntryTypeDescriptors,
1164       #else
1165         NULL,
1166       #endif
1167       #if MODEL_SPECIFIC_HT_PCI == TRUE
1168         (PACKAGE_HTLINK_MAP) &HtFam15Mod2xPackageLinkMap,
1169       #else
1170         NULL,
1171       #endif
1172       (CORE_PAIR_MAP *) &HtFam15KmCorePairMapping,
1173       InitCacheEnabled,
1174       #if AGESA_ENTRY_INIT_EARLY == TRUE
1175         GetF15KmEarlyInitOnCoreTable
1176       #else
1177         (PF_GET_EARLY_INIT_TABLE) CommonVoid
1178       #endif
1179     };
1180
1181     #define KM_SOCKETS 8
1182     #define KM_MODULES 2
1183     #define KM_RECOVERY_SOCKETS 1
1184     #define KM_RECOVERY_MODULES 1
1185     extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15KmLogicalIdAndRev;
1186     #define OPT_F15_KM_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15KmLogicalIdAndRev,
1187     #ifndef ADVCFG_PLATFORM_SOCKETS
1188       #define ADVCFG_PLATFORM_SOCKETS KM_SOCKETS
1189     #else
1190       #if ADVCFG_PLATFORM_SOCKETS < KM_SOCKETS
1191         #undef ADVCFG_PLATFORM_SOCKETS
1192         #define ADVCFG_PLATFORM_SOCKETS KM_SOCKETS
1193       #endif
1194     #endif
1195     #ifndef ADVCFG_PLATFORM_MODULES
1196       #define ADVCFG_PLATFORM_MODULES KM_MODULES
1197     #else
1198       #if ADVCFG_PLATFORM_MODULES < KM_MODULES
1199         #undef ADVCFG_PLATFORM_MODULES
1200         #define ADVCFG_PLATFORM_MODULES KM_MODULES
1201       #endif
1202     #endif
1203
1204     #if GET_PATCHES == TRUE
1205
1206       #if AGESA_ENTRY_INIT_EARLY == TRUE
1207         #if OPTION_EARLY_SAMPLES == TRUE
1208         #endif
1209       #endif
1210
1211       CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15KmMicroCodePatchArray[] =
1212       {
1213         NULL
1214       };
1215
1216       CONST UINT8 ROMDATA CpuF15KmNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15KmMicroCodePatchArray) / sizeof (CpuF15KmMicroCodePatchArray[0])) - 1);
1217     #endif
1218
1219     #define OPT_F15_KM_CPU {AMD_FAMILY_15_KM, &cpuF15KmServices},
1220
1221   #else  //  OPTION_FAMILY15H_KM == TRUE
1222     #define OPT_F15_KM_CPU
1223     #define OPT_F15_KM_ID
1224   #endif  //  OPTION_FAMILY15H_KM == TRUE
1225 #else  //  defined (OPTION_FAMILY15H_KM)
1226   #define OPT_F15_KM_CPU
1227   #define OPT_F15_KM_ID
1228 #endif  //  defined (OPTION_FAMILY15H_KM)
1229
1230 /*
1231  * Install unknown family 15h support
1232  */
1233
1234
1235 #if USES_REGISTER_TABLES == TRUE
1236   CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
1237   {
1238     #if BASE_FAMILY_PCI == TRUE
1239       &F15PciRegisterTable,
1240     #endif
1241     #if BASE_FAMILY_MSR == TRUE
1242       &F15MsrRegisterTable,
1243     #endif
1244     // the end.
1245     NULL
1246   };
1247 #endif
1248
1249 #if USES_REGISTER_TABLES == TRUE
1250   CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
1251   {
1252     {MsrRegister, SetRegisterForMsrEntry},
1253     {PciRegister, SetRegisterForPciEntry},
1254     {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
1255     {HtPhyRegister, SetRegisterForHtPhyEntry},
1256     {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
1257     {DeemphasisRegister, SetRegisterForDeemphasisEntry},
1258     {ProfileFixup, SetRegisterForPerformanceProfileEntry},
1259     {HtHostPciRegister, SetRegisterForHtHostEntry},
1260     {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
1261     {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
1262     {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
1263     {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
1264     {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
1265     {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
1266     {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
1267     // End
1268     {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
1269   };
1270 #endif
1271
1272
1273 CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
1274 {
1275   0,
1276   #if DISABLE_PSTATE == TRUE
1277     F15DisablePstate,
1278   #else
1279     (PF_CPU_DISABLE_PSTATE) CommonAssert,
1280   #endif
1281   #if TRANSITION_PSTATE == TRUE
1282     F15TransitionPstate,
1283   #else
1284     (PF_CPU_TRANSITION_PSTATE) CommonAssert,
1285   #endif
1286   #if PROC_IDD_MAX == TRUE
1287     (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
1288   #else
1289     (PF_CPU_GET_IDD_MAX) CommonAssert,
1290   #endif
1291   #if GET_TSC_RATE == TRUE
1292     F15GetTscRate,
1293   #else
1294     (PF_CPU_GET_TSC_RATE) CommonAssert,
1295   #endif
1296   #if GET_NB_FREQ == TRUE
1297     (PF_CPU_GET_NB_FREQ) CommonAssert,
1298   #else
1299     (PF_CPU_GET_NB_FREQ) CommonAssert,
1300   #endif
1301   #if GET_NB_FREQ == TRUE
1302     (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
1303   #else
1304     (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
1305   #endif
1306   #if GET_NB_FREQ == TRUE
1307     (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
1308   #else
1309     (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
1310   #endif
1311   #if IS_NBCOF_INIT_NEEDED == TRUE
1312     (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
1313   #else
1314     (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
1315   #endif
1316   #if GET_NB_IDD_MAX == TRUE
1317     (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1318   #else
1319     (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1320   #endif
1321   #if AP_INITIAL_LAUNCH == TRUE
1322     F15LaunchApCore,
1323   #else
1324     (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
1325   #endif
1326   #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
1327     (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonVoid,
1328   #else
1329     (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
1330   #endif
1331   #if GET_AP_MAILBOX_FROM_HW == TRUE
1332     (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
1333   #else
1334     (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
1335   #endif
1336   #if SET_AP_CORE_NUMBER == TRUE
1337     (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
1338   #else
1339     (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
1340   #endif
1341   #if GET_AP_CORE_NUMBER == TRUE
1342     (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
1343   #else
1344     (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
1345   #endif
1346   #if TRANSFER_AP_CORE_NUMBER == TRUE
1347     (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
1348   #else
1349     (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
1350   #endif
1351   #if ID_POSITION_INITIAL_APICID == TRUE
1352     F15CpuAmdCoreIdPositionInInitialApicId,
1353   #else
1354     (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
1355   #endif
1356   #if SAVE_FEATURES == TRUE
1357     // F15SaveFeatures,
1358     (PF_CPU_SAVE_FEATURES) CommonVoid,
1359   #else
1360     (PF_CPU_SAVE_FEATURES) CommonAssert,
1361   #endif
1362   #if WRITE_FEATURES == TRUE
1363     // F15WriteFeatures,
1364     (PF_CPU_WRITE_FEATURES) CommonVoid,
1365   #else
1366     (PF_CPU_WRITE_FEATURES) CommonAssert,
1367   #endif
1368   #if SET_WARM_RESET_FLAG == TRUE
1369     F15SetAgesaWarmResetFlag,
1370   #else
1371     (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
1372   #endif
1373   #if GET_WARM_RESET_FLAG == TRUE
1374     F15GetAgesaWarmResetFlag,
1375   #else
1376     (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
1377   #endif
1378   #if BRAND_STRING1 == TRUE
1379     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
1380   #else
1381     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1382   #endif
1383   #if BRAND_STRING2 == TRUE
1384     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
1385   #else
1386     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1387   #endif
1388   #if GET_PATCHES == TRUE
1389     GetEmptyArray,
1390   #else
1391     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1392   #endif
1393   #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
1394     GetEmptyArray,
1395   #else
1396     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1397   #endif
1398   #if GET_CACHE_INFO == TRUE
1399     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
1400   #else
1401     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1402   #endif
1403   #if GET_SYSTEM_PM_TABLE == TRUE
1404     GetEmptyArray,
1405   #else
1406     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1407   #endif
1408   #if GET_WHEA_INIT == TRUE
1409     GetF15WheaInitData,
1410   #else
1411     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1412   #endif
1413   #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
1414     (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
1415   #else
1416     (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
1417   #endif
1418   #if IS_NB_PSTATE_ENABLED == TRUE
1419     F15IsNbPstateEnabled,
1420   #else
1421     (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
1422   #endif
1423   #if (BASE_FAMILY_HT_PCI == TRUE)
1424     F15NextLinkHasHtPhyFeats,
1425   #else
1426     (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
1427   #endif
1428   #if (BASE_FAMILY_HT_PCI == TRUE)
1429     F15SetHtPhyRegister,
1430   #else
1431     (PF_SET_HT_PHY_REGISTER) CommonVoid,
1432   #endif
1433   #if BASE_FAMILY_PCI == TRUE
1434     F15GetNextHtLinkFeatures,
1435   #else
1436     (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
1437   #endif
1438   #if USES_REGISTER_TABLES == TRUE
1439     (REGISTER_TABLE **) F15UnknownRegisterTables,
1440   #else
1441     NULL,
1442   #endif
1443   #if USES_REGISTER_TABLES == TRUE
1444     (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
1445   #else
1446     NULL,
1447   #endif
1448   NULL,
1449   NULL,
1450   InitCacheEnabled,
1451   #if AGESA_ENTRY_INIT_EARLY == TRUE
1452     (PF_GET_EARLY_INIT_TABLE) CommonVoid
1453   #else
1454     (PF_GET_EARLY_INIT_TABLE) CommonVoid
1455   #endif
1456 };
1457
1458 // Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
1459 #if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
1460   #undef  FAMILY_MMIO_BASE_MASK
1461   #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
1462 #endif
1463
1464
1465 #undef OPT_F15_ID_TABLE
1466 #define OPT_F15_ID_TABLE {0x15, {AMD_FAMILY_15, AMD_F15_UNKNOWN}, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
1467 #define OPT_F15_UNKNOWN_CPU {AMD_FAMILY_15, &cpuF15UnknownServices},
1468
1469 #undef OPT_F15_TABLE
1470 #define OPT_F15_TABLE   OPT_F15_OR_CPU OPT_F15_TN_CPU OPT_F15_KM_CPU OPT_F15_UNKNOWN_CPU
1471
1472
1473 #if OPTION_G34_SOCKET_SUPPORT == TRUE
1474   #define F15_G34_BRANDSTRING1 NULL,
1475   #define F15_G34_BRANDSTRING2 NULL,
1476 #else
1477   #define F15_G34_BRANDSTRING1
1478   #define F15_G34_BRANDSTRING2
1479 #endif
1480 #if OPTION_C32_SOCKET_SUPPORT == TRUE
1481   #define F15_C32_BRANDSTRING1 NULL,
1482   #define F15_C32_BRANDSTRING2 NULL,
1483 #else
1484   #define F15_C32_BRANDSTRING1
1485   #define F15_C32_BRANDSTRING2
1486 #endif
1487 #if OPTION_AM3_SOCKET_SUPPORT == TRUE
1488   #define F15_AM3_BRANDSTRING1 NULL,
1489   #define F15_AM3_BRANDSTRING2 NULL,
1490 #else
1491   #define F15_AM3_BRANDSTRING1
1492   #define F15_AM3_BRANDSTRING2
1493 #endif
1494 #if OPTION_FS1_SOCKET_SUPPORT == TRUE
1495   #define F15_FS1_BRANDSTRING1 NULL,
1496   #define F15_FS1_BRANDSTRING2 NULL,
1497 #else
1498   #define F15_FS1_BRANDSTRING1
1499   #define F15_FS1_BRANDSTRING2
1500 #endif
1501 #if OPTION_FM2_SOCKET_SUPPORT == TRUE
1502   #define F15_FM2_BRANDSTRING1 NULL,
1503   #define F15_FM2_BRANDSTRING2 NULL,
1504 #else
1505   #define F15_FM2_BRANDSTRING1
1506   #define F15_FM2_BRANDSTRING2
1507 #endif
1508 #if OPTION_FP2_SOCKET_SUPPORT == TRUE
1509   #define F15_FP2_BRANDSTRING1 NULL,
1510   #define F15_FP2_BRANDSTRING2 NULL,
1511 #else
1512   #define F15_FP2_BRANDSTRING1
1513   #define F15_FP2_BRANDSTRING2
1514 #endif
1515 #if OPTION_G2012_SOCKET_SUPPORT == TRUE
1516   #define F15_G2012_BRANDSTRING1 NULL,
1517   #define F15_G2012_BRANDSTRING2 NULL,
1518 #else
1519   #define F15_G2012_BRANDSTRING1
1520   #define F15_G2012_BRANDSTRING2
1521 #endif
1522 #if OPTION_C2012_SOCKET_SUPPORT == TRUE
1523   #define F15_C2012_BRANDSTRING1 NULL,
1524   #define F15_C2012_BRANDSTRING2 NULL,
1525 #else
1526   #define F15_C2012_BRANDSTRING1
1527   #define F15_C2012_BRANDSTRING2
1528 #endif
1529
1530
1531 #if BRAND_STRING1 == TRUE
1532   CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
1533   {
1534     F15_G34_BRANDSTRING1
1535     F15_C32_BRANDSTRING1
1536     F15_AM3_BRANDSTRING1
1537     F15_FS1_BRANDSTRING1
1538     F15_FM2_BRANDSTRING1
1539     F15_FP2_BRANDSTRING1
1540     F15_G2012_BRANDSTRING1
1541     F15_C2012_BRANDSTRING1
1542   };
1543
1544   CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
1545 #endif
1546
1547 #if BRAND_STRING2 == TRUE
1548   CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
1549   {
1550     F15_G34_BRANDSTRING2
1551     F15_C32_BRANDSTRING2
1552     F15_AM3_BRANDSTRING2
1553     F15_FS1_BRANDSTRING2
1554     F15_FM2_BRANDSTRING2
1555     F15_FP2_BRANDSTRING2
1556     F15_G2012_BRANDSTRING2
1557     F15_C2012_BRANDSTRING2
1558   };
1559
1560   CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
1561 #endif
1562
1563 CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
1564 {
1565   OPT_F15_OR_ID
1566   OPT_F15_TN_ID
1567   OPT_F15_KM_ID
1568 };
1569
1570 #endif  // _OPTION_FAMILY_15H_INSTALL_H_