7 * Contains AMD AGESA Integrated Debug Macros
9 * @xrefitem bom "File Content Label" "Release Content"
12 * @e \$Revision: 55079 $ @e \$Date: 2011-06-16 03:48:27 -0600 (Thu, 16 Jun 2011) $
14 /*****************************************************************************
16 * Copyright (C) 2012 Advanced Micro Devices, Inc.
17 * All rights reserved.
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20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
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25 * documentation and/or other materials provided with the distribution.
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ***************************************************************************/
44 /* Macros to aid debugging */
45 /* These definitions expand to zero (0) bytes of code when disabled */
54 // Proto type for optionsids.h
55 typedef UINT32 IDS_STATUS; ///< Status of IDS function.
56 #define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
57 #define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
59 #define IDS_STRINGIZE(a) #a ///< for define stringize macro
61 #define IDS_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
64 * IDS Option Hook Points
66 * These are the values to indicate hook point in AGESA for IDS Options.
69 typedef enum { //vv- for debug reference only
70 IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
71 ///< IDS Object is initialized.
72 ///< Override CPU Core Leveling Mode.
73 ///< Set P-State in Post
74 IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
75 IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
76 ///< It will be used to control the following tables.
77 ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
82 IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
83 IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
84 IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
85 IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
86 ///< Control Interleaving and DRAM memory hole
87 ///< Override the setting of ECC Control
88 ///< Override the setting of Online Spare Rank
89 IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
90 IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
91 IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
92 IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
93 IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
94 IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
95 IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
96 IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
97 IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
98 IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
99 IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
100 IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
101 IDS_BEFORE_PCI_INIT, ///< 13 Override PCI or MSR Registers Before PCI Init
102 IDS_BEFORE_AP_EARLY_HALT, ///< 14 Option Hook Point before AP early halt
103 IDS_BEFORE_S3_RESUME, ///< 15 Option Hook Point before s3 resume
104 IDS_AFTER_S3_RESUME, ///< 16 Option Hook Point after s3 resume
105 IDS_BEFORE_PM_INIT, ///< 17 Option Hook Point Before Pm Init
107 IDS_MT_BASE = 0x20, ///< 0x20 ~ 0x38 24 time points reserved for MTTime
109 IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
110 IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
111 IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
112 IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
113 IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
114 IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
115 IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
116 IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
118 // All the above timing point is used by BVM, their value should never be changed
119 IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control
120 IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
121 IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing
122 ///< Dram Controller, Drive Strength and DQS Timing
123 IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing
124 IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged
125 IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode
126 IDS_BURST_LENGTH32, ///< 46 override Burst Length32
127 IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable
128 IDS_ECC, ///< 48 override ECC parameter
129 IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size
130 IDS_CPU_Early_Override, ///< 4a override CPU early parameter
131 IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt
132 IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave
133 IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery
134 IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times
135 IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit
136 IDS_HT_ASSIST, ///< 50 Override Probe Filter
137 IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result
138 IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down
139 IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement
140 IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature
141 IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure
142 IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support
143 IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory
144 IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service
145 IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake
146 IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config
147 IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration
148 IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep
149 IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config
150 IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings
151 IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature
152 IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control
153 IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around
154 IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register
155 IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop
156 IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation
157 IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions
158 IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry
159 IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround
160 IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit
161 IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting
162 IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting
163 IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg
164 IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature
165 IDS_CST_CREATE, ///< 6d Hook for create _CST
166 IDS_CST_SIZE, ///< 6e Hook for get _CST size
167 IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO
168 IDS_STRETCH_FREQUENCY_LIMIT, ///< 70 Hook for enforcing memory stretch frequency limit
169 IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table
170 IDS_SKIP_FUSED_MAX_RATE, ///< 72 Hook to skip fused max rate cap
171 IDS_FCH_INIT_AT_RESET, ///< 73 Hook for FCH reset parameter
172 IDS_FCH_INIT_AT_ENV, ///< 74 Hook for FCH ENV parameter
173 IDS_ENFORCE_PLAT_TABLES, ///< 75 Hook to enforce platform specific tables
174 IDS_NBPS_MIN_FREQ, ///< 76 Hook for override MIN nb ps freq
175 IDS_GNB_FORCE_CABLESAFE, ///< 77 Hook for override Force Cable Safe
176 IDS_SKIP_PM_TRANSITION_STEP, ///< 78 Hook for provide IDS ability to skip this PM step
177 IDS_GNB_PROPERTY, ///< 79 Hook for GNB Property
178 IDS_GNB_PCIE_POWER_GATING, ///< 7A Hook for GNB PCIe Power Gating
179 IDS_MEM_DYN_DRAM_TERM, ///< 7B Hook for Override Dynamic Dram Term
180 IDS_MEM_DRAM_TERM, ///< 7C Hook for Override Dram Term
181 IDS_TRACE_MODE, ///< 7D Trace Mode
182 IDS_GNB_ALTVDDNB, ///< 7E Hook for Override AltVddNB
183 IDS_UCODE, ///< 7F Enable or Disable microcode patching
184 IDS_FAM_REG_GMMX, ///< 80 GMMX register access
185 IDS_MEMORY_POWER_POLICY, ///< 81 Memory power policy
186 IDS_GET_STRETCH_FREQUENCY_LIMIT, ///< 82 Hook for enforcing memory stretch frequency limit
187 IDS_CPU_FEAT, ///< 83 Hook for runtime force cpu feature disable
188 IDS_OPTION_END, ///< 84 End of IDS option
191 #include "OptionsIds.h"
192 #include "Filecode.h"
194 /* Initialize IDS controls */
195 #ifndef IDSOPT_IDS_ENABLED
196 #define IDSOPT_IDS_ENABLED FALSE
199 #ifndef IDSOPT_CONTROL_ENABLED
200 #define IDSOPT_CONTROL_ENABLED FALSE
203 #ifndef IDSOPT_CONTROL_NV_TO_CMOS
204 #define IDSOPT_CONTROL_NV_TO_CMOS FALSE
207 #ifndef IDSOPT_TRACING_ENABLED
208 #define IDSOPT_TRACING_ENABLED FALSE
211 #ifndef IDSOPT_TRACE_USER_OPTIONS
212 #define IDSOPT_TRACE_USER_OPTIONS TRUE
215 #ifndef IDSOPT_PERF_ANALYSIS
216 #define IDSOPT_PERF_ANALYSIS FALSE
219 #ifndef IDSOPT_HEAP_CHECKING
220 #define IDSOPT_HEAP_CHECKING FALSE
223 #ifndef IDSOPT_ASSERT_ENABLED
224 #define IDSOPT_ASSERT_ENABLED FALSE
227 #ifndef IDSOPT_ERROR_TRAP_ENABLED
228 #define IDSOPT_ERROR_TRAP_ENABLED FALSE
231 #ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
232 #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
235 #ifndef IDSOPT_DEBUG_CODE_ENABLED
236 #define IDSOPT_DEBUG_CODE_ENABLED FALSE
239 #ifndef IDSOPT_IDT_EXCEPTION_TRAP
240 #define IDSOPT_IDT_EXCEPTION_TRAP FALSE
243 #ifndef IDSOPT_C_OPTIMIZATION_DISABLED
244 #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
247 #if IDSOPT_IDS_ENABLED == FALSE
248 #undef IDSOPT_CONTROL_ENABLED
249 #undef IDSOPT_TRACING_ENABLED
250 #undef IDSOPT_PERF_ANALYSIS
251 #undef IDSOPT_HEAP_CHECKING
252 #undef IDSOPT_ASSERT_ENABLED
253 #undef IDSOPT_ERROR_TRAP_ENABLED
254 #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
255 #undef IDSOPT_DEBUG_CODE_ENABLED
256 #undef IDSOPT_TRACE_USER_OPTIONS
258 #define IDSOPT_CONTROL_ENABLED FALSE
259 #define IDSOPT_TRACING_ENABLED FALSE
260 #define IDSOPT_PERF_ANALYSIS FALSE
261 #define IDSOPT_HEAP_CHECKING FALSE
262 #define IDSOPT_ASSERT_ENABLED FALSE
263 #define IDSOPT_ERROR_TRAP_ENABLED FALSE
264 #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
265 #define IDSOPT_DEBUG_CODE_ENABLED FALSE
266 #define IDSOPT_TRACE_USER_OPTIONS FALSE
270 * Make a Progress Report to the User.
272 * This Macro is always enabled. The default action is to write the TestPoint value
273 * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
274 * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
275 * in OptionsIds.h in their build tip.
277 * @param[in] TestPoint The value for display indicating progress
278 * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
282 #define AGESA_TESTPOINT(TestPoint, StdHeader)
284 #ifndef IDS_DEBUG_PORT
285 #define IDS_DEBUG_PORT 0x80
290 * (macro) - Causes program to halt. This is @b only for use during active debugging .
292 * Causes the program to halt and display the file number of the source of the
293 * halt (displayed in decimal).
296 #if IDSOPT_IDS_ENABLED == TRUE
300 #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
301 ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
302 (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
303 #define STOP_HERE IdsErrorStop (STOP_CODE);
305 #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
310 * Test an assertion that the given statement is True.
312 * The statement is evaluated to a boolean value. If the statement is True,
313 * then no action is taken (no error). If the statement is False, a error stop
314 * is generated to halt the program. Used for testing for fatal errors that
315 * must be resolved before production. This is used to do parameter checks,
316 * bounds checking, range checks and 'sanity' checks.
318 * @param[in] conditional Assert that evaluating this conditional results in TRUE.
322 #if IDSOPT_ASSERT_ENABLED == TRUE
326 #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
327 ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
328 (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
330 #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
332 #define ASSERT(conditional)
336 #if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
337 #undef IDSOPT_ERROR_TRAP_ENABLED
338 #define IDSOPT_ERROR_TRAP_ENABLED TRUE
339 #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
341 #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
345 #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
346 #define DEBUG_CODE(Code)
348 #define DEBUG_CODE(Code)
353 * @def IDS_ERROR_TRAP
354 * Trap AGESA Error events with stop code display.
356 * Works similarly to use of "ASSERT (FALSE);"
359 #if IDSOPT_ERROR_TRAP_ENABLED == TRUE
363 #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
364 ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
365 (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
367 #define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE)
369 #define IDS_ERROR_TRAP
372 ///give the extended Macro default value
373 #ifndef __IDS_EXTENDED__
374 #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
375 #define IDS_INITIAL_F10_PM_STEP
376 #define IDS_INITIAL_F12_PM_STEP
377 #define IDS_INITIAL_F14_PM_STEP
378 #define IDS_INITIAL_F15_OR_PM_STEP
379 #define IDS_INITIAL_F15_TN_PM_STEP
380 #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
381 #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
382 #define IDS_EXTENDED_HEAP_SIZE 0
383 #define IDS_EXT_INCLUDE_F10(file)
384 #define IDS_EXT_INCLUDE_F12(file)
385 #define IDS_EXT_INCLUDE_F14(file)
386 #define IDS_EXT_INCLUDE_F15(file)
387 #define IDS_EXT_INCLUDE(file)
391 #ifndef IDS_NUM_NV_ITEM
392 #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
395 #define IDS_CMOS_INDEX_PORT 0x70
396 #define IDS_CMOS_DATA_PORT 0x71
397 #define IDS_CMOS_REGION_START 0x20
398 #define IDS_CMOS_REGION_END 0x7F
399 #define IDS_AP_GET_NV_FROM_CMOS(x) FALSE
401 #if IDSOPT_CONTROL_ENABLED == TRUE
402 #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
404 #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
405 #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
406 #undef IDS_AP_GET_NV_FROM_CMOS
407 #define IDS_AP_GET_NV_FROM_CMOS(x)
408 #ifdef IDS_OPT_CMOS_INDEX_PORT
409 #undef IDS_CMOS_INDEX_PORT
410 #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT
413 #ifdef IDS_OPT_CMOS_DATA_PORT
414 #undef IDS_CMOS_DATA_PORT
415 #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT
418 #ifdef IDS_OPT_CMOS_REGION_START
419 #undef IDS_CMOS_REGION_START
420 #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START
423 #ifdef IDS_OPT_CMOS_REGION_END
424 #undef IDS_CMOS_REGION_END
425 #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END
429 #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
431 #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS
435 * Macro to add a *skip* hook for IDS options
437 * The default minimal action is to do nothing and there is no any code to increase.
438 * For debug environments, IDS dispatcher function will be called to perform
439 * the detailed action and to skip AGESA code if necessary.
441 * @param[in] IdsOption IDS Option ID for this hook point
442 * @param[in, out] DataPtr Data Pointer to override
443 * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
448 #if IDSOPT_CONTROL_ENABLED == TRUE
449 #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
451 #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
455 * Macro to add a heap manager routine
457 * when memory is allocated the heap manager actually allocates two extra dwords of data,
458 * one dword buffer before the actual memory, and one dword afterwards.
459 * a complete heap walk and check to be performed at any time.
460 * it would ASSERT if the heap is corrupt
462 * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
467 // Heap debug feature
468 #define SENTINEL_BEFORE_VALUE 0x64616548 // "Head"
469 #define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail"
470 #if IDSOPT_IDS_ENABLED == TRUE
471 #if IDSOPT_HEAP_CHECKING == TRUE
472 #define SIZE_OF_SENTINEL 4
473 #define NUM_OF_SENTINEL 2 // Before ("Head") and After ("Tail")
474 #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE);
475 #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE);
476 #define Heap_Check(stdheader)
478 #define SIZE_OF_SENTINEL 0
479 #define NUM_OF_SENTINEL 0
480 #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
481 #define SET_SENTINEL_AFTER(NodePtr)
482 #define Heap_Check(stdheader)
485 #define SIZE_OF_SENTINEL 0
486 #define NUM_OF_SENTINEL 0
487 #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
488 #define SET_SENTINEL_AFTER(NodePtr)
489 #define Heap_Check(stdheader)
493 * Macro to add IDT for debugging exception.
495 * A debug feature. Adding a 'jmp $' into every exception handler.
496 * So debugger could use HDT to skip 'jmp $' and execute the iret,
497 * then they could find which instruction cause the exception.
499 * @param[in] FunctionId IDS Function ID for this hook point
500 * @param[in, out] DataPtr Data Pointer to override
501 * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
505 #if IDSOPT_IDS_ENABLED == TRUE
506 #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE
507 #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
509 #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
512 #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
519 * Macro to add HDT OUT
521 * The default minimal action is to do nothing and there is no any code to increase.
522 * For debug environments, the debug information can be displayed in HDT or other
526 #if IDSOPT_IDS_ENABLED == TRUE
527 #if IDSOPT_TRACING_ENABLED == TRUE
528 #define IDS_HDT_CONSOLE_INIT(x)
529 #define IDS_HDT_CONSOLE_EXIT(x)
530 #define IDS_HDT_CONSOLE_S3_EXIT(x)
531 #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
534 #if CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
536 //#define IDS_HDT_CONSOLE(f, s, args...) do {do_printk(BIOS_DEBUG, s, ##args);} while (0)
537 #define IDS_HDT_CONSOLE(f, s, args...) do {\
538 if (f == MAIN_FLOW) {\
539 do_printk(BIOS_DEBUG, s, ##args);\
540 } else if (f == MEM_FLOW) {\
541 do_printk(BIOS_DEBUG, s, ##args);\
542 } else if (f == CPU_TRACE) {\
543 do_printk(BIOS_DEBUG, s, ##args);\
544 } else if (f == HT_TRACE) {\
545 do_printk(BIOS_DEBUG, s, ##args);\
546 } else if (f == GNB_TRACE) {\
547 do_printk(BIOS_DEBUG, s, ##args);\
548 } else if (f == FCH_TRACE) {\
549 do_printk(BIOS_DEBUG, s, ##args);\
553 #define IDS_HDT_CONSOLE(s, args...) do {} while(0)
556 #define IDS_HDT_CONSOLE(s, args...)
559 #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
560 #define IDS_HDT_CONSOLE_ASSERT(x)
561 #define IDS_FUNCLIST_ADDR NULL
562 #define IDS_FUNCLIST_EXTERN()
563 #define IDS_TIMEOUT_CTL(t)
564 #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
565 //#define CONSOLE(s, ...)
567 #define IDS_HDT_CONSOLE_INIT(x)
568 #define IDS_HDT_CONSOLE_EXIT(x)
569 #define IDS_HDT_CONSOLE_S3_EXIT(x)
570 #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
571 #define IDS_HDT_CONSOLE(f, s, ...)
572 #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
573 #define IDS_HDT_CONSOLE_ASSERT(x)
574 #define IDS_FUNCLIST_ADDR NULL
575 #define IDS_FUNCLIST_EXTERN()
576 #define IDS_TIMEOUT_CTL(t)
577 #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
578 //#define CONSOLE(s, ...) CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
581 #define IDS_HDT_CONSOLE_INIT(x)
582 #define IDS_HDT_CONSOLE_EXIT(x)
583 #define IDS_HDT_CONSOLE_S3_EXIT(x)
584 #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
585 #define IDS_HDT_CONSOLE(f, s, ...)
586 #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
587 #define IDS_HDT_CONSOLE_ASSERT(x)
588 #define IDS_FUNCLIST_ADDR NULL
589 #define IDS_FUNCLIST_EXTERN()
590 #define IDS_TIMEOUT_CTL(t)
591 #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
592 // #define CONSOLE(s, ...) CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
595 #define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
597 #if IDSOPT_PERF_ANALYSIS == TRUE
598 #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
599 #define IDS_PERF_ANALYSE(StdHeader)
600 #define IDS_PERF_TIME_MEASURE(StdHeader)
602 #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
603 #define IDS_PERF_ANALYSE(StdHeader)
604 #define IDS_PERF_TIME_MEASURE(StdHeader)
608 #define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull
609 #define IDS_BSP_ONLY TRUE
610 #define IDS_ALL_CORES FALSE
612 #define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_LIBRARY_IDSLIB_FILECODE
614 #define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization.
616 /// Function entry for HDT script to call
617 typedef struct _SCRIPT_FUNCTION {
618 UINT32 FuncAddr; ///< Function address in ROM
619 CHAR8 FuncName[40]; ///< Function name
622 /// Data Structure for Mem ECC parameter override
624 IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
625 IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
626 IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
627 IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
628 IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
629 IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
630 IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
631 } ECC_OVERRIDE_STRUCT;
639 * These are the values displayed to the user to indicate progress through boot.
640 * These can be used in a debug environment to stop the debugger at a specific
642 * For SimNow!, this command
644 * will stop the debugger on one of the TracePoints (49 is the TP value in this example).
648 StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
650 // Memory test points
651 TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
652 TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
653 TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
654 TpProcMemDramInit, ///< 04 .. DRAM initialization
655 TpProcMemSPDChecking, ///< 05 ..
656 TpProcMemModeChecking, ///< 06 ..
657 TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
658 TpProcMemSpdTiming, ///< 08 ..
659 TpProcMemDramMapping, ///< 09 ..
660 TpProcMemPlatformSpecificConfig, ///< 0A ..
661 TPProcMemPhyCompensation, ///< 0B ..
662 TpProcMemStartDcts, ///< 0C ..
663 TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
664 TpProcMemPhyFenceTraining, ///< 0E ..
665 TpProcMemSynchronizeDcts, ///< 0F ..
666 TpProcMemSystemMemoryMapping, ///< 10 ..
667 TpProcMemMtrrConfiguration, ///< 11 ..
668 TpProcMemDramTraining, ///< 12 ..
669 TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
670 TpProcMemWriteLevelizationTraining, ///< 14 ..
671 TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
672 TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
673 TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured
674 TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
675 TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
676 TpProcMemReceiverEnableTraining, ///< 1A ..
677 TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
678 TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
679 TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
680 TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
681 TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
682 TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
683 TpProcMemReceiveDqsTraining, ///< 21 ..
684 TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
685 TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
686 TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
687 TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
688 TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
689 TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
690 TpProcMemRcvDqsResults, ///< 28 .. Update results
691 TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
692 TpProcMemTransmitDqsTraining, ///< 2A ..
693 TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
694 TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
695 TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
696 TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
697 TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
698 TpProcMemTxDqResults, ///< 30 .. Update results
699 TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
700 TpProcMemMaxRdLatencyTraining, ///< 32 ..
701 TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
702 TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
703 TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
704 TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
705 TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
706 TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
707 TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
708 TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
709 TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
710 TpProcMemEccInitialization, ///< 3C .. ECC initialization
711 TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
712 TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
713 TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
714 TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
715 TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
716 TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
717 TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
718 TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
719 TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
720 TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
721 TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
722 TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
723 TpProcMemInitMCT, ///< 49 .. Before InitMCT
724 TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
725 TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
726 TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
727 TpProcMemMemClr, ///< 4D .. Before MemClr
728 TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
729 TpProcMemDmi, ///< 4F .. Before DMI
730 TpProcMemEnd, ///< 50 .. End of memory code
733 TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
734 TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
735 TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
736 TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
737 TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
738 TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
739 TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
740 TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
741 TpProcCpuSetBrandID, ///< 59 .. Set brand ID
742 TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
743 TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
744 TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
745 TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
746 TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
747 TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
748 TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
749 TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
750 TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling
751 TpProcCpuBeforeRelinquishAPsFeatureInit, ///< 63 .. Before Relinquishing control of APs feature dispatch point
752 TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer
753 TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer
754 TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer
755 TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer
756 TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer
757 TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer
758 TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer
759 TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer
762 TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface)
763 TpProcHtTopology, ///< 72 .. Topology match, routing, begin
764 TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin
765 TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin
766 TpProcHtOptGather, ///< 75 .. Optimization: Gather begin
767 TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin
768 TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin
769 TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin
770 TpProcHtOptFinish, ///< 79 .. Optimization: Set begin
771 TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin
772 TpProcHtTuning, ///< 7B .. Misc Tuning Begin
773 TpProcHtDone, ///< 7C .. HT Init complete
774 TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin
775 TpProcHtApMapDone, ///< 7E .. AP HT: Complete
777 // Extended memory test point
778 TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2
779 TpProcMemSendMRS3, ///< 81 .. Sedding MRS3
780 TpProcMemSendMRS1, ///< 82 .. Sending MRS1
781 TpProcMemSendMRS0, ///< 83 .. Sending MRS0
782 TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read
783 TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write
784 TpProcMem__RdDqsTraining, ///< 86 .. Mem: RdDqs Training begin
785 TpProcMemBefore__TrainExtVrefChange,///< 87 .. Mem: Before optional callout to platfrom BIOS to change External Vref during training
786 TpProcMemAfter__TrainExtVrefChange, ///< 88 .. Mem: After optional callout to platfrom BIOS to change External Vref during training
788 StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs
790 EndNbTestPoints, ///< 92 End of TP range for NB
792 StartFchTestPoints = 0xB0, ///< B0 Entry used for range testing for @b FCH related TPs
793 TpFchInitResetDispatching, ///< B1 .. FCH InitReset dispatch point
794 TpFchGppBeforePortTraining, ///< B2 .. Before FCH GPP port training
795 TpFchGppGen1PortPolling, ///< B3 .. FCH GPP port polling with GEN1 speed
796 TpFchGppGen2PortPolling, ///< B4 .. FCH GPP port polling with GEN2 speed
797 TpFchGppAfterPortTraining, ///< B5 .. After FCH GPP port training
798 TpFchInitEnvDispatching, ///< B6 .. FCH InitEnv dispatch point
799 TpFchInitMidDispatching, ///< B7 .. FCH InitMid dispatch point
800 TpFchInitLateDispatching, ///< B8 .. FCH InitLate dispatch point
801 TpFchGppHotPlugging, ///< B9 .. FCH GPP hot plug event
802 TpFchGppHotUnplugging, ///< BA .. AFCH GPP hot unplug event
803 TpFchInitS3EarlyDispatching, ///< BB .. FCH InitS3Early dispatch point
804 TpFchInitS3LateDispatching, ///< BC .. FCH InitS3Late dispatch point
805 EndFchTestPoints, ///< BF End of TP range for FCH
807 // Interface test points
808 TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
809 TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
810 TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
811 TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
812 TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
813 TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
814 TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
815 TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
816 TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
817 TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
818 TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
819 TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
820 TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
821 TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
822 TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
823 TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
824 TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
825 TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
826 TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
827 TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
828 TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
829 TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
830 TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
831 TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
832 TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
833 TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
834 TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
835 TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
836 TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
837 TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
838 TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
839 TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
840 TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
841 TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
842 TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
843 TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
844 TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
845 TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
846 TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
847 TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
848 TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
849 TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
850 TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
851 TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
852 TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
853 TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
854 TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
855 TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
856 TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
857 TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
858 TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
859 TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
860 TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
861 TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
862 TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
863 TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
864 TpPerfUnit, ///< F8 .. The Unit of performance measure.
865 EndAgesaTps = 0xFF, ///< Last defined AGESA TP
868 ///Ids Feat description
870 IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
871 IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
872 IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
873 IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
874 IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
875 IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
876 IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
877 IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
878 IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
879 IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
880 IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter
881 IDS_FEAT_HDTOUT, ///< Feat for hdt out
882 IDS_FEAT_HT_SETTING, ///< Feat for Ht setting
883 IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
884 IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
885 IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
886 IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
887 IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy
888 IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS
889 IDS_FEAT_COMMON, ///< Common Feat
890 IDS_FEAT_END = 0xFF ///< End of Common feat
893 ///Ids IDT table function ID
895 IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000, ///< Function ID for saving IDTR for BSC
896 IDS_IDT_RESTORE_IDTR_FOR_BSC, ///< Function ID for restoring IDTR for BSC
897 IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, ///< Function ID for updating exception vector
900 typedef IDS_STATUS IDS_COMMON_FUNC (
901 IN OUT VOID *DataPtr,
902 IN OUT AMD_CONFIG_PARAMS *StdHeader,
903 IN IDS_NV_ITEM *IdsNvPtr
906 typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
908 /// Data Structure of IDS Feature block
909 typedef struct _IDS_FAMILY_FEAT_STRUCT {
910 IDS_FEAT IdsFeat; ///< Ids Feat ID
911 BOOLEAN IsBsp; ///< swith for Bsp check
912 AGESA_IDS_OPTION IdsOption; ///< IDS option
913 UINT64 CpuFamily; ///<
914 PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
915 } IDS_FAMILY_FEAT_STRUCT;
918 /// Data Structure of IDS option
919 typedef struct _IDS_OPTION_STRUCT {
920 AGESA_IDS_OPTION idsoption; ///< IDS option
921 PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
924 /// Data Structure of IDS option table
925 typedef struct _IDS_OPTION_STRUCT_TBL {
926 UINT8 version; ///<Version of IDS option table
927 UINT16 size; ///<Size of IDS option table
928 CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
929 } IDS_OPTION_STRUCT_TBL;
931 #define IDS_NV_TO_CMOS_LEN_BYTE 1
932 #define IDS_NV_TO_CMOS_LEN_WORD 2
933 #define IDS_NV_TO_CMOS_LEN_END 0xFF
934 #define IDS_NV_TO_CMOS_ID_END 0xFFFF
936 /// Data struct of set/get NV to/from CMOS
937 typedef struct _IDS_NV_TO_CMOS {
938 UINT8 Length; ///< Length of NV
939 UINT16 IDS_NV_ID; ///< IDS id
943 AmdIdsCtrlDispatcher (
944 IN AGESA_IDS_OPTION IdsOption,
945 IN OUT VOID *DataPtr,
946 IN OUT AMD_CONFIG_PARAMS *StdHeader
952 IN OUT VOID *DataPtr,
953 IN OUT AMD_CONFIG_PARAMS *StdHeader
957 AmdIdsDebugPrintInit (
958 IN OUT AMD_CONFIG_PARAMS *StdHeader
962 AmdIdsDebugPrintExit (
963 IN OUT AMD_CONFIG_PARAMS *StdHeader
967 AmdIdsDebugPrintS3Exit (
968 IN OUT AMD_CONFIG_PARAMS *StdHeader
972 AmdIdsDebugPrintS3ApExit (
973 IN OUT AMD_CONFIG_PARAMS *StdHeader
990 AmdIdsDebugPrintCpu (
996 AmdIdsDebugPrintMem (
1002 AmdIdsDebugPrintGnb (
1008 AmdIdsDebugPrintFlush (
1009 IN OUT AMD_CONFIG_PARAMS *StdHeader
1014 IN OUT VOID *DataPtr
1019 IN AGESA_TP TestPoint,
1020 IN OUT AMD_CONFIG_PARAMS *StdHeader
1024 * IDS Backend Function for ASSERT
1026 * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
1027 * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
1028 * to help distinguish the stop code from a post code loop.
1029 * Additional features may be available if using simulation.
1031 * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
1033 * @retval TRUE No error
1041 * The engine code for ASSERT MACRO
1043 * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
1044 * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
1045 * to help distinguish the stop code from a post code loop.
1046 * Additional features may be available if using simulation.
1048 * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
1062 AmdHeapIntactCheck (
1063 IN AMD_CONFIG_PARAMS *StdHeader
1067 IdsCarCorruptionCheck (
1068 IN OUT AMD_CONFIG_PARAMS *StdHeader
1073 IN IDS_IDT_FUNC_ID IdsIdtFuncId,
1075 IN OUT AMD_CONFIG_PARAMS *StdHeader
1078 #if IDSOPT_IDS_ENABLED == FALSE
1079 #undef IEM_SKIP_CODE
1080 #undef IEM_INSERT_CODE
1082 #ifndef IEM_SKIP_CODE
1083 #define IEM_SKIP_CODE(L)
1085 #ifndef IEM_INSERT_CODE
1086 #define IEM_INSERT_CODE(L,Fn,Parm)
1089 //Note a is from 0 to 63
1090 #define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
1091 //If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
1093 #define MEM_SETREG DEBUG_PRINT_SHIFT (0)
1094 #define MEM_GETREG DEBUG_PRINT_SHIFT (1)
1095 #define MEM_FLOW DEBUG_PRINT_SHIFT (2)
1096 #define MEM_STATUS DEBUG_PRINT_SHIFT (3)
1097 #define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4)
1098 #define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
1099 #define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
1100 #define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
1101 #define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
1102 #define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
1107 #define CPU_TRACE DEBUG_PRINT_SHIFT (10)
1108 #define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
1109 #define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
1110 #define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
1111 #define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
1112 #define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
1113 #define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
1114 #define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
1115 #define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
1116 #define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
1119 #define GNB_TRACE DEBUG_PRINT_SHIFT (20)
1120 #define PCIE_MISC DEBUG_PRINT_SHIFT (21)
1121 #define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
1122 #define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
1123 #define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
1124 #define NB_MISC DEBUG_PRINT_SHIFT (25)
1125 #define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
1126 #define GFX_MISC DEBUG_PRINT_SHIFT (27)
1127 #define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
1128 #define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
1131 #define HT_TRACE DEBUG_PRINT_SHIFT (30)
1132 #define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
1133 #define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
1134 #define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
1135 #define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
1136 #define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
1137 #define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
1138 #define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
1139 #define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
1140 #define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
1143 #define FCH_TRACE DEBUG_PRINT_SHIFT (40)
1144 #define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
1145 #define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
1146 #define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
1147 #define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
1148 #define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
1149 #define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
1150 #define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
1151 #define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
1152 #define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
1155 #define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
1156 #define EVENT_LOG DEBUG_PRINT_SHIFT (51)
1157 #define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
1160 #define IDS_TRACE DEBUG_PRINT_SHIFT (53)
1161 #define IDS_REG DEBUG_PRINT_SHIFT (54)
1162 #define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
1163 #define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
1166 #define S3_TRACE DEBUG_PRINT_SHIFT (57)
1168 //Library function to read/write PCI/MSR registers
1169 #define LIB_PCI_RD DEBUG_PRINT_SHIFT (58)
1170 #define LIB_PCI_WR DEBUG_PRINT_SHIFT (59)
1173 #define TRACE_RSV3 DEBUG_PRINT_SHIFT (60)
1174 #define TRACE_RSV4 DEBUG_PRINT_SHIFT (61)
1175 #define TRACE_RSV5 DEBUG_PRINT_SHIFT (62)
1176 #define TRACE_RSV6 DEBUG_PRINT_SHIFT (63)