5 * Agesa structures and definitions
7 * Contains AMD AGESA core interface
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: Include
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
14 /*****************************************************************************
16 * Copyright (C) 2012 Advanced Micro Devices, Inc.
17 * All rights reserved.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ***************************************************************************/
48 #define AGESA_REVISION "Arch2008"
49 #define AGESA_ID "AGESA"
51 #define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
52 #define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
55 // AGESA Types and Definitions
58 #define LAST_ENTRY 0xFFFFFFFF
59 #define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
63 /// The return status for all AGESA public services.
65 /// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
66 /// will have log entries with more detail.
69 AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
70 AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
72 AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
73 ///< Example, memory address not installed, heap buffer handle not found.
75 // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
76 AGESA_ALERT, ///< An observed condition, but no loss of function.
77 ///< See log. Example, HT CRC.
78 AGESA_WARNING, ///< Possible or minor loss of function. See Log.
79 AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
80 AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
81 AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
82 ///< may not be able to reliably produce log events.
83 AgesaStatusMax ///< Not a status, for limit checking.
86 /// For checking whether a status is at or above the mandatory log level.
87 #define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
90 * Callout method to the host environment.
92 * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
94 * @param[in] Function The specific callout function being invoked.
95 * @param[in] FcnData Function specific data item.
96 * @param[in,out] ConfigPtr Reference to Callout params.
98 typedef AGESA_STATUS (*CALLOUT_ENTRY) (
101 IN OUT VOID *ConfigPtr
104 typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
105 typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
107 ///This allocation type is used by the AmdCreateStruct entry point
109 PreMemHeap = 0, ///< Create heap in cache.
110 PostMemDram, ///< Create heap in memory.
111 ByHost ///< Create heap by Host.
114 /// These width descriptors are used by the library function, and others, to specify the data size
115 typedef enum ACCESS_WIDTH {
116 AccessWidth8 = 1, ///< Access width is 8 bits.
117 AccessWidth16, ///< Access width is 16 bits.
118 AccessWidth32, ///< Access width is 32 bits.
119 AccessWidth64, ///< Access width is 64 bits.
121 AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
122 AccessS3SaveWidth16, ///< Save 16 bits data.
123 AccessS3SaveWidth32, ///< Save 32 bits data.
124 AccessS3SaveWidth64, ///< Save 64 bits data.
127 /// AGESA struct name
129 // AGESA BASIC FUNCTIONS
130 AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
131 AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
132 AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
133 AMD_INIT_ENV, ///< AmdInitEnv entry point handle
134 AMD_INIT_LATE, ///< AmdInitLate entry point handle
135 AMD_INIT_MID, ///< AmdInitMid entry point handle
136 AMD_INIT_POST, ///< AmdInitPost entry point handle
137 AMD_INIT_RESET, ///< AmdInitReset entry point handle
138 AMD_INIT_RESUME, ///< AmdInitResume entry point handle
139 AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
140 AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
141 AMD_S3_SAVE, ///< AmdS3Save entry point handle
142 AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
143 AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
144 AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
145 AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
146 AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
147 AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
148 AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
151 /* ResetType constant values */
152 #define WARM_RESET_WHENEVER 1
153 #define COLD_RESET_WHENEVER 2
154 #define WARM_RESET_IMMEDIATELY 3
155 #define COLD_RESET_IMMEDIATELY 4
160 /// The standard header for all AGESA services.
161 /// For internal AGESA naming conventions, see @ref amdconfigparamname .
163 IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
164 IN UINT32 Func; ///< The service desired
165 IN UINT32 AltImageBasePtr; ///< Alternate Image location
166 IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
167 IN UINT8 HeapStatus; ///< For heap status from boot time slide.
168 IN UINT64 HeapBasePtr; ///< Location of the heap
169 IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
173 /// Create Struct Interface.
175 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
176 IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
177 IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
178 IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
179 IN OUT VOID *NewStructPtr; ///< The struct for the service.
180 ///< The struct to init for ByHost allocation,
181 ///< the initialized struct on return.
182 } AMD_INTERFACE_PARAMS;
184 #define FUNC_0 0 // bit-placed for PCI address creation
193 /// AGESA Binary module header structure
195 IN UINT32 Signature; ///< Binary Signature
196 IN CHAR8 CreatorID[8]; ///< 8 characters ID
197 IN CHAR8 Version[12]; ///< 12 characters version
198 IN UINT32 ModuleInfoOffset; ///< Offset of module
199 IN UINT32 EntryPointAddress; ///< Entry address
200 IN UINT32 ImageBase; ///< Image base
201 IN UINT32 RelocTableOffset; ///< Relocate Table offset
202 IN UINT32 ImageSize; ///< Size
203 IN UINT16 Checksum; ///< Checksum
204 IN UINT8 ImageType; ///< Type
205 IN UINT8 V_Reserved; ///< Reserved
207 /// AGESA Binary module header structure
208 typedef struct _AMD_MODULE_HEADER {
209 IN UINT32 ModuleHeaderSignature; ///< Module signature
210 IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
211 IN CHAR8 ModuleVersion[12]; ///< 12 characters version
212 IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
213 IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
216 // AMD_CODE_HEADER Signatures.
217 #define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
218 #define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
219 #define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
221 /// AGESA_CODE_SIGNATURE
223 IN CHAR8 Signature[8]; ///< code header Signature
224 IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
225 IN CHAR8 Version[12]; ///< 12 character version string
226 IN CHAR8 TerminatorNull; ///< null terminated string
227 IN CHAR8 VerReserved[7]; ///< reserved space
230 /// Extended PCI address format
232 IN OUT UINT32 Register:12; ///< Register offset
233 IN OUT UINT32 Function:3; ///< Function number
234 IN OUT UINT32 Device:5; ///< Device number
235 IN OUT UINT32 Bus:8; ///< Bus number
236 IN OUT UINT32 Segment:4; ///< Segment
239 /// Union type for PCI address
240 typedef union _PCI_ADDR {
241 IN UINT32 AddressValue; ///< Formal address
242 IN EXT_PCI_ADDR Address; ///< Extended address
245 // SBDFO - Segment Bus Device Function Offset
246 // 31:28 Segment (4-bits)
247 // 27:20 Bus (8-bits)
248 // 19:15 Device (5-bits)
249 // 14:12 Function(3-bits)
250 // 11:00 Offset (12-bits)
252 #define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
253 (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
254 #define ILLEGAL_SBDFO 0xFFFFFFFF
256 /// CPUID data received registers format
258 OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
259 OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
260 OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
261 OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
264 /// HT frequency for external callbacks
266 HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
267 HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
268 HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
269 HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
270 HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
271 HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
272 HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
273 HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
274 HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
275 HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
276 HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
277 HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
278 HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
279 HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
280 HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
281 HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
282 HT_FREQUENCY_MAX ///< Limit check.
284 // The minimum HT3 frequency
285 #define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
288 #define BIT0 0x0000000000000001ull
291 #define BIT1 0x0000000000000002ull
294 #define BIT2 0x0000000000000004ull
297 #define BIT3 0x0000000000000008ull
300 #define BIT4 0x0000000000000010ull
303 #define BIT5 0x0000000000000020ull
306 #define BIT6 0x0000000000000040ull
309 #define BIT7 0x0000000000000080ull
312 #define BIT8 0x0000000000000100ull
315 #define BIT9 0x0000000000000200ull
318 #define BIT10 0x0000000000000400ull
321 #define BIT11 0x0000000000000800ull
324 #define BIT12 0x0000000000001000ull
327 #define BIT13 0x0000000000002000ull
330 #define BIT14 0x0000000000004000ull
333 #define BIT15 0x0000000000008000ull
336 #define BIT16 0x0000000000010000ull
339 #define BIT17 0x0000000000020000ull
342 #define BIT18 0x0000000000040000ull
345 #define BIT19 0x0000000000080000ull
348 #define BIT20 0x0000000000100000ull
351 #define BIT21 0x0000000000200000ull
354 #define BIT22 0x0000000000400000ull
357 #define BIT23 0x0000000000800000ull
360 #define BIT24 0x0000000001000000ull
363 #define BIT25 0x0000000002000000ull
366 #define BIT26 0x0000000004000000ull
369 #define BIT27 0x0000000008000000ull
372 #define BIT28 0x0000000010000000ull
375 #define BIT29 0x0000000020000000ull
378 #define BIT30 0x0000000040000000ull
381 #define BIT31 0x0000000080000000ull
384 #define BIT32 0x0000000100000000ull
387 #define BIT33 0x0000000200000000ull
390 #define BIT34 0x0000000400000000ull
393 #define BIT35 0x0000000800000000ull
396 #define BIT36 0x0000001000000000ull
399 #define BIT37 0x0000002000000000ull
402 #define BIT38 0x0000004000000000ull
405 #define BIT39 0x0000008000000000ull
408 #define BIT40 0x0000010000000000ull
411 #define BIT41 0x0000020000000000ull
414 #define BIT42 0x0000040000000000ull
417 #define BIT43 0x0000080000000000ull
420 #define BIT44 0x0000100000000000ull
423 #define BIT45 0x0000200000000000ull
426 #define BIT46 0x0000400000000000ull
429 #define BIT47 0x0000800000000000ull
432 #define BIT48 0x0001000000000000ull
435 #define BIT49 0x0002000000000000ull
438 #define BIT50 0x0004000000000000ull
441 #define BIT51 0x0008000000000000ull
444 #define BIT52 0x0010000000000000ull
447 #define BIT53 0x0020000000000000ull
450 #define BIT54 0x0040000000000000ull
453 #define BIT55 0x0080000000000000ull
456 #define BIT56 0x0100000000000000ull
459 #define BIT57 0x0200000000000000ull
462 #define BIT58 0x0400000000000000ull
465 #define BIT59 0x0800000000000000ull
468 #define BIT60 0x1000000000000000ull
471 #define BIT61 0x2000000000000000ull
474 #define BIT62 0x4000000000000000ull
477 #define BIT63 0x8000000000000000ull