src/vendorcode/amd/agesa/f15/AGESA.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * Agesa structures and definitions
   6  *
   7  * Contains AMD AGESA core interface
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      AGESA
  11  * @e sub-project:  Include
  12  * @e \$Revision: 60222 $   @e \$Date: 2011-10-10 23:39:36 -0600 (Mon, 10 Oct 2011) $
  13  */
  14 /*****************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *
  42  ***************************************************************************/
  43
  44
  45 #ifndef _AGESA_H_
  46 #define _AGESA_H_
  47
  48 #include  "Porting.h"
  49 #include  "AMD.h"
  50
  51 //
  52 //
  53 // AGESA Types and Definitions
  54 //
  55 //
  56
  57 // AGESA BASIC CALLOUTS
  58 #define AGESA_MEM_RELEASE              0x00028000
  59
  60 // AGESA ADVANCED CALLOUTS, Processor
  61 #define AGESA_CHECK_UMA                0x00028100
  62 #define AGESA_DO_RESET                 0x00028101
  63 #define AGESA_ALLOCATE_BUFFER          0x00028102
  64 #define AGESA_DEALLOCATE_BUFFER        0x00028103
  65 #define AGESA_LOCATE_BUFFER            0x00028104
  66 #define AGESA_RUNFUNC_ONAP             0x00028105
  67
  68 // AGESA ADVANCED CALLOUTS, HyperTransport
  69
  70 // AGESA ADVANCED CALLOUTS, Memory
  71 #define AGESA_READ_SPD                 0x00028140
  72 #define AGESA_HOOKBEFORE_DRAM_INIT     0x00028141
  73 #define AGESA_HOOKBEFORE_DQS_TRAINING  0x00028142
  74 #define AGESA_READ_SPD_RECOVERY        0x00028143
  75 #define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
  76 #define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY     0x00028145
  77 #define AGESA_EXTERNAL____TRAIN_VREF_CHANGE     0x00028146
  78
  79 // AGESA IDS CALLOUTS
  80 #define AGESA_GET_IDS_INIT_DATA       0x00028200
  81
  82 // AGESA GNB CALLOUTS
  83 #define AGESA_GNB_PCIE_SLOT_RESET      0x00028301
  84
  85 // AGESA FCH CALLOUTS
  86 #define AGESA_FCH_OEM_CALLOUT          0x00028401
  87
  88 //------------------------------------------------------------------------
  89 //
  90 // HyperTransport Interface
  91
  92
  93
  94 //-----------------------------------------------------------------------------
  95 //                         HT DEFINITIONS AND MACROS
  96 //
  97 //-----------------------------------------------------------------------------
  98
  99
 100 // Width equates for call backs
 101 #define HT_WIDTH_8_BITS              8                          ///< Specifies 8 bit, or up to 8 bit widths.
 102 #define HT_WIDTH_16_BITS             16                         ///< Specifies 16 bit, or up to 16 bit widths.
 103 #define HT_WIDTH_4_BITS              4
 104 #define HT_WIDTH_2_BITS              2
 105 #define HT_WIDTH_NO_LIMIT            HT_WIDTH_16_BITS
 106
 107 // Frequency Limit equates for call backs which take a frequency supported mask.
 108 #define HT_FREQUENCY_LIMIT_200M      1                           ///< Specifies a limit of no more than 200 MHz HT frequency.
 109 #define HT_FREQUENCY_LIMIT_400M      7                           ///< Specifies a limit of no more than 400 MHz HT frequency.
 110 #define HT_FREQUENCY_LIMIT_600M      0x1F                        ///< Specifies a limit of no more than 600 MHz HT frequency.
 111 #define HT_FREQUENCY_LIMIT_800M      0x3F                        ///< Specifies a limit of no more than 800 MHz HT frequency.
 112 #define HT_FREQUENCY_LIMIT_1000M     0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
 113 #define HT_FREQUENCY_LIMIT_HT1_ONLY  0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
 114 #define HT_FREQUENCY_LIMIT_1200M     0xFF                        ///< Specifies a limit of no more than 1200 MHz HT frequency.
 115 #define HT_FREQUENCY_LIMIT_1400M     0x1FF                       ///< Specifies a limit of no more than 1400 MHz HT frequency.
 116 #define HT_FREQUENCY_LIMIT_1600M     0x3FF                       ///< Specifies a limit of no more than 1600 MHz HT frequency.
 117 #define HT_FREQUENCY_LIMIT_1800M     0x7FF                       ///< Specifies a limit of no more than 1800 MHz HT frequency.
 118 #define HT_FREQUENCY_LIMIT_2000M     0xFFF                       ///< Specifies a limit of no more than 2000 MHz HT frequency.
 119 #define HT_FREQUENCY_LIMIT_2200M     0x1FFF                      ///< Specifies a limit of no more than 2200 MHz HT frequency.
 120 #define HT_FREQUENCY_LIMIT_2400M     0x3FFF                      ///< Specifies a limit of no more than 2400 MHz HT frequency.
 121 #define HT_FREQUENCY_LIMIT_2600M     0x7FFF                      ///< Specifies a limit of no more than 2600 MHz HT frequency.
 122 #define HT_FREQUENCY_LIMIT_2800M     0x27FFF                     ///< Specifies a limit of no more than 2800 MHz HT frequency.
 123 #define HT_FREQUENCY_LIMIT_3000M     0x67FFF                     ///< Specifies a limit of no more than 3000 MHz HT frequency.
 124 #define HT_FREQUENCY_LIMIT_3200M     0xE7FFF                     ///< Specifies a limit of no more than 3200 MHz HT frequency.
 125 #define HT_FREQUENCY_LIMIT_3600M     0x1E7FFF
 126 #define HT_FREQUENCY_LIMIT_MAX       HT_FREQUENCY_LIMIT_3600M
 127 #define HT_FREQUENCY_NO_LIMIT        0xFFFFFFFF                  ///< Specifies a no limit of HT frequency.
 128
 129 // Unit ID Clumping special values
 130 #define HT_CLUMPING_DISABLE          0x00000000
 131 #define HT_CLUMPING_NO_LIMIT         0xFFFFFFFF
 132
 133 #define HT_LIST_TERMINAL             0xFF             ///< End of list.
 134 #define HT_LIST_MATCH_ANY            0xFE             ///< Match Any value, used for Sockets, Links, IO Chain Depth.
 135 #define HT_LIST_MATCH_INTERNAL_LINK  0xFD             ///< Match all of the internal links.
 136
 137 // Event Notify definitions
 138
 139 // Event definitions.
 140
 141 // Coherent subfunction events
 142 #define HT_EVENT_COH_EVENTS             0x10001000
 143 #define HT_EVENT_COH_NO_TOPOLOGY        0x10011000    ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
 144 #define HT_EVENT_COH_OBSOLETE000        0x10021000    //   No longer used.
 145 #define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000    ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
 146 #define HT_EVENT_COH_NODE_DISCOVERED    0x10041000    ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
 147 #define HT_EVENT_COH_MPCAP_MISMATCH     0x10051000    ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
 148
 149 // Non-coherent subfunction events
 150 #define HT_EVENT_NCOH_EVENTS         0x10002000
 151 #define HT_EVENT_NCOH_BUID_EXCEED    0x10012000       ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
 152 #define HT_EVENT_NCOH_OBSOLETE000    0x10022000       //   No longer used.
 153 #define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000       ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
 154 #define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000       ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
 155 #define HT_EVENT_NCOH_DEVICE_FAILED  0x10052000       ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
 156 #define HT_EVENT_NCOH_AUTO_DEPTH     0x10062000       ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
 157
 158 // Optimization subfunction events
 159 #define HT_EVENT_OPT_EVENTS               0x10003000
 160 #define HT_EVENT_OPT_REQUIRED_CAP_RETRY   0x10013000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
 161 #define HT_EVENT_OPT_REQUIRED_CAP_GEN3    0x10023000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
 162 #define HT_EVENT_OPT_UNUSED_LINKS         0x10033000  ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
 163 #define HT_EVENT_OPT_LINK_PAIR_EXCEED     0x10043000  ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
 164
 165 // HW Fault events
 166 #define HT_EVENT_HW_EVENTS           0x10004000
 167 #define HT_EVENT_HW_SYNCFLOOD        0x10014000       ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
 168 #define HT_EVENT_HW_HTCRC            0x10024000       ///< See ::HT_EVENT_DATA_HW_HT_CRC.
 169
 170 // The Recovery HT component uses 0x10005000 for events.
 171 // For consistency, we avoid that range here.
 172
 173 #define HT_MAX_NC_BUIDS 32
 174 //----------------------------------------------------------------------------
 175 //                         HT TYPEDEFS, STRUCTURES, ENUMS
 176 //
 177 //----------------------------------------------------------------------------
 178
 179 /// Specify the state redundant links are to be left in after match.
 180 ///
 181 /// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
 182 /// or powered off.
 183
 184 typedef enum {
 185   MATCHED,                               ///< The link matches the requested customization.
 186                                          ///< When used with IGNORE_LINK,
 187                                          ///< this will generally require other software to initialize the link.
 188                                          ///< When used with SKIP_REGANG,
 189                                          ///< the two unganged links will be available for distribution.
 190
 191   POWERED_OFF,                           ///< Power the link off.  Support may vary based on processor model.
 192                                          ///< Power Off is only supported for coherent links.
 193                                          ///< Link power off may occur at a warm reset rather than immediately.
 194                                          ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
 195
 196   UNMATCHED,                             ///< The link should be processed according to normal defaults.
 197                                          ///< Effectively, the link does not match the requested customization.
 198                                          ///< This can be used to exclude links from a following match any.
 199
 200   MaxFinalLinkState                      ///< Not a final link state, use for limit checking.
 201 } FINAL_LINK_STATE;
 202
 203 /// Swap a device from its current id to a new one.
 204
 205 typedef struct {
 206   IN       UINT8 FromId;                 ///< The device responding to FromId,
 207   IN       UINT8 ToId;                   ///< will be moved to ToId.
 208 } BUID_SWAP_ITEM;
 209
 210
 211 /// Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
 212 /// the final in order list of device ids is provided. (There can be more swaps than devices.)
 213 /// The unused entries in both are filled with 0xFF.
 214
 215 typedef struct {
 216   IN       BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
 217   IN       UINT8 FinalIds[HT_MAX_NC_BUIDS];       ///< The ordered final BUIDs, resulting from the swaps
 218 } BUID_SWAP_LIST;
 219
 220
 221 /// Control Manual Initialization of Non-Coherent Chains
 222 ///
 223 /// This interface is checked every time a non-coherent chain is
 224 /// processed.  BUID assignment may be controlled explicitly on a
 225 /// non-coherent chain. Provide a swap list.  Swaps controls the
 226 /// BUID assignment and FinalIds provides the device to device
 227 /// Linking.  Device orientation can be detected automatically, or
 228 /// explicitly.  See interface documentation for more details.
 229 ///
 230 /// If a manual swap list is not supplied,
 231 /// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 232 /// based on each device's unit count.
 233
 234 typedef struct {
 235   // Match fields
 236   IN       UINT8 Socket;                       ///< The Socket on which this chain is located
 237   IN       UINT8 Link;                         ///< The Link on the host for this chain
 238   // Override fields
 239   IN       BUID_SWAP_LIST SwapList;            ///< The swap list
 240 } MANUAL_BUID_SWAP_LIST;
 241
 242
 243 /// Override options for DEVICE_CAP_OVERRIDE.
 244 ///
 245 /// Specify which override actions should be performed.  For Checks, 1 means to check the item
 246 /// and 0 means to skip the check.  For the override options, 1 means to apply the override and
 247 /// 0 means to ignore the override.
 248
 249 typedef struct {
 250   IN       UINT32  IsCheckDevVenId:1;     ///< Check Match on Device/Vendor id
 251   IN       UINT32  IsCheckRevision:1;     ///< Check Match on device Revision
 252   IN       UINT32  IsOverrideWidthIn:1;   ///< Override Width In
 253   IN       UINT32  IsOverrideWidthOut:1;  ///< Override Width Out
 254   IN       UINT32  IsOverrideFreq:1;      ///< Override Frequency
 255   IN       UINT32  IsOverrideClumping:1;  ///< Override Clumping
 256   IN       UINT32  IsDoCallout:1;         ///< Make the optional callout
 257 } DEVICE_CAP_OVERRIDE_OPTIONS;
 258
 259 /// Override capabilities of a device.
 260 ///
 261 /// This interface is checked once for every Link on every IO device.
 262 /// Provide the width and frequency capability if needed for this device.
 263 /// This is used along with device capabilities, the limit interfaces, and northbridge
 264 /// limits to compute the default settings.  The components of the device's PCI config
 265 /// address are provided, so its settings can be consulted if need be.
 266 /// The optional callout is a catch all.
 267
 268 typedef struct {
 269   // Match fields
 270   IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
 271   IN       UINT8 HostLink;             ///< The Link on the host for this chain.
 272   IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
 273   IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
 274   IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
 275   IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
 276   IN       DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
 277   // Override fields
 278   IN       UINT8 LinkWidthIn;          ///< modify to change the Link Width In.
 279   IN       UINT8 LinkWidthOut;         ///< modify to change the Link Width Out.
 280   IN       UINT32 FreqCap;             ///< modify to change the Link's frequency capability.
 281   IN       UINT32 Clumping;            ///< modify to change Unit ID clumping support.
 282   IN       CALLOUT_ENTRY Callout;      ///< optional call for really complex cases, or NULL.
 283 } DEVICE_CAP_OVERRIDE;
 284
 285 /// Callout param struct for override capabilities of a device.
 286 ///
 287 /// If the optional callout is implemented this param struct is passed to it.
 288
 289 typedef struct {
 290   IN       AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
 291   // Match fields
 292   IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
 293   IN       UINT8 HostLink;             ///< The Link on the host for this chain.
 294   IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
 295   IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
 296   IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
 297   IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
 298   IN       PCI_ADDR PciAddress;        ///< The Device's PCI Address.
 299   // Override fields
 300      OUT   UINT8 *LinkWidthIn;          ///< modify to change the Link Width In.
 301      OUT   UINT8 *LinkWidthOut;         ///< modify to change the Link Width Out.
 302      OUT   UINT32 *FreqCap;             ///< modify to change the Link's frequency capability.
 303      OUT   UINT32 *Clumping;            ///< modify to change Unit ID clumping support.
 304 } DEVICE_CAP_CALLOUT_PARAMS;
 305
 306 ///  Limits for CPU to CPU Links.
 307 ///
 308 ///  For each coherent connection this interface is checked once.
 309 ///  Provide the frequency and width if needed for this Link (usually based on board
 310 ///  restriction).  This is used with CPU device capabilities and northbridge limits
 311 ///  to compute the default settings.
 312
 313 typedef struct {
 314   // Match fields
 315   IN       UINT8 SocketA;                ///< One Socket on which this Link is located
 316   IN       UINT8 LinkA;                  ///< The Link on this Node
 317   IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
 318   IN       UINT8 LinkB;                  ///< The Link on that Node
 319   // Limit fields
 320   IN       UINT8 ABLinkWidthLimit;       ///< modify to change the Link Width A->B
 321   IN       UINT8 BALinkWidthLimit;       ///< modify to change the Link Width B-<A
 322   IN       UINT32 PcbFreqCap;            ///< modify to change the Link's frequency capability
 323 } CPU_TO_CPU_PCB_LIMITS;
 324
 325 ///  Get limits for non-coherent Links.
 326 ///
 327 /// For each non-coherent connection this interface is checked once.
 328 /// Provide the frequency and width if needed for this Link (usually based on board
 329 /// restriction).  This is used with device capabilities, device overrides, and northbridge limits
 330 /// to compute the default settings.
 331 ///
 332 typedef struct {
 333   // Match fields
 334   IN       UINT8 HostSocket;               ///< The Socket on which this Link is located
 335   IN       UINT8 HostLink;                 ///< The Link about to be initialized
 336   IN       UINT8 Depth;                    ///< The Depth in the I/O chain from the Host
 337   // Limit fields
 338   IN       UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
 339   IN       UINT8 UpstreamLinkWidthLimit;   ///< modify to change the Link Width moving toward processor
 340   IN       UINT32 PcbFreqCap;              ///< modify to change the Link's frequency capability
 341 } IO_PCB_LIMITS;
 342
 343 ///  Manually control bus number assignment.
 344 ///
 345 /// This interface is checked every time a non-coherent chain is processed.
 346 /// If a system can not use the auto Bus numbering feature for non-coherent chain bus
 347 /// assignments, this interface can provide explicit control.  For each chain, provide
 348 /// the bus number range to use.
 349
 350 typedef struct {
 351   // Match fields
 352   IN       UINT8 Socket;                 ///< The Socket on which this chain is located
 353   IN       UINT8 Link;                   ///< The Link on the host for this chain
 354   // Override fields
 355   IN       UINT8 SecBus;                 ///< Secondary Bus number for this non-coherent chain
 356   IN       UINT8 SubBus;                 ///< Subordinate Bus number
 357 } OVERRIDE_BUS_NUMBERS;
 358
 359
 360 ///  Ignore a Link.
 361 ///
 362 ///  This interface is checked every time a coherent Link is found and then every
 363 ///  time a non-coherent Link from a CPU is found.
 364 ///  Any coherent or non-coherent Link from a CPU can be ignored and not used
 365 ///  for discovery or initialization.  Useful for connection based systems.
 366 ///  (Note: not checked for IO device to IO Device Links.)
 367 ///  (Note: not usable for internal links (MCM processors).)
 368
 369 typedef struct {
 370   // Match fields
 371   IN       UINT8 Socket;                 ///< The Socket on which this Link is located
 372   IN       UINT8 Link;                   ///< The Link about to be initialized
 373   // Customization fields
 374   IN       FINAL_LINK_STATE LinkState;   ///< The link may be left unitialized, or powered off.
 375 } IGNORE_LINK;
 376
 377
 378 ///  Skip reganging of subLinks.
 379 ///
 380 ///  This interface is checked whenever two subLinks are both connected to the same CPUs.
 381 ///  Normally, unganged sublinks between the same two CPUs are reganged.
 382 ///  Provide a matching structure to leave the Links unganged.
 383
 384 typedef struct {
 385   // Match fields
 386   IN       UINT8 SocketA;                ///< One Socket on which this Link is located
 387   IN       UINT8 LinkA;                  ///< The Link on this Node
 388   IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
 389   IN       UINT8 LinkB;                  ///< The Link on that Node
 390   // Customization fields
 391   IN       FINAL_LINK_STATE LinkState;   ///< The paired sublink may be active, or powered off.
 392 } SKIP_REGANG;
 393
 394 ///  The System Socket layout, which sockets are physically connected.
 395 ///
 396 ///  The hardware method for Socket naming is preferred.  Use this software method only
 397 ///  if required.
 398
 399 typedef struct {
 400   IN       UINT8 CurrentSocket;    ///< The socket from which this connection originates.
 401   IN       UINT8 CurrentLink;      ///< The Link from the source socket connects to another socket.
 402   IN       UINT8 TargetSocket;     ///< The target socket which is connected on that link.
 403 } SYSTEM_PHYSICAL_SOCKET_MAP;
 404
 405 //----------------------------------------------------------------------------
 406 ///
 407 /// This is the input structure for AmdHtInitialize.
 408 ///
 409 typedef struct {
 410   // Basic level customization
 411   IN       UINT8 AutoBusStart;           ///< For automatic bus number assignment, starting bus number - usually zero.
 412                                          ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
 413   IN       UINT8 AutoBusMax;             ///< For automatic bus number assignment, do not assign above max.
 414                                          ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
 415   IN       UINT8 AutoBusIncrement;       ///< For automatic bus number assignment, each chain gets this many busses.
 416                                          ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUM}
 417
 418   // Advanced Level Customization
 419   IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;     ///< Provide Manual Swap List, if any.
 420                                                           ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
 421   IN       DEVICE_CAP_OVERRIDE *DeviceCapOverrideList;    ///< Provide Device Overrides, if any.
 422                                                           ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
 423   IN       CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList;   ///< Provide CPU PCB Limits, if any.
 424                                                           ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
 425                                                           ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
 426   IN       IO_PCB_LIMITS *IoPcbLimitsList;                ///< Provide IO PCB Limits, if any.
 427                                                           ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
 428                                                           ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
 429   IN       OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList;  ///< Provide manual Bus Number assignment, if any.
 430                                                           ///< Use either auto bus numbering or override bus
 431                                                           ///< numbers, not both.
 432                                                           ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
 433
 434   IN       IGNORE_LINK *IgnoreLinkList;                   ///< Provide links to ignore, if any.
 435                                                           ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
 436   IN       SKIP_REGANG *SkipRegangList;                   ///< Provide links to remain unganged, if any.
 437                                                           ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
 438                                                           ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
 439
 440   // Expert Level Customization
 441   IN       UINT8 **Topolist;                         ///< Use this topology list in addition to the built in, if not NULL.
 442                                                      ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
 443   IN       SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
 444                                                      ///< The hardware socket naming method is preferred,
 445                                                      ///<  If it can't be used, this provides a software method.
 446                                                      ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
 447 } AMD_HT_INTERFACE;
 448
 449 //-----------------------------------------------------------------------------
 450 //
 451 // HT Recovery Interface
 452 //
 453
 454
 455 /*-----------------------------------------------------------------------------
 456  *              HT Recovery DEFINITIONS AND MACROS
 457  *
 458  *-----------------------------------------------------------------------------
 459  */
 460
 461 // BBHT subfunction events
 462 #define HT_EVENT_BB_EVENTS         0x10005000
 463 #define HT_EVENT_BB_BUID_EXCEED    0x10015000
 464 #define HT_EVENT_BB_DEVICE_FAILED  0x10055000
 465 #define HT_EVENT_BB_AUTO_DEPTH     0x10065000
 466
 467 /*----------------------------------------------------------------------------
 468  *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
 469  *
 470  *----------------------------------------------------------------------------
 471  */
 472
 473
 474 /// The Interface structure to Recovery HT.
 475
 476 typedef struct {
 477   IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;  ///< Option to manually control SB link init
 478                                                        ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
 479      OUT   UINT32 Depth;           ///< If auto init was used this is set to the depth of the chain,
 480                                    ///< else, for manual init unmodified.
 481 } AMD_HT_RESET_INTERFACE;
 482
 483
 484 //-----------------------------------------------------------------------------
 485 //                     FCH DEFINITIONS AND MACROS
 486 //
 487 //-----------------------------------------------------------------------------
 488
 489 /// Configuration values for SdConfig
 490 typedef enum {
 491   SdDisable = 0,                      ///< Disabled
 492   SdAmda,                             ///< AMDA,  set 24,18,16,  default
 493   SdDma,                              ///< DMA clear 24, 16, set 18
 494   SdPio                               ///< PIO clear 24,18,16
 495 } SD_MODE;
 496
 497 /// Configuration values for SdClockControl
 498 typedef enum {
 499   Sd50MhzTraceCableLengthWithinSixInches = 4,           ///< 50Mhz, default
 500   Sd40MhzTraceCableLengthSix2ElevenInches = 6,          ///< 40Mhz
 501   Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7,   ///< 25Mhz
 502 } SD_CLOCK_CONTROL;
 503
 504 /// Configuration values for AzaliaController
 505 typedef enum {
 506   AzAuto = 0,                         ///< Auto - Detect Azalia controller automatically
 507   AzDisable,                          ///< Diable - Disable Azalia controller
 508   AzEnable                            ///< Enable - Enable Azalia controller
 509 } HDA_CONFIG;
 510
 511 /// Configuration values for IrConfig
 512 typedef enum {
 513   IrDisable  = 0,                     ///< Disable
 514   IrRxTx0    = 1,                     ///< Rx and Tx0
 515   IrRxTx1    = 2,                     ///< Rx and Tx1
 516   IrRxTx0Tx1 = 3                      ///< Rx and both Tx0,Tx1
 517 } IR_CONFIG;
 518
 519 /// Configuration values for SataClass
 520 typedef enum {
 521   SataNativeIde = 0,                  ///< Native IDE mode
 522   SataRaid,                           ///< RAID mode
 523   SataAhci,                           ///< AHCI mode
 524   SataLegacyIde,                      ///< Legacy IDE mode
 525   SataIde2Ahci,                       ///< IDE->AHCI mode
 526   SataAhci7804,                       ///< AHCI mode as 7804 ID (AMD driver)
 527   SataIde2Ahci7804                    ///< IDE->AHCI mode as 7804 ID (AMD driver)
 528 } SATA_CLASS;
 529
 530 /// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG
 531 typedef enum {
 532   PortA4       = 0,                   ///< 4:0:0:0
 533   PortA2B2     = 2,                   ///< 2:2:0:0
 534   PortA2B1C1   = 3,                   ///< 2:1:1:0
 535   PortA1B1C1D1 = 4                    ///< 1:1:1:1
 536 } GPP_LINKMODE;
 537
 538 /// Configuration values for FchPowerFail
 539 typedef enum {
 540   AlwaysOff   = 0,                    ///< Always power off after power resumes
 541   AlwaysOn    = 1,                    ///< Always power on after power resumes
 542   UsePrevious = 3,                    ///< Resume to same setting when power fails
 543 } POWER_FAIL;
 544
 545
 546 /// Configuration values for SATA Link Speed
 547 typedef enum {
 548   Gen1   = 1,                         ///< SATA port GEN1 speed
 549   Gen2   = 2,                         ///< SATA port GEN2 speed
 550   Gen3   = 3,                         ///< SATA port GEN3 speed
 551 } SATA_SPEED;
 552
 553
 554 /// Configuration values for GPIO function
 555 typedef enum {
 556   Function0   = 0,                    ///< GPIO Function 1
 557   Function1   = 1,                    ///< GPIO Function 1
 558   Function2   = 2,                    ///< GPIO Function 2
 559   Function3   = 3,                    ///< GPIO Function 3
 560 } GPIO_FUN;
 561
 562
 563 /// Configuration values for GPIO_CFG
 564 typedef enum {
 565   OwnedByEc   = 1 << 0,               ///< This bit can only be written by EC
 566   OwnedByHost = 1 << 1,               ///< This bit can only be written by host (BIOS)
 567   Sticky      = 1 << 2,               ///< If set, [6:3] are sticky
 568   PullUpB     = 1 << 3,               ///< 0: Pullup enable; 1: Pullup disabled
 569   PullDown    = 1 << 4,               ///< 0: Pulldown disabled; 1: Pulldown enable
 570   GpioOutEnB  = 1 << 5,               ///< 0: Output enable; 1: Output disable
 571   GpioOut     = 1 << 6,               ///< Output state when GpioOutEnB is 0
 572   GpioIn      = 1 << 7,               ///< This bit is read only - current pin state
 573 } CFG_BYTE;
 574
 575 /// FCH GPIO CONTROL
 576 typedef struct {
 577   IN         UINT8        GpioPin;               ///< Gpio Pin, valid range: 0-67, 128-150, 160-228
 578   IN         GPIO_FUN     PinFunction;           ///< Multi-function selection
 579   IN         CFG_BYTE     CfgByte;               ///< GPIO Register value
 580 } GPIO_CONTROL;
 581
 582 ///
 583 /// FCH SCI MAP CONTROL
 584 ///
 585 typedef struct {
 586   IN         UINT8        InputPin;              ///< Input Pin, valid range 0-63
 587   IN         UINT8        GpeMap;                ///< Gpe Map, valid range 0-31
 588 } SCI_MAP_CONTROL;
 589
 590 ///
 591 /// FCH SATA PHY CONTROL
 592 ///
 593 typedef struct {
 594   IN         BOOLEAN      CommonPhy;             ///< Common PHY or not
 595                                       ///<   @li <b>FALSE</b> - Only applied to specified port
 596                                       ///<   @li <b>TRUE</b>  - Apply to all SATA ports
 597   IN         SATA_SPEED   Gen;                   ///< SATA speed
 598   IN         UINT8        Port;                  ///< Port number, valid range: 0-7
 599   IN         UINT32       PhyData;               ///< SATA PHY data, valid range: 0-0xFFFFFFFF
 600 } SATA_PHY_CONTROL;
 601
 602 ///
 603 /// FCH Component Data Structure in InitReset stage
 604 ///
 605 typedef struct {
 606   IN       BOOLEAN      UmiGen2;             ///< Enable Gen2 data rate of UMI
 607                                              ///<   @li <b>FALSE</b> - Disable Gen2
 608                                              ///<   @li <b>TRUE</b>  - Enable Gen2
 609
 610   IN       BOOLEAN      SataEnable;          ///< SATA controller function
 611                                              ///<   @li <b>FALSE</b> - SATA controller is disabled
 612                                              ///<   @li <b>TRUE</b> - SATA controller is enabled
 613
 614   IN       BOOLEAN      IdeEnable;           ///< SATA IDE controller mode enabled/disabled
 615                                              ///<   @li <b>FALSE</b> - IDE controller is disabled
 616                                              ///<   @li <b>TRUE</b> - IDE controller is enabled
 617
 618   IN       BOOLEAN      GppEnable;           ///< Master switch of GPP function
 619                                              ///<   @li <b>FALSE</b> - GPP disabled
 620                                              ///<   @li <b>TRUE</b> - GPP enabled
 621
 622   IN       BOOLEAN      Xhci0Enable;         ///< XHCI0 controller function
 623                                              ///<   @li <b>FALSE</b> - XHCI0 controller disabled
 624                                              ///<   @li <b>TRUE</b> - XHCI0 controller enabled
 625
 626   IN       BOOLEAN      Xhci1Enable;         ///< XHCI1 controller function
 627                                              ///<   @li <b>FALSE</b> - XHCI1 controller disabled
 628                                              ///<   @li <b>TRUE</b> - XHCI1 controller enabled
 629 } FCH_RESET_INTERFACE;
 630
 631
 632 ///
 633 /// FCH Component Data Structure from InitEnv stage
 634 ///
 635 typedef struct {
 636   IN       SD_MODE      SdConfig;            ///< Secure Digital (SD) controller mode
 637   IN       HDA_CONFIG   AzaliaController;    ///< Azalia HD Audio Controller
 638
 639   IN       IR_CONFIG    IrConfig;            ///< Infrared (IR) Configuration
 640   IN       BOOLEAN      UmiGen2;             ///< Enable Gen2 data rate of UMI
 641                                              ///<   @li <b>FALSE</b> - Disable Gen2
 642                                              ///<   @li <b>TRUE</b>  - Enable Gen2
 643
 644   IN       SATA_CLASS   SataClass;           ///< SATA controller mode
 645   IN       BOOLEAN      SataEnable;          ///< SATA controller function
 646                                              ///<   @li <b>FALSE</b> - SATA controller is disabled
 647                                              ///<   @li <b>TRUE</b> - SATA controller is enabled
 648
 649   IN       BOOLEAN      IdeEnable;           ///< SATA IDE controller mode enabled/disabled
 650                                              ///<   @li <b>FALSE</b> - IDE controller is disabled
 651                                              ///<   @li <b>TRUE</b> - IDE controller is enabled
 652
 653   IN       BOOLEAN      SataIdeMode;         ///< Native mode of SATA IDE controller
 654                                              ///<   @li <b>FALSE</b> - Legacy IDE mode
 655                                              ///<   @li <b>TRUE</b> - Native IDE mode
 656
 657   IN       BOOLEAN      Ohci1Enable;         ///< OHCI controller #1 Function
 658                                              ///<   @li <b>FALSE</b> - OHCI1 is disabled
 659                                              ///<   @li <b>TRUE</b> - OHCI1 is enabled
 660
 661   IN       BOOLEAN      Ohci2Enable;         ///< OHCI controller #2 Function
 662                                              ///<   @li <b>FALSE</b> - OHCI2 is disabled
 663                                              ///<   @li <b>TRUE</b> - OHCI2 is enabled
 664
 665   IN       BOOLEAN      Ohci3Enable;         ///< OHCI controller #3 Function
 666                                              ///<   @li <b>FALSE</b> - OHCI3 is disabled
 667                                              ///<   @li <b>TRUE</b> - OHCI3 is enabled
 668
 669   IN       BOOLEAN      Ohci4Enable;         ///< OHCI controller #4 Function
 670                                              ///<   @li <b>FALSE</b> - OHCI4 is disabled
 671                                              ///<   @li <b>TRUE</b> - OHCI4 is enabled
 672
 673   IN       BOOLEAN      XhciSwitch;          ///< XHCI controller Function
 674                                              ///<   @li <b>FALSE</b> - XHCI is disabled
 675                                              ///<   @li <b>TRUE</b> - XHCI is enabled
 676
 677   IN       BOOLEAN      GppEnable;           ///< Master switch of GPP function
 678                                              ///<   @li <b>FALSE</b> - GPP disabled
 679                                              ///<   @li <b>TRUE</b> - GPP enabled
 680
 681   IN       POWER_FAIL   FchPowerFail;        ///< FCH power failure option
 682 } FCH_INTERFACE;
 683
 684
 685 /*----------------------------------------------------------------------------
 686  *   CPU Feature related info
 687  *----------------------------------------------------------------------------
 688  */
 689
 690 /// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
 691 typedef enum {
 692   C1eModeDisabled                   = 0,   ///< Disabled
 693   C1eModeAuto                       = 1,   ///< Auto mode enables the best C1e method for the
 694                                            ///< currently installed processor
 695   C1eModeHardware                   = 2,   ///< Hardware method
 696   C1eModeMsgBased                   = 3,   ///< Message-based method
 697   C1eModeSoftwareDeprecated         = 4,   ///< Deprecated software SMI method.
 698                                            ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for
 699                                            ///< example host BIOS SMM Handler implementation
 700   C1eModeHardwareSoftwareDeprecated = 5,   ///< Hardware or deprecated software SMI method
 701   MaxC1eMode                        = 6    ///< Not a valid value, used for verifying input
 702 } PLATFORM_C1E_MODES;
 703
 704 /// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
 705 typedef enum {
 706   CStateModeDisabled = 0,           ///< Disabled
 707   CStateModeC6       = 1,           ///< C6 State
 708   MaxCStateMode      = 2            ///< Not a valid value, used for verifying input
 709 } PLATFORM_CSTATE_MODES;
 710
 711 /// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
 712 typedef enum {
 713   CpbModeAuto     = 0,           ///< Auto
 714   CpbModeDisabled = 1,           ///< Disabled
 715   MaxCpbMode      = 2            ///< Not a valid value, used for verifying input
 716 } PLATFORM_CPB_MODES;
 717
 718 /// Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
 719 typedef enum {
 720   LOW_POWER_PSTATE_FOR_PROCHOT_AUTO      = 0,           ///< Auto
 721   LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE   = 1,           ///< Disabled
 722   MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE  = 2            ///< Not a valid value, used for verifying input
 723 } PLATFORM_LOW_POWER_PSTATE_MODES;
 724
 725 /*----------------------------------------------------------------------------
 726  *   GNB PCIe configuration info
 727  *----------------------------------------------------------------------------
 728  */
 729
 730 // Event definitions
 731
 732
 733 #define GNB_EVENT_INVALID_CONFIGURATION               0x20010000   // User configuration invalid
 734 #define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001   // Requested lane allocation for PCIe port can not be supported
 735 #define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION     0x20010002   // Requested incorrect PCIe port device address
 736 #define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION      0x20010003   // Incorrect parameter in DDI link configuration
 737 #define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION    0x20010004   // Invalid with for PCIe port or DDI link
 738 #define GNB_EVENT_INVALID_LANES_CONFIGURATION         0x20010005   // Lane double subscribe lanes
 739 #define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION  0x20010006   // Requested lane allocation for DDI link(s) can not be supported
 740 #define GNB_EVENT_LINK_TRAINING_FAIL                  0x20020000   // PCIe Link training fail
 741 #define GNB_EVENT_BROKEN_LANE_RECOVERY                0x20030000   // Broken lane workaround applied to recover link training
 742 #define GNB_EVENT_GEN2_SUPPORT_RECOVERY               0x20040000   // Scale back to GEN1 to recover link training
 743
 744
 745 #define DESCRIPTOR_TERMINATE_LIST           0x80000000ull
 746 #define DESCRIPTOR_IGNORE                   0x40000000ull
 747
 748 /// PCIe port misc extended controls
 749 typedef struct  {
 750   IN      UINT8                     LinkComplianceMode :1;  ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
 751   IN      UINT8                     LinkSafeMode       :2;  /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
 752                                                              *  @li @b 0 - port can advertize muximum supported capability
 753                                                              *  @li @b 1 - port limit advertized capability and speed to PCIe Gen1
 754                                                              */
 755   IN      UINT8                     SbLink             :1;  /**< PCIe link type
 756                                                              *  @li @b 0 - General purpose port
 757                                                              *  @li @b 1 - Port connected to SB
 758                                                              */
 759 } PCIe_PORT_MISC_CONTROL;
 760
 761
 762 /// PCIe port configuration data
 763 typedef struct  {
 764   IN       UINT8                   PortPresent;              ///< Enable PCIe port for initialization.
 765   IN       UINT8                   ChannelType;              /**< Channel type.
 766                                                                *  @li @b 0 - "lowLoss",
 767                                                                *  @li @b 1 - "highLoss",
 768                                                                *  @li @b 2 - "mob0db",
 769                                                                *  @li @b 3 - "mob3db",
 770                                                                *  @li @b 4 - "extnd6db"
 771                                                                *  @li @b 5 - "extnd8db"
 772                                                                */
 773   IN       UINT8                   DeviceNumber;             /**< PCI Device number for port.
 774                                                                *   @li @b 0 - Native port device number
 775                                                                *   @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12",  @ref F14ONLaneConfigurations "Family 0x14(ON)")
 776                                                                */
 777   IN       UINT8                   FunctionNumber;           ///< Reserved for future use
 778   IN       UINT8                   LinkSpeedCapability;      /**< PCIe link speed/
 779                                                                *  @li @b 0 - Maximum supported by silicon
 780                                                                *  @li @b 1 - Gen1
 781                                                                *  @li @b 2 - Gen2
 782                                                                *  @li @b 3 - Gen3
 783                                                                */
 784   IN       UINT8                   LinkAspm;                 /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
 785                                                                *  @li @b 0 - Disabled
 786                                                                *  @li @b 1 - L0s only
 787                                                                *  @li @b 2 - L1 only
 788                                                                *  @li @b 3 - L0s and L1
 789                                                                */
 790   IN       UINT8                   LinkHotplug;              /**< Hotplug control.
 791                                                                *  @li @b 0 - Disabled
 792                                                                *  @li @b 1 - Basic
 793                                                                *  @li @b 2 - Server
 794                                                                *  @li @b 3 - Enhanced
 795                                                                */
 796   IN       UINT8                   ResetId;                  /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
 797                                                                *   identification which control reset for given port.
 798                                                                *   Each port with unique GPIO should have unique ResetId assigned.
 799                                                                *   All ports use same GPIO to control reset should have same ResetId assigned.
 800                                                                *   see AgesaPcieSlotResetContol.
 801                                                                */
 802   IN       PCIe_PORT_MISC_CONTROL  MiscControls;             ///< Misc extended controls
 803 } PCIe_PORT_DATA;
 804
 805 /// DDI channel lane mapping
 806 typedef struct {                                          ///< Structure that discribe lane mapping
 807   IN      UINT8              Lane0   :2;                  /**< Lane 0 mapping
 808                                                            *  @li @b 0 - Map to lane 0
 809                                                            *  @li @b 1 - Map to lane 1
 810                                                            *  @li @b 2 - Map to lane 2
 811                                                            *  @li @b 2 - Map to lane 3
 812                                                            */
 813   IN      UINT8              Lane1   :2;                  ///< Lane 1 mapping (see "Lane 0 mapping")
 814   IN      UINT8              Lane2   :2;                  ///< Lane 2 mapping (see "Lane 0 mapping")
 815   IN      UINT8              Lane3   :2;                  ///< Lane 3 mapping (see "Lane 0 mapping")
 816 } CHANNEL_MAPPING;                                        ///< Lane mapping
 817
 818 /// Common Channel Mapping
 819 typedef union {
 820   IN      UINT8                ChannelMappingValue;       ///< Raw lane mapping
 821   IN      CHANNEL_MAPPING      ChannelMapping;            ///< Channel mapping
 822 } CONN_CHANNEL_MAPPING;
 823
 824 /// DDI Configuration data
 825 typedef struct  {
 826   IN       UINT8                ConnectorType;            /**< Display Connector Type
 827                                                             *  @li @b 0 - DP
 828                                                             *  @li @b 1 - eDP
 829                                                             *  @li @b 2 - Single Link DVI-D
 830                                                             *  @li @b 3 - Dual  Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description")
 831                                                             *  @li @b 4 - HDMI
 832                                                             *  @li @b 5 - Travis DP-to-VGA
 833                                                             *  @li @b 6 - Travis DP-to-LVDS
 834                                                             *  @li @b 7 - Hudson-2 NutMeg DP-to-VGA
 835                                                             *  @li @b 8 - Single Link DVI-I
 836                                                             *  @li @b 9 - Native CRT (Family 0x14)
 837                                                             *  @li @b 10 - Native LVDS (Family 0x14)
 838                                                             *  @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS
 839                                                             *              The auto detection method only support panel with EDID.
 840                                                             */
 841   IN       UINT8                AuxIndex;                 /**< Indicates which AUX or DDC Line is used
 842                                                             *  @li @b 0 - AUX1
 843                                                             *  @li @b 1 - AUX2
 844                                                             *  @li @b 2 - AUX3
 845                                                             *  @li @b 3 - AUX4
 846                                                             *  @li @b 4 - AUX5
 847                                                             *  @li @b 5 - AUX6
 848                                                             */
 849   IN       UINT8                HdpIndex;                 /**< Indicates which HDP pin is used
 850                                                             *  @li @b 0 - HDP1
 851                                                             *  @li @b 1 - HDP2
 852                                                             *  @li @b 2 - HDP3
 853                                                             *  @li @b 3 - HDP4
 854                                                             *  @li @b 4 - HDP5
 855                                                             *  @li @b 5 - HDP6
 856                                                             */
 857   IN       CONN_CHANNEL_MAPPING Mapping[2];               /**< Set specific mapping of lanes to connector pins
 858                                                             *  @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
 859                                                             *  @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
 860                                                             *  if Mapping[x] set to 0 than default mapping assumed
 861                                                             */
 862   IN       UINT8                LanePnInversionMask;      /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port.
 863                                                             *  @li 0 - Do not invert (default)
 864                                                             *  @li 1 - Invert P and N on this lane
 865                                                             */
 866 } PCIe_DDI_DATA;
 867
 868 /// Engine Configuration
 869 typedef struct {
 870   IN       UINT8                EngineType;               /**< Engine type
 871                                                            *  @li @b 0 -  Ignore engine configuration
 872                                                            *  @li @b 1 -  PCIe port
 873                                                            *  @li @b 2 -  DDI
 874                                                            */
 875   IN       UINT16               StartLane;                /**< Start Lane ID (in reversed configuration StartLane > EndLane)
 876                                                            * See lane description for @ref F12PcieLaneDescription "Family 0x12"
 877                                                            * @ref F14ONPcieLaneDescription "Family 0x14(ON)".
 878                                                            * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
 879                                                            * @ref F14ONLaneConfigurations "Family 0x14(ON)".
 880                                                            */
 881   IN       UINT16               EndLane;                  /**< End lane ID (in reversed configuration StartLane > EndLane)
 882                                                            * See lane description for @ref F12PcieLaneDescription "Family 0x12",
 883                                                            * @ref F14ONPcieLaneDescription "Family 0x14(ON)".
 884                                                            * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
 885                                                            * @ref F14ONLaneConfigurations "Family 0x14(ON)".
 886                                                            */
 887
 888 } PCIe_ENGINE_DATA;
 889
 890 /// PCIe port descriptor
 891 typedef struct {
 892   IN       UINT32               Flags;                    /**< Descriptor flags
 893                                                            * @li @b Bit31 - last descriptor in complex
 894                                                            */
 895   IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
 896   IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
 897 } PCIe_PORT_DESCRIPTOR;
 898
 899 /// DDI descriptor
 900 typedef struct {
 901   IN       UINT32               Flags;                    /**< Descriptor flags
 902                                                            * @li @b Bit31 - last descriptor in complex
 903                                                            */
 904   IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
 905   IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
 906 } PCIe_DDI_DESCRIPTOR;
 907
 908 /// PCIe Complex descriptor
 909 typedef struct {
 910   IN       UINT32               Flags;                    /**< Descriptor flags
 911                                                            * @li @b Bit31 - last descriptor in topology
 912                                                            */
 913   IN       UINT32               SocketId;                 ///< Socket Id
 914   IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
 915   IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
 916   IN       VOID                 *Reserved;                ///< Reserved for future use
 917 } PCIe_COMPLEX_DESCRIPTOR;
 918
 919 /// Action to control PCIe slot reset
 920 typedef enum {
 921   AssertSlotReset,                                        ///< Assert slot reset
 922   DeassertSlotReset                                       ///< Deassert slot reset
 923 } PCIE_RESET_CONTROL;
 924
 925 ///Slot Reset Info
 926 typedef struct {
 927   IN      AMD_CONFIG_PARAMS     StdHeader;                ///< Standard configuration header
 928   IN      UINT8                 ResetId;                  ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
 929   IN      UINT8                 ResetControl;             ///< Reset control as in PCIE_RESET_CONTROL
 930 } PCIe_SLOT_RESET_INFO;
 931
 932 /// Engine descriptor type
 933 typedef enum {
 934   PcieUnusedEngine = 0,                                   ///< Unused descriptor
 935   PciePortEngine = 1,                                     ///< PCIe port
 936   PcieDdiEngine = 2,                                      ///< DDI
 937   MaxPcieEngine                                           ///< Max engine type for boundary check.
 938 } PCIE_ENGINE_TYPE;
 939
 940 /// PCIe link capability/speed
 941 typedef enum  {
 942   PcieGenMaxSupported,                                    ///< Maximum supported
 943   PcieGen1 = 1,                                           ///< Gen1
 944   PcieGen2,                                               ///< Gen2
 945   MaxPcieGen                                              ///< Max Gen for boundary check
 946 } PCIE_LINK_SPEED_CAP;
 947
 948 /// PCIe PSPP Power policy
 949 typedef enum  {
 950   PsppDisabled,                                           ///< PSPP disabled
 951   PsppPerformance = 1,                                    ///< Performance
 952   PsppBalanceHigh,                                        ///< Balance-High
 953   PsppBalanceLow,                                         ///< Balance-Low
 954   PsppPowerSaving,                                        ///< Power Saving
 955   MaxPspp                                                 ///< Max Pspp for boundary check
 956 } PCIE_PSPP_POLICY;
 957
 958 /// DDI display connector type
 959 typedef enum {
 960   ConnectorTypeDP,                                        ///< DP
 961   ConnectorTypeEDP,                                       ///< eDP
 962   ConnectorTypeSingleLinkDVI,                             ///< Single Link DVI-D
 963   ConnectorTypeDualLinkDVI,                               ///< Dual  Link DVI-D
 964   ConnectorTypeHDMI,                                      ///< HDMI
 965   ConnectorTypeTravisDpToVga,                             ///< Travis DP-to-VGA
 966   ConnectorTypeTravisDpToLvds,                            ///< Travis DP-to-LVDS
 967   ConnectorTypeNutmegDpToVga,                             ///< Hudson-2 NutMeg DP-to-VGA
 968   ConnectorTypeSingleLinkDviI,                            ///< Single Link DVI-I
 969   ConnectorTypeCrt,                                       ///< CRT (VGA)
 970   ConnectorTypeLvds,                                      ///< LVDS
 971   ConnectorTypeAutoDetect,                                ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS)
 972   MaxConnectorType                                        ///< Not valid value, used to verify input
 973 } PCIE_CONNECTOR_TYPE;
 974
 975 /// PCIe link channel type
 976 typedef enum {
 977   ChannelTypeLowLoss,                                     ///< Low Loss
 978   ChannelTypeHighLoss,                                    ///< High Loss
 979   ChannelTypeMob0db,                                      ///< Mobile 0dB
 980   ChannelTypeMob3db,                                      ///< Mobile 3dB
 981   ChannelTypeExt6db,                                      ///< Extended 6dB
 982   ChannelTypeExt8db,                                      ///< Extended 8dB
 983   MaxChannelType                                          ///< Not valid value, used to verify input
 984 } PCIE_CHANNEL_TYPE;
 985
 986 /// PCIe link ASPM
 987 typedef enum {
 988   AspmDisabled,                                           ///< Disabled
 989   AspmL0s,                                                ///< PCIe L0s link state
 990   AspmL1,                                                 ///< PCIe L1 link state
 991   AspmL0sL1,                                              ///< PCIe L0s & L1 link state
 992   MaxAspm                                                 ///< Not valid value, used to verify input
 993 } PCIE_ASPM_TYPE;
 994
 995 /// PCIe link hotplug support
 996 typedef enum {
 997   HotplugDisabled,                                        ///< Hotplug disable
 998   HotplugBasic,                                           ///< Basic Hotplug
 999   HotplugServer,                                          ///< Server Hotplug
1000   HotplugEnhanced,                                        ///< Enhanced
1001   HotplugInboard,                                         ///< Inboard
1002   MaxHotplug                                              ///< Not valid value, used to verify input
1003 } PCIE_HOTPLUG_TYPE;
1004
1005 /// PCIe link initialization
1006 typedef enum {
1007   PortDisabled,                                           ///< Disable
1008   PortEnabled                                             ///< Enable
1009 } PCIE_PORT_ENABLE;
1010
1011 /// DDI Aux channel
1012 typedef enum {
1013   Aux1,                                                   ///< Aux1
1014   Aux2,                                                   ///< Aux2
1015   Aux3,                                                   ///< Aux3
1016   Aux4,                                                   ///< Aux4
1017   Aux5,                                                   ///< Aux5
1018   Aux6,                                                   ///< Aux6
1019   MaxAux                                                  ///< Not valid value, used to verify input
1020 } PCIE_AUX_TYPE;
1021
1022 /// DDI Hdp Index
1023 typedef enum {
1024   Hdp1,                                                   ///< Hdp1
1025   Hdp2,                                                   ///< Hdp2
1026   Hdp3,                                                   ///< Hdp3
1027   Hdp4,                                                   ///< Hdp4
1028   Hdp5,                                                   ///< Hdp5
1029   Hdp6,                                                   ///< Hdp6
1030   MaxHdp                                                  ///< Not valid value, used to verify input
1031 } PCIE_HDP_TYPE;
1032
1033 // Macro for statically initialization of various structures
1034 #define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
1035 #define  PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
1036 {mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} }
1037 #define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
1038 {mConnectorType, mAuxIndex, mHpdIndex, {0, 0}, 0}
1039 #define  PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \
1040 {mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion}
1041
1042 ///IOMMU requestor ID
1043 typedef struct {
1044   IN       UINT16     Bus       :8;                                ///< Bus
1045   IN       UINT16     Device    :5;                                ///< Device
1046   IN       UINT16     Function  :3;                                ///< Function
1047 } IOMMU_REQUESTOR_ID;
1048
1049 /// IVMD exclusion range descriptor
1050 typedef struct {
1051   IN       UINT32               Flags;                    /**< Descriptor flags
1052                                                            * @li @b Flags[31] - Terminate descriptor array.
1053                                                            * @li @b Flags[30] - Ignore descriptor.
1054                                                            */
1055   IN       IOMMU_REQUESTOR_ID   RequestorIdStart;         ///< Requestor ID start
1056   IN       IOMMU_REQUESTOR_ID   RequestorIdEnd;           ///< Requestor ID end (use same as start for single ID)
1057   IN       UINT64               RangeBaseAddress;         ///< Phisical base address of exclusion range
1058   IN       UINT64               RangeLength;              ///< Length of exclusion range in bytes
1059 } IOMMU_EXCLUSION_RANGE_DESCRIPTOR;
1060
1061 /*----------------------------------------------------------------------------
1062  *   GNB configuration info
1063  *----------------------------------------------------------------------------
1064  */
1065
1066 /// LVDS Misc Control Field
1067 typedef struct {
1068   IN  UINT8     FpdiMode:1;          ///< This item configures LVDS 888bit panel mode
1069                                      ///< @li FALSE = LVDS 888 panel in LDI mode
1070                                      ///< @li TRUE =  LVDS 888 panel in FPDI mode
1071                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
1072   IN  UINT8     DlChSwap:1;          ///< This item configures LVDS panel lower and upper link mapping
1073                                      ///< @li FALSE = Lower link and upper link not swap
1074                                      ///< @li TRUE = Lower link and upper link are swapped
1075                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
1076   IN  UINT8     VsyncActiveLow:1;    ///< This item configures polarity of frame pulse encoded in lvds data stream
1077                                      ///< @li FALSE = Active high Frame Pulse/Vsync
1078                                      ///< @li TRUE = Active low Frame Pulse/Vsync
1079                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW}
1080   IN  UINT8     HsyncActiveLow:1;    ///< This item configures polarity of line pulse encoded in lvds data
1081                                      ///< @li FALSE = Active high Line Pulse
1082                                      ///< @li TRUE = Active low Line Pulse / Hsync
1083                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW}
1084   IN  UINT8     BLONActiveLow:1;     ///< This item configures polarity of signal sent to digital BLON output pin
1085                                      ///< @li FALSE = Not inverted(active high)
1086                                      ///< @li TRUE = Inverted (active low)
1087                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
1088   IN  UINT8     Reserved:3;          ///< Reserved
1089 } LVDS_MISC_CONTROL_FIELD;
1090
1091 /// LVDS Misc Control
1092 typedef union _LVDS_MISC_CONTROL {
1093   IN LVDS_MISC_CONTROL_FIELD Field;  ///< LVDS_MISC_CONTROL_FIELD
1094   IN UINT8   Value;                  ///< LVDS Misc Control Value
1095 } LVDS_MISC_CONTROL;
1096
1097 /// Configuration settings for GNB.
1098 typedef struct {
1099   IN  UINT8     Gnb3dStereoPinIndex;      ///< 3D Stereo Pin ID.
1100                                           ///< @li 0 = Stereo 3D is disabled (default).
1101                                           ///< @li 1 = Use processor pin HPD1.
1102                                           ///< @li 2 = Use processor pin HPD2
1103                                           ///< @li 3 = Use processor pin HPD3
1104                                           ///< @li 4 = Use processor pin HPD4
1105                                           ///< @li 5 = Use processor pin HPD5
1106                                           ///< @li 6 = Use processor pin HPD6
1107                                           ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
1108   IN  BOOLEAN    IommuSupport;            ///< IOMMU support.
1109                                           ///< @li FALSE = Disabled. Disable and hide IOMMU device.
1110                                           ///< @li TRUE  = Initialize IOMMU subsystem. Generate ACPI IVRS table.
1111                                           ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT}
1112   IN  UINT16     LvdsSpreadSpectrum;      ///< Spread spectrum value in 0.01 %
1113                                           ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
1114   IN  UINT16     LvdsSpreadSpectrumRate;  ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
1115                                           ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
1116   IN  UINT8      LvdsPowerOnSeqDigonToDe;    ///< This item configures panel initialization timing.
1117                                              ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE}
1118   IN  UINT8      LvdsPowerOnSeqDeToVaryBl;   ///< This item configures panel initialization timing.
1119                                              ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL}
1120   IN  UINT8      LvdsPowerOnSeqDeToDigon;    ///< This item configures panel initialization timing.
1121                                              ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON}
1122   IN  UINT8      LvdsPowerOnSeqVaryBlToDe;   ///< This item configures panel initialization timing.
1123                                              ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE}
1124   IN  UINT8      LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing.
1125                                              ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY}
1126   IN  UINT8      LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing.
1127                                              ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON}
1128   IN  UINT8      LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing.
1129                                              ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL}
1130   IN  UINT16     LvdsMaxPixelClockFreq;      ///< This item configures the maximum pixel clock frequency supported.
1131                                              ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ}
1132   IN  UINT32     LcdBitDepthControlValue;    ///< This item configures the LCD bit depth control settings.
1133                                              ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE}
1134   IN  UINT8      Lvds24bbpPanelMode;         ///< This item configures the LVDS 24 BBP mode.
1135                                              ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE}
1136   IN  LVDS_MISC_CONTROL      LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
1137   IN  UINT16     PcieRefClkSpreadSpectrum;   ///< Spread spectrum value in 0.01 %
1138                                              ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
1139   IN  BOOLEAN    GnbRemoteDisplaySupport;    ///< This item enables Wireless Display Support
1140                                              ///< @li TRUE  = Enable Wireless Display Support
1141                                              ///< @li FALSE = Disable Wireless Display Support
1142                                              ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT}
1143 } GNB_ENV_CONFIGURATION;
1144
1145 /// GNB configuration info
1146 typedef struct {
1147   IN       PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
1148                                                         * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST
1149                                                         * Example of topology definition for single socket system:
1150                                                         * @code
1151                                                         *  PCIe_PORT_DESCRIPTOR PortList [] = {
1152                                                         *    // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
1153                                                         *    {
1154                                                         *      0,   //Descriptor flags
1155                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
1156                                                         *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
1157                                                         *    },
1158                                                         *    // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
1159                                                         *    {
1160                                                         *      0,   //Descriptor flags
1161                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
1162                                                         *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
1163                                                         *    },
1164                                                         *    // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
1165                                                         *    {
1166                                                         *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
1167                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
1168                                                         *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
1169                                                         *    }
1170                                                         *  };
1171                                                         *  PCIe_PORT_DESCRIPTOR DdiList [] = {
1172                                                         *    // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
1173                                                         *    {
1174                                                         *      0,   //Descriptor flags
1175                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
1176                                                         *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
1177                                                         *    },
1178                                                         *    // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
1179                                                         *    {
1180                                                         *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
1181                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
1182                                                         *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
1183                                                         *    }
1184                                                         *  };
1185                                                         * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
1186                                                         *   DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate complexes list
1187                                                         *   0,  //Socket ID
1188                                                         *   &PortList[0],
1189                                                         *   &DdiList[0],
1190                                                         * }
1191                                                         * @endcode
1192                                                         */
1193   IN       UINT8                    PsppPolicy;         /**< PSPP (PCIe Speed Power Policy)
1194                                                          *  @li @b 0 - Disabled
1195                                                          *  @li @b 1 - Performance
1196                                                          *  @li @b 2 - Balance-High
1197                                                          *  @li @b 3 - Balance-Low
1198                                                          *  @li @b 4 - Power Saving
1199                                                          */
1200
1201 } GNB_CONFIGURATION;
1202 //
1203 //  MEMORY-SPECIFIC DATA STRUCTURES
1204 //
1205 //
1206 //
1207 //
1208 // AGESA MAXIMIUM VALUES
1209 //
1210 //   These Max values are used to define array sizes and associated loop
1211 //   counts in the code.  They reflect the maximum values that AGESA
1212 //   currently supports and does not necessarily reflect the hardware
1213 //   capabilities of configuration.
1214 //
1215
1216 #define MAX_SOCKETS_SUPPORTED   8   ///< Max number of sockets in system
1217 #define MAX_CHANNELS_PER_SOCKET 4   ///< Max Channels per sockets
1218 #define MAX_DIMMS_PER_CHANNEL   4   ///< Max DIMMs on a memory channel (independent of platform)
1219 #define NUMBER_OF_DELAY_TABLES  9   ///< Number of tables defined in CH_DEF_STRUCT.
1220                                     ///< Eg: UINT16  *RcvEnDlys;
1221                                     ///<     UINT8   *WrDqsDlys;
1222                                     ///<     UINT8   *RdDqsDlys;
1223                                     ///<     UINT8   *WrDatDlys;
1224                                     ///<     UINT8   *RdDqsMinDlys;
1225                                     ///<     UINT8   *RdDqsMaxDlys;
1226                                     ///<     UINT8   *WrDatMinDlys;
1227                                     ///<     UINT8   *WrDatMaxDlys;
1228 #define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
1229
1230 #define MAX_PLATFORM_TYPES     16   ///< Platform types per system
1231
1232 #define MCT_TRNG_KEEPOUT_START  0x00004000    ///< base [39:8]
1233 #define MCT_TRNG_KEEPOUT_END    0x00007FFF    ///< base [39:8]
1234
1235 #define UMA_ATTRIBUTE_INTERLEAVE 0x80000000   ///< Uma Region is interleaved
1236 #define UMA_ATTRIBUTE_ON_DCT0    0x40000000   ///< UMA resides on memory that belongs to DCT0
1237 #define UMA_ATTRIBUTE_ON_DCT1    0x20000000   ///< UMA resides on memory that belongs to DCT1
1238
1239 typedef UINT8 PSO_TABLE;            ///< Platform Configuration Table
1240
1241 //        AGESA DEFINITIONS
1242 //
1243 //        Many of these are derived from the platform and hardware specific definitions
1244
1245 /// EccSymbolSize override value
1246 #define ECCSYMBOLSIZE_USE_BKDG      0   ///< Use BKDG Recommended Value
1247 #define ECCSYMBOLSIZE_FORCE_X4      4   ///< Force to x4
1248 #define ECCSYMBOLSIZE_FORCE_X8      8   ///< Force to x8
1249 /// CPU Package Type
1250 #define PT_L1       0                 ///< L1 Package type
1251 #define PT_M2       1                 ///< AM Package type
1252 #define PT_S1       2                 ///< S1 Package type
1253
1254 /// Structures use to pass system Logical CPU-ID
1255 typedef struct {
1256   IN OUT   UINT64 Family;             ///< Indicates logical ID Family
1257   IN OUT   UINT64 Revision;           ///< Indicates logical ID Family
1258 } CPU_LOGICAL_ID;
1259
1260 /// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
1261 typedef enum {
1262   AMD_PLATFORM_SERVER = 0x8000,     ///< Server
1263   AMD_PLATFORM_DESKTOP = 0x10000,   ///< Desktop
1264   AMD_PLATFORM_MOBILE = 0x20000,    ///< Mobile
1265 } AMD_PLATFORM_TYPE;
1266
1267 /// Dram technology type
1268 typedef enum {
1269   DDR2_TECHNOLOGY,      ///< DDR2 technology
1270   DDR3_TECHNOLOGY       ///< DDR3 technology
1271 } TECHNOLOGY_TYPE;
1272
1273 /// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
1274 typedef enum {
1275   DDR400_FREQUENCY = 200,     ///< DDR 400
1276   DDR533_FREQUENCY = 266,     ///< DDR 533
1277   DDR667_FREQUENCY = 333,     ///< DDR 667
1278   DDR800_FREQUENCY = 400,     ///< DDR 800
1279   DDR1066_FREQUENCY = 533,    ///< DDR 1066
1280   DDR1333_FREQUENCY = 667,    ///< DDR 1333
1281   DDR1600_FREQUENCY = 800,    ///< DDR 1600
1282   DDR1866_FREQUENCY = 933,    ///< DDR 1866
1283   DDR2100_FREQUENCY = 1050,   ///< DDR 2100
1284   DDR2133_FREQUENCY = 1066,   ///< DDR 2133
1285   DDR2400_FREQUENCY = 1200,   ///< DDR 2400
1286   UNSUPPORTED_DDR_FREQUENCY   ///< Highest limit of DDR frequency
1287 } MEMORY_BUS_SPEED;
1288
1289 /// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
1290 typedef enum {
1291   QUADRANK_REGISTERED,        ///< Quadrank registered DIMM
1292   QUADRANK_UNBUFFERED         ///< Quadrank unbuffered DIMM
1293 } QUANDRANK_TYPE;
1294
1295 /// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
1296 typedef enum {
1297   TIMING_MODE_AUTO,           ///< Use best rate possible
1298   TIMING_MODE_LIMITED,        ///< Set user top limit
1299   TIMING_MODE_SPECIFIC        ///< Set user specified speed
1300 } USER_MEMORY_TIMING_MODE;
1301
1302 /// Build Configuration values for BLDCFG_POWER_DOWN_MODE
1303 typedef enum {
1304   POWER_DOWN_BY_CHANNEL,      ///< Channel power down mode
1305   POWER_DOWN_BY_CHIP_SELECT,  ///< Chip select power down mode
1306   POWER_DOWN_MODE_AUTO        ///< AGESA to select power down mode
1307 } POWER_DOWN_MODE;
1308
1309 /// Low voltage support
1310 typedef enum {
1311   VOLT_INITIAL,              ///< Initial value for VDDIO
1312   VOLT1_5,                   ///< 1.5 Volt
1313   VOLT1_35,                  ///< 1.35 Volt
1314   VOLT1_25,                  ///< 1.25 Volt
1315   VOLT_UNSUPPORTED = 0xFF    ///< No common voltage found
1316 } DIMM_VOLTAGE;
1317
1318 /// UMA Mode
1319 typedef enum {
1320   UMA_NONE = 0,              ///< UMA None
1321   UMA_SPECIFIED = 1,         ///< UMA Specified
1322   UMA_AUTO = 2               ///< UMA Auto
1323 } UMA_MODE;
1324
1325 /// Force Training Mode
1326 typedef enum {
1327   FORCE_TRAIN_1D = 0,              ///< 1D Training only
1328   FORCE_TRAIN___ = 1,              ///<
1329   FORCE_TRAIN_AUTO = 2             ///<  Auto
1330 } FORCE_TRAIN_MODE;
1331
1332 ///  The possible DRAM prefetch mode settings.
1333 typedef enum  {
1334   DRAM_PREFETCHER_AUTO,                         ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
1335   DISABLE_DRAM_PREFETCH_FOR_IO,                 ///< Disable DRAM prefetching for I/O requests only.
1336   DISABLE_DRAM_PREFETCH_FOR_CPU,                ///< Disable DRAM prefetching for requests from processor cores only.
1337   DISABLE_DRAM_PREFETCHER,                      ///< Disable DRAM prefetching.
1338   MAX_DRAM_FREFETCH_MODE                        ///< Not a DRAM prefetch mode, use for limit checking.
1339 } DRAM_PREFETCH_MODE;
1340
1341 /// Build Configuration values for BLDCFG_UMA_ALIGNMENT
1342 typedef enum {
1343   NO_UMA_ALIGNED = 0x00FFFFFF,           ///< NO UMA aligned
1344   UMA_4MB_ALIGNED = 0x00FFFFC0,          ///< UMA 4MB aligned
1345   UMA_128MB_ALIGNED = 0x00FFF800,        ///< UMA 128MB aligned
1346   UMA_256MB_ALIGNED = 0x00FFF000,        ///< UMA 256MB aligned
1347   UMA_512MB_ALIGNED = 0x00FFE000,        ///< UMA 512MB aligned
1348 } UMA_ALIGNMENT;
1349
1350 ///
1351 ///   Global MCT Configuration Status Word (GStatus)
1352 ///
1353 typedef enum {
1354   GsbMTRRshort,              ///< Ran out of MTRRs while mapping memory
1355   GsbAllECCDimms,            ///< All banks of all Nodes are ECC capable
1356   GsbDramECCDis,             ///< Dram ECC requested but not enabled.
1357   GsbSoftHole,               ///< A Node Base gap was created
1358   GsbHWHole,                 ///< A HW dram remap was created
1359   GsbNodeIntlv,              ///< Node Memory interleaving was enabled
1360   GsbSpIntRemapHole,         ///< Special condition for Node Interleave and HW remapping
1361   GsbEnDIMMSpareNW,          ///< Indicates that DIMM Spare can be used without a warm reset
1362
1363   GsbEOL                     ///< End of list
1364 } GLOBAL_STATUS_FIELD;
1365
1366 ///
1367 ///   Local Error Status (DIE_STRUCT.ErrStatus[31:0])
1368 ///
1369 typedef enum {
1370   EsbNoDimms,                  ///< No DIMMs
1371   EsbSpdChkSum,                ///< SPD Checksum fail
1372   EsbDimmMismatchM,            ///< dimm module type(buffer) mismatch
1373   EsbDimmMismatchT,            ///< dimm CL/T mismatch
1374   EsbDimmMismatchO,            ///< dimm organization mismatch (128-bit)
1375   EsbNoTrcTrfc,                ///< SPD missing Trc or Trfc info
1376   EsbNoCycTime,                ///< SPD missing byte 23 or 25
1377   EsbBkIntDis,                 ///< Bank interleave requested but not enabled
1378   EsbDramECCDis,               ///< Dram ECC requested but not enabled
1379   EsbSpareDis,                 ///< Online spare requested but not enabled
1380   EsbMinimumMode,              ///< Running in Minimum Mode
1381   EsbNoRcvrEn,                 ///< No DQS Receiver Enable pass window found
1382   EsbSmallRcvr,                ///< DQS Rcvr En pass window too small (far right of dynamic range)
1383   EsbNoDqsPos,                 ///< No DQS-DQ passing positions
1384   EsbSmallDqs,                 ///< DQS-DQ passing window too small
1385   EsbDCBKScrubDis,             ///< DCache scrub requested but not enabled
1386
1387   EsbEMPNotSupported,          ///< Processor is not capable for EMP.
1388   EsbEMPConflict,               ///< EMP requested but cannot be enabled since
1389                                ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
1390   EsbEMPDis,                   ///< EMP requested but cannot be enabled since
1391                                ///< memory size of each DCT is not a power of two.
1392
1393   EsbEOL                       ///< End of list
1394 } ERROR_STATUS_FIELD;
1395
1396 ///
1397 ///  Local Configuration Status (DIE_STRUCT.Status[31:0])
1398 ///
1399 typedef enum {
1400   SbRegistered,                ///< All DIMMs are Registered
1401   SbEccDimms,                  ///< All banks ECC capable
1402   SbParDimms,                  ///< All banks Addr/CMD Parity capable
1403   SbDiagClks,                  ///< Jedec ALL slots clock enable diag mode
1404   Sb128bitmode,                ///< DCT in 128-bit mode operation
1405   Sb64MuxedMode,               ///< DCT in 64-bit mux'ed mode.
1406   Sb2TMode,                    ///< 2T CMD timing mode is enabled.
1407   SbSWNodeHole,                ///< Remapping of Node Base on this Node to create a gap.
1408   SbHWHole,                    ///< Memory Hole created on this Node using HW remapping.
1409   SbOver400Mhz,                ///< DCT freq greater than or equal to 400MHz flag
1410   SbDQSPosPass2,               ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
1411   SbDQSRcvLimit,               ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
1412   SbExtConfig,                 ///< Indicate the default setting for extended PCI configuration support
1413   SbLrdimms,                   ///< All DIMMs are LRDIMMs
1414
1415   SbEOL                        ///< End of list
1416 } LOCAL_STATUS_FIELD;
1417
1418
1419 ///< CPU MSR Register definitions ------------------------------------------
1420 #define SYS_CFG     0xC0010010
1421 //#define TOP_MEM     0xC001001A
1422 //#define TOP_MEM2    0xC001001D
1423 #ifndef TOP_MEM
1424   #define TOP_MEM                       0xC001001A
1425 #endif
1426 #ifndef TOP_MEM2
1427   #define TOP_MEM2                      0xC001001D
1428 #endif
1429 #define HWCR        0xC0010015
1430 #define NB_CFG      0xC001001F
1431
1432 #define FS_BASE     0xC0000100
1433 #define IORR0_BASE  0xC0010016
1434 #define IORR0_MASK  0xC0010017
1435 #define BU_CFG      0xC0011023
1436 #define BU_CFG2     0xC001102A
1437 #define COFVID_STAT 0xC0010071
1438 #define TSC         0x10
1439
1440 //-----------------------------------------------------------------------------
1441 ///
1442 /// SPD Data for each DIMM.
1443 ///
1444 typedef struct _SPD_DEF_STRUCT {
1445   IN BOOLEAN DimmPresent;       ///< Indicates that the DIMM is present and Data is valid
1446   IN UINT8 Data[256];           ///< Buffer for 256 Bytes of SPD data from DIMM
1447 } SPD_DEF_STRUCT;
1448
1449 ///
1450 /// Channel Definition Structure.
1451 /// This data structure defines entries that are specific to the channel initialization
1452 ///
1453 typedef struct _CH_DEF_STRUCT {
1454   OUT UINT8   ChannelID;         ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
1455   OUT TECHNOLOGY_TYPE TechType;  ///< Technology type of this channel
1456   OUT UINT8   ChDimmPresent;     ///< For each bit n 0..7, 1 = DIMM n is present.
1457                                  ///<  DIMM#  Select Signal
1458                                  ///<  0      MA0_CS_L[0, 1]
1459                                  ///<  1      MB0_CS_L[0, 1]
1460                                  ///<  2      MA1_CS_L[0, 1]
1461                                  ///<  3      MB1_CS_L[0, 1]
1462                                  ///<  4      MA2_CS_L[0, 1]
1463                                  ///<  5      MB2_CS_L[0, 1]
1464                                  ///<  6      MA3_CS_L[0, 1]
1465                                  ///<  7      MB3_CS_L[0, 1]
1466
1467   OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
1468   OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
1469   OUT SPD_DEF_STRUCT *SpdPtr;    ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
1470   OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
1471                                  ///<   SPD Data for each Dimm. (Setup by Tech Block Constructor)
1472   OUT UINT8   ChDimmValid;       ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
1473                                  ///<
1474   OUT UINT8   RegDimmPresent;    ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
1475   OUT UINT8   LrDimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
1476   OUT UINT8   SODimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
1477   OUT UINT8   Loads;             ///< Number of devices loading bus
1478   OUT UINT8   Dimms;             ///< Number of DIMMs loading Channel
1479   OUT UINT8   Ranks;             ///< Number of ranks loading Channel DATA
1480   OUT BOOLEAN SlowMode;          ///< 1T or 2T CMD mode (slow access mode)
1481                                  ///< FALSE = 1T
1482                                  ///< TRUE = 2T
1483   ///< The following pointers will be pointed to dynamically allocated buffers.
1484   ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
1485   ///< Example: If DIMM and Byte based training, then
1486   ///< XX is a value in Hex
1487   ///<                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
1488   ///<  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
1489   ///<  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
1490   OUT UINT16  *RcvEnDlys;       ///< DQS Receiver Enable Delays
1491   OUT UINT8   *WrDqsDlys;       ///< Write DQS delays (only valid for DDR3)
1492   OUT UINT8   *RdDqsDlys;       ///< Read Dqs delays
1493   OUT UINT8   *WrDatDlys;       ///< Write Data delays
1494   OUT UINT8   *RdDqs__Dlys;     ///< Read DQS data
1495   OUT UINT8   *RdDqsMinDlys;    ///< Minimum Window for Read DQS
1496   OUT UINT8   *RdDqsMaxDlys;    ///< Maximum Window for Read DQS
1497   OUT UINT8   *WrDatMinDlys;    ///< Minimum Window for Write data
1498   OUT UINT8   *WrDatMaxDlys;    ///< Maximum Window for Write data
1499   OUT UINT16  *RcvEnDlysMemPs1;       ///< DQS Receiver Enable Delays for Mem Pstate 1
1500   OUT UINT8   *WrDqsDlysMemPs1;       ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1
1501   OUT UINT8   *RdDqsDlysMemPs1;       ///< Read Dqs delays for Memory Pstate 1
1502   OUT UINT8   *WrDatDlysMemPs1;       ///< Write Data delays for Memory Pstate 1
1503   OUT UINT8   *RdDqs__DlysMemPs1;     ///< Read DQS data for Memory Pstate 1
1504   OUT UINT8   *RdDqsMinDlysMemPs1;    ///< Minimum Window for Read DQS for Memory Pstate 1
1505   OUT UINT8   *RdDqsMaxDlysMemPs1;    ///< Maximum Window for Read DQS for Memory Pstate 1
1506   OUT UINT8   *WrDatMinDlysMemPs1;    ///< Minimum Window for Write data for Memory Pstate 1
1507   OUT UINT8   *WrDatMaxDlysMemPs1;    ///< Maximum Window for Write data for Memory Pstate 1
1508   OUT UINT8   RowCount;         ///< Number of rows of the allocated buffer.
1509   OUT UINT8   ColumnCount;      ///< Number of columns of the allocated buffer.
1510   OUT UINT8   *FailingBitMask;    ///< Table of masks to Track Failing bits
1511   OUT UINT8   *FailingBitMaskMemPs1;    ///< Table of masks to Track Failing bits for Memory Pstate 1
1512   OUT UINT32  DctOdcCtl;          ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
1513   OUT UINT32  DctAddrTmg;         ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
1514   OUT UINT32  PhyRODTCSLow;       ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
1515   OUT UINT32  PhyRODTCSHigh;      ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
1516   OUT UINT32  PhyWODTCSLow;       ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
1517   OUT UINT32  PhyWODTCSHigh;      ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
1518   OUT UINT8   PhyWLODT[4];        ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
1519   OUT UINT16  DctEccDqsLike;      ///< DCT DQS ECC UINT8 like...
1520   OUT UINT8   DctEccDqsScale;     ///< DCT DQS ECC UINT8 scale
1521   OUT UINT16  PtrPatternBufA;     ///< Ptr on stack to aligned DQS testing pattern
1522   OUT UINT16  PtrPatternBufB;     ///< Ptr on stack to aligned DQS testing pattern
1523   OUT UINT8   ByteLane;           ///< Current UINT8 Lane (0..7)
1524   OUT UINT8   Direction;          ///< Current DQS-DQ training write direction (0=read, 1=write)
1525   OUT UINT8   Pattern;            ///< Current pattern
1526   OUT UINT8   DqsDelay;           ///< Current DQS delay value
1527   OUT UINT16  HostBiosSrvc1;      ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
1528   OUT UINT32  HostBiosSrvc2;      ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
1529   OUT UINT16  DctMaxRdLat[4];     ///< Max Read Latency (ns) for the DCT
1530                                   ///< DctMaxRdLat [i] is for NBPstate i
1531   OUT UINT8   DIMMValidCh;        ///< DIMM# in CH
1532   OUT UINT8   MaxCh;              ///< Max number of CH in system
1533   OUT UINT8   Dct;                ///< Dct pointer
1534   OUT UINT8   WrDatGrossH;        ///< Write Data Gross delay high value
1535   OUT UINT8   DqsRcvEnGrossL;     ///< DQS Receive Enable Gross Delay low
1536
1537   OUT UINT8   TrwtWB;             ///<  Non-SPD timing value for TrwtWB
1538   OUT UINT8   CurrRcvrDctADelay;  ///< for keep current RcvrEnDly
1539   OUT UINT16  T1000;              ///< get the T1000 figure (cycle time (ns) * 1K)
1540   OUT UINT8   DqsRcvEnPass;       ///< for TrainRcvrEn UINT8 lane pass flag
1541   OUT UINT8   DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
1542   OUT UINT8   SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
1543
1544   OUT UINT8   ClToNbFlag;         ///< is used to restore ClLinesToNbDis bit after memory
1545   OUT UINT32  NodeSysBase;        ///< for channel interleave usage
1546   OUT UINT8   RefRawCard[MAX_DIMMS_PER_CHANNEL];   ///< Array of rawcards detected
1547   OUT UINT8   CtrlWrd02[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 2 values per DIMM
1548   OUT UINT8   CtrlWrd03[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 3 values per DIMM
1549   OUT UINT8   CtrlWrd04[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 4 values per DIMM
1550   OUT UINT8   CtrlWrd05[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 5 values per DIMM
1551   OUT UINT8   CtrlWrd08[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 8 values per DIMM
1552
1553   OUT UINT16  CsPresentDCT;       ///< For each bit n 0..7, 1 = Chip-select n is present
1554   OUT UINT8   DimmMirrorPresent;  ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
1555   OUT UINT8   DimmSpdCse;         ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
1556   OUT UINT8   DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
1557   OUT UINT8   DimmYr06;           ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
1558   OUT UINT8   DimmWk2406;         ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
1559   OUT UINT8   DimmPlPresent;      ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
1560   OUT UINT8   DimmQrPresent;      ///< QuadRank DIMM present?
1561   OUT UINT8   DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present
1562   OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present
1563   OUT UINT8   Dimmx4Present;      ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
1564   OUT UINT8   Dimmx8Present;      ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
1565   OUT UINT8   Dimmx16Present;     ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
1566   OUT UINT8   LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
1567   OUT UINT8   LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
1568   OUT UINT8   LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
1569   OUT UINT8   DimmNibbleAccess;   ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
1570   OUT UINT8   *MemClkDisMap;      ///<  This pointer will be set to point to an array that describes
1571                                   ///<  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
1572                                   ///<  base on this array to disable unused MemClk to save power.
1573                                   ///<
1574                                   ///<  The array must have 8 entries. Each entry, which associates with
1575                                   ///<  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
1576                                   ///<    Example:
1577                                   ///<    BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
1578                                   ///<    is like below:
1579                                   ///<         Bit AM3/S1g3 pin name
1580                                   ///<         0   M[B,A]_CLK_H/L[0]
1581                                   ///<         1   M[B,A]_CLK_H/L[1]
1582                                   ///<         2   M[B,A]_CLK_H/L[2]
1583                                   ///<         3   M[B,A]_CLK_H/L[3]
1584                                   ///<         4   M[B,A]_CLK_H/L[4]
1585                                   ///<         5   M[B,A]_CLK_H/L[5]
1586                                   ///<         6   M[B,A]_CLK_H/L[6]
1587                                   ///<         7   M[B,A]_CLK_H/L[7]
1588                                   ///<    And platform has the following routing:
1589                                   ///<         CS0   M[B,A]_CLK_H/L[4]
1590                                   ///<         CS1   M[B,A]_CLK_H/L[2]
1591                                   ///<         CS2   M[B,A]_CLK_H/L[3]
1592                                   ///<         CS3   M[B,A]_CLK_H/L[5]
1593                                   ///<    Then MemClkDisMap should be pointed to the following array:
1594                                   ///<               CLK_2 CLK_3 CLK_4 CLK_5
1595                                   ///<    0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
1596                                   ///<  Each entry of the array is the bitmask of 8 chip selects.
1597
1598   OUT UINT8   *CKETriMap;         ///<  This pointer will be set to point to an array that describes
1599                                   ///<  the routing of CKE pins to the DIMMs' ranks.
1600                                   ///<  The array must have 2 entries. Each entry, which associates with
1601                                   ///<  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
1602                                   ///<  AGESA will base on this array to disable unused CKE pins to save power.
1603
1604   OUT UINT8   *ODTTriMap;         ///<  This pointer will be set to point to an array that describes
1605                                   ///<  the routing of ODT pins to the DIMMs' ranks.
1606                                   ///<  The array must have 4 entries. Each entry, which associates with
1607                                   ///<  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
1608                                   ///<  AGESA will base on this array to disable unused ODT pins to save power.
1609
1610   OUT UINT8   *ChipSelTriMap;     ///<  This pointer will be set to point to an array that describes
1611                                   ///<  the routing of chip select pins to the DIMMs' ranks.
1612                                   ///<  The array must have 8 entries. Each entry is a bitmap of 8 CS.
1613                                   ///<  AGESA will base on this array to disable unused Chip select pins to save power.
1614
1615   OUT BOOLEAN   ExtendTmp;        ///<  If extended temperature is supported on all dimms on a channel.
1616
1617   OUT UINT8   MaxVref;            ///<  Maximum Vref Value for channel
1618
1619   OUT UINT8   Reserved[100];      ///< Reserved
1620 } CH_DEF_STRUCT;
1621
1622 ///
1623 /// DCT Channel Timing Parameters.
1624 /// This data structure sets timings that are specific to the channel.
1625 ///
1626 typedef struct _CH_TIMING_STRUCT {
1627   OUT UINT16  DctDimmValid;       ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
1628   OUT UINT16  DimmMirrorPresent;  ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
1629   OUT UINT16  DimmSpdCse;         ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
1630   OUT UINT16  DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
1631   OUT UINT16  CsPresent;          ///< For each bit n 0..7, 1=Chip-select n is present
1632   OUT UINT16  CsEnabled;          ///< For each bit n 0..7, 1=Chip-select n is enabled
1633   OUT UINT16  CsTestFail;         ///< For each bit n 0..7, 1=Chip-select n is present but disabled
1634   OUT UINT16  CsTrainFail;        ///< Bitmap showing which chipselects failed training
1635   OUT UINT16  DIMM1KPage;         ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
1636   OUT UINT16  DimmQrPresent;      ///< QuadRank DIMM present?
1637   OUT UINT16  DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
1638   OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
1639   OUT UINT16  Dimmx4Present;      ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
1640   OUT UINT16  Dimmx8Present;      ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
1641   OUT UINT16  Dimmx16Present;     ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
1642
1643   OUT UINT16  DIMMTrcd;           ///< Minimax Trcd*40 (ns) of DIMMs
1644   OUT UINT16  DIMMTrp;            ///< Minimax Trp*40 (ns) of DIMMs
1645   OUT UINT16  DIMMTrtp;           ///< Minimax Trtp*40 (ns) of DIMMs
1646   OUT UINT16  DIMMTras;           ///< Minimax Tras*40 (ns) of DIMMs
1647   OUT UINT16  DIMMTrc;            ///< Minimax Trc*40 (ns) of DIMMs
1648   OUT UINT16  DIMMTwr;            ///< Minimax Twr*40 (ns) of DIMMs
1649   OUT UINT16  DIMMTrrd;           ///< Minimax Trrd*40 (ns) of DIMMs
1650   OUT UINT16  DIMMTwtr;           ///< Minimax Twtr*40 (ns) of DIMMs
1651   OUT UINT16  DIMMTfaw;           ///< Minimax Tfaw*40 (ns) of DIMMs
1652   OUT UINT16  TargetSpeed;        ///< Target DRAM bus speed in MHz
1653   OUT UINT16  Speed;              ///< DRAM bus speed in MHz
1654                                   ///<  400 (MHz)
1655                                   ///<  533 (MHz)
1656                                   ///<  667 (MHz)
1657                                   ///<  800 (MHz)
1658                                   ///<  and so on...
1659   OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
1660   OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
1661   OUT UINT8   Trp;                ///< DCT Trp (busclocks)
1662   OUT UINT8   Trtp;               ///< DCT Trtp (busclocks)
1663   OUT UINT8   Tras;               ///< DCT Tras (busclocks)
1664   OUT UINT8   Trc;                ///< DCT Trc (busclocks)
1665   OUT UINT8   Twr;                ///< DCT Twr (busclocks)
1666   OUT UINT8   Trrd;               ///< DCT Trrd (busclocks)
1667   OUT UINT8   Twtr;               ///< DCT Twtr (busclocks)
1668   OUT UINT8   Tfaw;               ///< DCT Tfaw (busclocks)
1669   OUT UINT8   Trfc0;              ///< DCT Logical DIMM0 Trfc
1670                                   ///<  0 = 75ns (for 256Mb devs)
1671                                   ///<  1 = 105ns (for 512Mb devs)
1672                                   ///<  2 = 127.5ns (for 1Gb devs)
1673                                   ///<  3 = 195ns (for 2Gb devs)
1674                                   ///<  4 = 327.5ns (for 4Gb devs)
1675   OUT UINT8   Trfc1;              ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
1676   OUT UINT8   Trfc2;              ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
1677   OUT UINT8   Trfc3;              ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
1678   OUT UINT32  DctMemSize;         ///< Base[47:16], total DRAM size controlled by this DCT.
1679                                   ///<
1680   OUT BOOLEAN SlowMode;           ///< 1T or 2T CMD mode (slow access mode)
1681                                   ///< FALSE = 1T
1682                                   ///< TRUE = 2T
1683   OUT UINT8   TrwtTO;             ///< DCT TrwtTO (busclocks)
1684   OUT UINT8   Twrrd;              ///< DCT Twrrd (busclocks)
1685   OUT UINT8   Twrwr;              ///< DCT Twrwr (busclocks)
1686   OUT UINT8   Trdrd;              ///< DCT Trdrd (busclocks)
1687   OUT UINT8   TrwtWB;             ///< DCT TrwtWB (busclocks)
1688   OUT UINT8   TrdrdSD;            ///< DCT TrdrdSD (busclocks)
1689   OUT UINT8   TwrwrSD;            ///< DCT TwrwrSD (busclocks)
1690   OUT UINT8   TwrrdSD;            ///< DCT TwrrdSD (busclocks)
1691   OUT UINT16  MaxRdLat;           ///< Max Read Latency
1692   OUT UINT8   WrDatGrossH;        ///< Temporary variables must be removed
1693   OUT UINT8   DqsRcvEnGrossL;     ///< Temporary variables must be removed
1694 } CH_TIMING_STRUCT;
1695
1696 ///
1697 /// Data for each DCT.
1698 /// This data structure defines data used to configure each DRAM controller.
1699 ///
1700 typedef struct _DCT_STRUCT {
1701   OUT UINT8   Dct;                ///< Current Dct
1702   OUT CH_TIMING_STRUCT Timings;   ///< Channel Timing structure
1703   OUT CH_TIMING_STRUCT *TimingsMemPs1;   ///< Pointed to channel timing structure for memory Pstate 1
1704   OUT CH_DEF_STRUCT    *ChData;   ///< Pointed to a dynamically allocated array of Channel structures
1705   OUT UINT8   ChannelCount;       ///< Number of channel per this DCT
1706   OUT BOOLEAN BkIntDis;           ///< Bank interleave requested but not enabled on current DCT
1707 } DCT_STRUCT;
1708
1709
1710 ///
1711 /// Data Structure defining each Die.
1712 /// This data structure contains information that is used to configure each Die.
1713 ///
1714 typedef struct _DIE_STRUCT {
1715
1716   /// Advanced:
1717
1718   OUT UINT8   NodeId;              ///< Node ID of current controller
1719   OUT UINT8   SocketId;            ///< Socket ID of this Die
1720   OUT UINT8   DieId;               ///< ID of this die relative to the socket
1721   OUT PCI_ADDR      PciAddr;       ///< Pci bus and device number of this controller.
1722   OUT AGESA_STATUS  ErrCode;       ///< Current error condition of Node
1723                                    ///<  0x0 = AGESA_SUCCESS
1724                                    ///<  0x1 = AGESA_UNSUPPORTED
1725                                    ///<  0x2 = AGESA_BOUNDS_CHK
1726                                    ///<  0x3 = AGESA_ALERT
1727                                    ///<  0x4 = AGESA_WARNING
1728                                    ///<  0x5 = AGESA_ERROR
1729                                    ///<  0x6 = AGESA_CRITICAL
1730                                    ///<  0x7 = AGESA_FATAL
1731                                    ///<
1732   OUT BOOLEAN ErrStatus[EsbEOL];   ///< Error Status bit Field
1733                                    ///<
1734   OUT BOOLEAN Status[SbEOL];       ///< Status bit Field
1735                                    ///<
1736   OUT UINT32  NodeMemSize;         ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
1737                                    ///<
1738   OUT UINT32  NodeSysBase;         ///< Base[47:16] (system address) DRAM base address of this Node.
1739                                    ///<
1740   OUT UINT32  NodeHoleBase;        ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
1741                                    ///<
1742   OUT UINT32  NodeSysLimit;        ///< Base[47:16] (system address) DRAM limit address of this Node.
1743                                    ///<
1744   OUT UINT32  DimmPresent;         ///< For each bit n 0..7, 1 = DIMM n is present.
1745                                    ///<   DIMM#  Select Signal
1746                                    ///<   0      MA0_CS_L[0, 1]
1747                                    ///<   1      MB0_CS_L[0, 1]
1748                                    ///<   2      MA1_CS_L[0, 1]
1749                                    ///<   3      MB1_CS_L[0, 1]
1750                                    ///<   4      MA2_CS_L[0, 1]
1751                                    ///<   5      MB2_CS_L[0, 1]
1752                                    ///<   6      MA3_CS_L[0, 1]
1753                                    ///<   7      MB3_CS_L[0, 1]
1754                                    ///<
1755   OUT UINT32  DimmValid;           ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
1756   OUT UINT32  RegDimmPresent;      ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
1757   OUT UINT32  LrDimmPresent;       ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
1758   OUT UINT32  DimmEccPresent;      ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
1759   OUT UINT32  DimmParPresent;      ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
1760                                    ///<
1761   OUT UINT16  DimmTrainFail;       ///< Bitmap showing which dimms failed training
1762   OUT UINT16  ChannelTrainFail;    ///< Bitmap showing the channel information about failed Chip Selects
1763                                    ///<  0 in any bit field indicates Channel 0
1764                                    ///<  1 in any bit field indicates Channel 1
1765   OUT UINT8   Dct;                 ///<  Need to be removed
1766                                    ///<  DCT pointer
1767   OUT BOOLEAN GangedMode;          ///< Ganged mode
1768                                    ///<  0 = disabled
1769                                    ///<  1 = enabled
1770   OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
1771                                    ///<
1772   OUT UINT16  HostBiosSrvc1;       ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
1773                                    ///<
1774   OUT UINT32  HostBiosSrvc2;       ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
1775                                    ///<
1776   OUT UINT8   MLoad;               ///< Need to be removed
1777                                    ///< Number of devices loading MAA bus
1778                                    ///<
1779   OUT UINT8   MaxAsyncLat;         ///< Legacy wrapper
1780                                    ///<
1781   OUT UINT8   ChbD3Rcvrdly;        ///< Legacy wrapper
1782                                    ///<
1783   OUT UINT16  ChaMaxRdLat;         ///< Max Read Latency (ns) for DCT 0
1784                                    ///<
1785   OUT UINT8   ChbD3BcRcvrdly;      ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
1786
1787   OUT DCT_STRUCT *DctData;         ///< Pointed to a dynamically allocated array of DCT_STRUCTs
1788   OUT UINT8   DctCount;            ///< Number of DCTs per this Die
1789   OUT UINT8   Reserved[16];        ///< Reserved
1790 } DIE_STRUCT;
1791
1792 /**********************************************************************
1793  * S3 Support structure
1794  **********************************************************************/
1795 /// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
1796 typedef struct {
1797      OUT   UINT32 Signature;           ///< "ASTR" for AMD Suspend-To-RAM
1798      OUT   UINT16 Version;             ///< S3 Params version number
1799   IN OUT   UINT32 Flags;               ///< Indicates operation
1800   IN OUT   VOID   *NvStorage;          ///< Pointer to memory critical save state data
1801   IN OUT   UINT32 NvStorageSize;       ///< Size in bytes of the NvStorage region
1802   IN OUT   VOID   *VolatileStorage;    ///< Pointer to remaining AMD save state data
1803   IN OUT   UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
1804 } AMD_S3_PARAMS;
1805
1806 ///===============================================================================
1807 /// MEM_PARAMETER_STRUCT
1808 /// This data structure is used to pass wrapper parameters to the memory configuration code
1809 ///
1810 typedef struct _MEM_PARAMETER_STRUCT {
1811
1812   // Basic (Return parameters)
1813   // (This section contains the outbound parameters from the memory init code)
1814
1815   OUT BOOLEAN GStatus[GsbEOL];    ///< Global Status bitfield.
1816                                   ///<
1817   OUT UINT32 HoleBase;            ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
1818                                   ///<
1819   OUT UINT32 Sub4GCacheTop;       ///< If not zero, the 32-bit top of cacheable memory.
1820                                   ///<
1821   OUT UINT32 Sub1THoleBase;       ///< If not zero Base[47:16] (system address) of sub 1TB dram hole.
1822                                   ///<
1823   OUT UINT32 SysLimit;            ///< Limit[47:16] (system address).
1824                                   ///<
1825   OUT DIMM_VOLTAGE DDR3Voltage;   ///< Find support voltage and send back to platform BIOS.
1826                                   ///<
1827   OUT UINT8 ExternalVrefValue;    ///< Target reference voltage for external Vref for training
1828                                   ///<
1829   OUT struct _MEM_DATA_STRUCT *MemData;   ///< Access to global memory init data.
1830
1831   //  Advanced (Optional parameters)
1832   //  Optional (all defaults values will be initialized by the
1833   //  'AmdMemInitDataStructDef' based on AMD defaults. It is up
1834   //  to the IBV/OEM to change the defaults after initialization
1835   //  but prior to the main entry to the memory code):
1836
1837   // Memory Map/Mgt.
1838
1839   IN UINT16  BottomIo;             ///< Bottom of 32-bit IO space (8-bits).
1840                                    ///<   NV_BOTTOM_IO[7:0]=Addr[31:24]
1841                                    ///<
1842   IN BOOLEAN MemHoleRemapping;     ///< Memory Hole Remapping (1-bit).
1843                                    ///<  FALSE = disable
1844                                    ///<  TRUE  = enable
1845                                    ///<
1846   IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB
1847                                    ///<  FALSE = disable
1848                                    ///<  TRUE  = enable
1849                                    ///<
1850                                    ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB}
1851
1852
1853   // Dram Timing
1854
1855   IN USER_MEMORY_TIMING_MODE   UserTimingMode;  ///< User Memclock Mode.
1856                                                 ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
1857
1858   IN MEMORY_BUS_SPEED          MemClockValue;   ///< Memory Clock Value.
1859                                                 ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
1860
1861
1862   // Dram Configuration
1863
1864   IN BOOLEAN EnableBankIntlv;      ///< Dram Bank (chip-select) Interleaving (1-bit).
1865                                    ///<  - FALSE =disable (default)
1866                                    ///<  - TRUE = enable
1867                                    ///<
1868                                    ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
1869
1870   IN BOOLEAN EnableNodeIntlv;      ///< Node Memory Interleaving (1-bit).
1871                                    ///<   - FALSE = disable (default)
1872                                    ///<   - TRUE = enable
1873                                    ///<
1874                                    ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
1875
1876   IN BOOLEAN EnableChannelIntlv;   ///< Channel Interleaving (1-bit).
1877                                    ///<   - FALSE = disable (default)
1878                                    ///<   - TRUE = enable
1879                                    ///<
1880                                    ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
1881   // ECC
1882
1883   IN BOOLEAN EnableEccFeature;     ///< enable ECC error to go into MCE.
1884                                    ///<   - FALSE = disable (default)
1885                                    ///<   - TRUE = enable
1886                                    ///<
1887                                    ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
1888   // Dram Power
1889
1890   IN BOOLEAN EnablePowerDown;      ///< CKE based power down mode (1-bit).
1891                                    ///<   - FALSE =disable (default)
1892                                    ///<   - TRUE =enable
1893                                    ///<
1894                                    ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
1895
1896   // Online Spare
1897
1898   IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
1899                                    ///<  - FALSE = disable Spare (default)
1900                                    ///<  - TRUE = enable Spare
1901                                    ///<
1902                                    ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
1903
1904   IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
1905
1906   IN PSO_TABLE *PlatformMemoryConfiguration;
1907                                    ///< A table that contains platform specific settings.
1908                                    ///< For example, MemClk routing, the number of DIMM slots per channel, ....
1909                                    ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
1910                                    ///< contains default conservative settings. Platform BIOS can either tweak
1911                                    ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
1912                                    ///<
1913   IN BOOLEAN EnableParity;         ///< Parity control.
1914                                    ///<  - TRUE = enable
1915                                    ///<  - FALSE = disable (default)
1916                                    ///<
1917                                    ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
1918
1919   IN BOOLEAN EnableBankSwizzle;    ///< BankSwizzle control.
1920                                    ///<  - FALSE = disable
1921                                    ///<  - TRUE = enable  (default)
1922                                    ///<
1923                                    ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
1924
1925                                    ///<
1926
1927   IN BOOLEAN EnableMemClr;         ///< Memory Clear functionality control.
1928                                    ///<  - FALSE = disable
1929                                    ///<  - TRUE = enable  (default)
1930                                    ///<
1931
1932   // Uma Configuration
1933
1934   IN UMA_MODE UmaMode;             ///<  Uma Mode
1935                                    ///<  0 = None
1936                                    ///<  1 = Specified
1937                                    ///<  2 = Auto
1938   IN OUT UINT32 UmaSize;           ///<  The size of shared graphics dram (16-bits)
1939                                    ///<  NV_UMA_Size[31:0]=Addr[47:16]
1940                                    ///<
1941   OUT UINT32 UmaBase;              ///<  The allocated Uma base address (32-bits)
1942                                    ///<  NV_UMA_Base[31:0]=Addr[47:16]
1943                                    ///<
1944
1945   /// Memory Restore Feature
1946
1947   IN BOOLEAN MemRestoreCtl;        ///< Memory context restore control
1948                                    ///<   FALSE = perform memory init as normal (AMD default)
1949                                    ///<   TRUE = restore memory context and skip training. This requires
1950                                    ///<          MemContext is valid before AmdInitPost
1951                                    ///<
1952   IN BOOLEAN SaveMemContextCtl;    ///< Control switch to save memory context at the end of MemAuto
1953                                    ///<   TRUE = AGESA will setup MemContext block before exit AmdInitPost
1954                                    ///<   FALSE = AGESA will not setup MemContext block. Platform is
1955                                    ///<           expected to call S3Save later in POST if it wants to
1956                                    ///<           use memory context restore feature.
1957                                    ///<
1958   IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
1959                                    ///< save and restore for memory context restore feature to work.
1960                                    ///< It uses the subset of S3Save block to save/restore. Hence platform
1961                                    ///< may save only S3 block and uses it for both S3 resume and
1962                                    ///< memory context restore.
1963                                    ///<  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
1964                                    ///<    before AmdInitPost.
1965                                    ///<  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
1966                                    ///<    right after AmdInitPost.
1967                                    ///<
1968   IN BOOLEAN ExternalVrefCtl;      ///< Control the use of external Vref
1969                                    ///<   TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list
1970                                    ///<          to change the vref
1971                                    ///<   FALSE = AGESA will will use the internal vref control.
1972                                    ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE}
1973                                    ///<
1974   IN FORCE_TRAIN_MODE ForceTrainMode;   ///<  Training Mode
1975                                    ///<  0 = Force 1D Training for all configurations
1976                                    ///<  1 = Force training for all configurations
1977                                    ///<  2 = Auto - AGESA will control
1978 } MEM_PARAMETER_STRUCT;
1979
1980
1981 ///
1982 /// Function definition.
1983 /// This data structure passes function pointers to the memory configuration code.
1984 /// The wrapper can use this structure with customized versions.
1985 ///
1986 typedef struct _MEM_FUNCTION_STRUCT {
1987
1988   // PUBLIC required Internal functions
1989
1990   IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData);  ///< Proc for Unbuffered DIMMs, platform specific
1991   IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData);   ///< Proc for Registered DIMMs, platform specific
1992
1993   // PUBLIC optional functions
1994
1995   IN OUT VOID (*amdMemEccInit) (VOID *pMemData);                  ///< NB proc for ECC feature
1996   IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
1997   IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData);      ///< NB proc for Channel interleave feature
1998   IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData);      ///< NB proc for Node interleave feature
1999   IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData);         ///< NB proc for parallel training feature
2000   IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData);       ///< NB code for early sample support feature
2001   IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData);     ///< NB code for 'multi-part'
2002   IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData);       ///< NB code for On-Line Spare feature
2003   IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData);                ///< NB code for UDIMMs
2004   IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData);                ///< NB code for RDIMMs
2005   IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData);               ///< NB code for LRDIMMs
2006   IN OUT UINT32   Reserved[100]; ///< Reserved for later function definition
2007 } MEM_FUNCTION_STRUCT;
2008
2009 ///
2010 /// Socket Structure
2011 ///
2012 ///
2013 typedef struct _MEM_SOCKET_STRUCT {
2014   OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels training data
2015
2016   OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels timing data
2017 } MEM_SOCKET_STRUCT;
2018
2019 ///
2020 /// Contains all data relevant to Memory Initialization.
2021 ///
2022 typedef struct _MEM_DATA_STRUCT {
2023   IN AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
2024
2025   IN MEM_PARAMETER_STRUCT *ParameterListPtr;  ///< List of input Parameters
2026
2027   OUT MEM_FUNCTION_STRUCT FunctionList;       ///< List of function Pointers
2028
2029   IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
2030
2031   IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
2032
2033
2034   OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED];  ///< Socket list for memory code.
2035                                    ///< SocketList is a shortcut for IBVs to retrieve training
2036                                    ///< and timing data for each channel indexed by socket/channel,
2037                                    ///< eliminating their need to parse die/dct/channel etc.
2038                                    ///< It contains pointers to the populated data structures for
2039                                    ///< each channel and skips the channel structures that are
2040                                    ///< unpopulated. In the case of channels sharing the same DCT,
2041                                    ///< the pTimings pointers will point to the same DCT Timing data.
2042
2043   OUT DIE_STRUCT *DiesPerSystem;  ///< Pointed to an array of DIE_STRUCTs
2044   OUT UINT8      DieCount;        ///< Number of MCTs in the system.
2045
2046   IN SPD_DEF_STRUCT *SpdDataStructure;              ///< Pointer to SPD Data structure
2047
2048   IN OUT  struct _PLATFORM_CONFIGURATION   *PlatFormConfig;    ///< Platform profile/build option config structure
2049
2050   IN OUT BOOLEAN IsFlowControlSupported;    ///< Indicates if flow control is supported
2051
2052   OUT UINT32 TscRate;             ///< The rate at which the TSC increments in megahertz.
2053
2054 } MEM_DATA_STRUCT;
2055
2056 ///
2057 /// Uma Structure
2058 ///
2059 ///
2060 typedef struct _UMA_INFO {
2061   OUT UINT64 UmaBase;          ///< UmaBase[63:0] = Addr[63:0]
2062   OUT UINT32 UmaSize;          ///< UmaSize[31:0] = Addr[31:0]
2063   OUT UINT32 UmaAttributes;    ///< Indicate the attribute of Uma
2064   OUT UINT8 UmaMode;           ///< Indicate the mode of Uma
2065   OUT UINT16 MemClock;         ///< Indicate memory running speed in MHz
2066   OUT UINT8 Reserved[3];       ///< Reserved for future usage
2067 } UMA_INFO;
2068
2069 /// Bitfield for ID
2070 typedef struct {
2071   OUT UINT16 SocketId:8;       ///< Socket ID
2072   OUT UINT16 ModuleId:8;       ///< Module ID
2073 } ID_FIELD;
2074 ///
2075 /// Union for ID of socket and module that will be passed out in call out
2076 ///
2077 typedef union {
2078   OUT ID_FIELD IdField;         ///< Bitfield for ID
2079   OUT UINT16 IdInformation;     ///< ID information for call out
2080 } ID_INFO;
2081
2082 //  AGESA MEMORY ERRORS
2083
2084 // AGESA_ALERT Memory Errors
2085 #define MEM_ALERT_USER_TMG_MODE_OVERRULED   0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
2086                                                        ///< cannot be applied to current configurations.
2087 #define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100          ///< DIMM organization miss-match
2088 #define MEM_ALERT_BK_INT_DIS 0x04010200                 ///< Bank interleaving disable for internal issue
2089
2090 // AGESA_ERROR Memory Errors
2091 #define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300     ///< No DQS Position window for RD DQS
2092 #define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300  ///< Small DQS Position window for RD DQS
2093 #define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300     ///< No DQS Position window for WR DQS
2094 #define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300  ///< Small DQS Position window for WR DQS
2095 #define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
2096 #define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
2097 #define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
2098 #define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
2099 #define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
2100 #define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
2101 #define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
2102 #define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
2103 #define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
2104 #define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
2105 #define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
2106 #define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
2107 #define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
2108 #define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
2109 #define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
2110 #define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
2111 #define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
2112 #define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
2113 #define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
2114 #define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
2115 #define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
2116 #define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
2117 #define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR  0x04011200    ///< SPD Checksum error for NV_SPDCHK_RESTRT
2118 #define MEM_ERROR_NO_CHIPSELECT 0x04011300              ///< No chipselects found
2119 #define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500   ///< Unbuffered dimm is not supported at 333MHz
2120 #define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300   ///< Returned PRE value during write levelizzation was out of range
2121 #define MEM_ERROR_NO____RDDQS_WINDOW 0x040D0300           ///< No RdDqs Window
2122 #define MEM_ERROR_NO____RDDQS_HEIGHT 0x040E0300  ///< No RdDqs Height
2123 #define MEM_ERROR____DQS_ERROR  0x040F0300 ///< RdDqs Error
2124 #define MEM_ERROR_INVALID____RDDQS_VALUE  0x04022400 ///< RdDqs invalid value found
2125 #define MEM_ERROR____DQS_VREF_MARGIN_ERROR  0x04023400 ///< RdDqs Vef Margin error found
2126 #define MEM_ERROR_LR_IBT_NOT_FOUND  0x04013500 ///< No LR dimm IBT value is found
2127 #define MEM_ERROR_MR0_NOT_FOUND  0x04023500 ///< No MR0 value is found
2128 #define MEM_ERROR_ODT_PATTERN_NOT_FOUND  0x04033500 ///< No odt pattern value is found
2129 #define MEM_ERROR_RC2_IBT_NOT_FOUND  0x04043500 ///< No RC2 IBT value is found
2130 #define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND  0x04053500 ///< No RC10 op speed is found
2131 #define MEM_ERROR_RTT_NOT_FOUND  0x04063500 ///< No RTT value is found
2132 #define MEM_ERROR_P___NOT_FOUND  0x04073500 ///< No training config value is found
2133 #define MEM_ERROR_SAO_NOT_FOUND  0x04083500 ///< No slow access mode, Address timing and Output driver compensation value is found
2134 #define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND  0x04093500 ///< No CLK disable map is found
2135 #define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND  0x040A3500 ///< No CKE tristate map is found
2136 #define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND  0x040B3500 ///< No ODT tristate map is found
2137 #define MEM_ERROR_CS_TRI_MAP_NOT_FOUND  0x040C3500 ///< No CS tristate map is found
2138 #define MEM_ERROR_TRAINING_SEED_NOT_FOUND  0x040D3500 ///< No training seed is found
2139
2140 // AGESA_WARNING Memory Errors
2141 #define MEM_WARNING_UNSUPPORTED_QRDIMM      0x04011600 ///< QR DIMMs detected but not supported
2142 #define MEM_WARNING_UNSUPPORTED_UDIMM       0x04021600 ///< U DIMMs detected but not supported
2143 #define MEM_WARNING_UNSUPPORTED_SODIMM      0x04031600 ///< SO-DIMMs detected but not supported
2144 #define MEM_WARNING_UNSUPPORTED_X4DIMM      0x04041600 ///< x4 DIMMs detected but not supported
2145 #define MEM_WARNING_UNSUPPORTED_RDIMM       0x04051600 ///< R DIMMs detected but not supported
2146 #define MEM_WARNING_UNSUPPORTED_LRDIMM      0x04061600 ///< LR DIMMs detected but not supported
2147 #define MEM_WARNING_EMP_NOT_SUPPORTED       0x04011700 ///< Processor is not capable for EMP
2148 #define MEM_WARNING_EMP_CONFLICT            0x04021700  ///< EMP cannot be enabled if channel interleaving,
2149 #define MEM_WARNING_EMP_NOT_ENABLED         0x04031700  ///< Memory size is not power of two.
2150 #define MEM_WARNING_ECC_DIS                 0x04041700  ///< ECC has been disabled as a result of an internal issue
2151 #define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800  ///< Performance has been enabled, but battery life is preferred.
2152                                                         ///< bank interleaving, or bank swizzle is enabled.
2153 #define MEM_WARNING_NO_SPDTRC_FOUND         0x04011900  ///< No Trc timing value found in SPD of a dimm.
2154 #define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000    ///< Node Interleaveing Requested, but could not be enabled
2155 #define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
2156 #define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
2157 #define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
2158 #define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO   0x04012400 ///< DDR3 voltage initial value is not 0
2159 #define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO   0x04012500 ///< Cannot find a commonly supported VDDIO
2160
2161 // AGESA_FATAL Memory Errors
2162 #define MEM_ERROR_MINIMUM_MODE 0x04011A00               ///< Running in minimum mode
2163 #define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00  ///< DIMM modules are miss-matched
2164 #define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00    ///< No DIMMs have been found
2165 #define MEM_ERROR_MISMATCH_DIMM_CLOCKS  0x04011D00      ///< DIMM clocks miss-matched
2166 #define MEM_ERROR_NO_CYC_TIME 0x04011E00                ///< No cycle time found
2167 #define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS   0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
2168 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs   0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
2169 #define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
2170 #define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD     0x04041F00    ///< Heap allocation error for SPD data
2171 #define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     0x04051F00    ///< Heap allocation error for RECEIVED_DATA during parallel training
2172 #define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     0x04061F00    ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
2173 #define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     0x04071F00   ///< Heap allocation error for Training Data
2174 #define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK     0x04081F00    ///< Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
2175 #define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM     0x04022300   ///< No Constructor for DIMM Identify
2176 #define MEM_ERROR_VDDIO_UNSUPPORTED      0x04022500     ///< VDDIO of the dimms on the board is not supported
2177 #define MEM_ERROR_HEAP_ALLOCATE_FOR___     0x040B1F00    ///< Heap allocation error for training data
2178 #define MEM_ERROR_HEAP_DEALLOCATE_FOR___     0x040C1F00    ///< Heap de-allocation error for training data
2179
2180 // AGESA_CRITICAL Memory Errors
2181 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3     0x04091F00    ///< Heap allocation error for DMI table for DDR3
2182 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2     0x040A1F00    ///< Heap allocation error for DMI table for DDR2
2183 #define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG              0x04011400    ///< Dimm population is not supported
2184
2185
2186
2187 /*----------------------------------------------------------------------------
2188  *
2189  *                END OF MEMORY-SPECIFIC DATA STRUCTURES
2190  *
2191  *----------------------------------------------------------------------------
2192  */
2193
2194
2195
2196
2197 /*----------------------------------------------------------------------------
2198  *
2199  *                    CPU RELATED DEFINITIONS
2200  *
2201  *----------------------------------------------------------------------------
2202  */
2203
2204 // CPU Event definitions.
2205
2206 // Defines used to filter CPU events based on functional blocks
2207 #define CPU_EVENT_PM_EVENT_MASK                         0xFF00FF00
2208 #define CPU_EVENT_PM_EVENT_CLASS                        0x08000400
2209
2210 //================================================================
2211 // CPU General events
2212 //    Heap allocation                     (AppFunction =      01h)
2213 #define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            0x08000100
2214 #define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           0x08010100
2215 #define CPU_ERROR_HEAP_IS_FULL                          0x08020100
2216 #define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    0x08030100
2217 #define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     0x08040100
2218 //    BrandId                             (AppFunction =      02h)
2219 #define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            0x08000200
2220 //    Micro code patch                    (AppFunction =      03h)
2221 #define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        0x08000300
2222 //    Power management                    (AppFunction =      04h)
2223 #define CPU_EVENT_PM_PSTATE_OVERCURRENT                 0x08000400
2224 #define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             0x08010400
2225 #define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             0x08020400
2226 #define CPU_ERROR_PM_NB_PSTATE_MISMATCH                 0x08030400
2227 //    Other CPU events                    (AppFunction =      05h)
2228 #define CPU_EVENT_BIST_ERROR                            0x08000500
2229 #define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY              0x08010500
2230 #define CPU_EVENT_STACK_REENTRY                         0x08020500
2231 #define CPU_EVENT_CORE_NOT_IDENTIFIED                   0x08030500
2232
2233 //=================================================================
2234 // CPU Feature events
2235 //    Execution cache                     (AppFunction =      21h)
2236 //        AGESA_CACHE_SIZE_REDUCED                            2101
2237 //        AGESA_CACHE_REGIONS_ACROSS_1MB                      2102
2238 //        AGESA_CACHE_REGIONS_ACROSS_4GB                      2103
2239 //        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY                2104
2240 //        AGESA_CACHE_START_ADDRESS_LESS_D0000                2105
2241 //        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB                 2106
2242 //        AGESA_DEALLOCATE_CACHE_REGIONS                      2107
2243 #define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      0x08002100
2244 //    Core Leveling                       (AppFunction =      22h)
2245 #define CPU_WARNING_ADJUSTED_LEVELING_MODE              0x08002200
2246 //    HT Assist                           (AppFunction =      23h)
2247 #define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            0x08002300
2248
2249 // CPU Build Configuration structures and definitions
2250
2251 /// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
2252 typedef struct {
2253   IN  UINT32 MsrAddr;     ///< Fixed-Sized MTRR address
2254   IN  UINT64 MsrData;     ///< MTRR Settings
2255 } AP_MTRR_SETTINGS;
2256
2257 #define AMD_AP_MTRR_FIX64k_00000    0x00000250
2258 #define AMD_AP_MTRR_FIX16k_80000    0x00000258
2259 #define AMD_AP_MTRR_FIX16k_A0000    0x00000259
2260 #define AMD_AP_MTRR_FIX4k_C0000     0x00000268
2261 #define AMD_AP_MTRR_FIX4k_C8000     0x00000269
2262 #define AMD_AP_MTRR_FIX4k_D0000     0x0000026A
2263 #define AMD_AP_MTRR_FIX4k_D8000     0x0000026B
2264 #define AMD_AP_MTRR_FIX4k_E0000     0x0000026C
2265 #define AMD_AP_MTRR_FIX4k_E8000     0x0000026D
2266 #define AMD_AP_MTRR_FIX4k_F0000     0x0000026E
2267 #define AMD_AP_MTRR_FIX4k_F8000     0x0000026F
2268 #define CPU_LIST_TERMINAL           0xFFFFFFFF
2269
2270 /// Data structure for the Mapping Item between Unified ID for IDS Setup Option
2271 /// and the option value.
2272 ///
2273 typedef struct {
2274   IN    UINT16 IdsNvId;           ///< Unified ID for IDS Setup Option.
2275   OUT UINT16 IdsNvValue;        ///< The value of IDS Setup Option.
2276 } IDS_NV_ITEM;
2277
2278 /// Data Structure for IDS CallOut Function
2279 typedef struct {
2280   IN    AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
2281   IN    IDS_NV_ITEM *IdsNvPtr;              ///< Memory Pointer of IDS NV Table
2282   IN OUT UINTN Reserved;              ///< reserved
2283 } IDS_CALLOUT_STRUCT;
2284
2285 /************************************************************************
2286  *
2287  *  AGESA interface Call-Out function parameter structures
2288  *
2289  ***********************************************************************/
2290
2291 /// Parameters structure for interface call-out AgesaAllocateBuffer
2292 typedef struct {
2293   IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
2294   IN OUT    UINT32              BufferLength;   ///< Size of buffer to allocate
2295   IN        UINT32              BufferHandle;   ///< Identifier or name for the buffer
2296   OUT       VOID                *BufferPointer; ///< location of the created buffer
2297 } AGESA_BUFFER_PARAMS;
2298
2299 /// Parameters structure for interface call-out AgesaRunCodeOnAp
2300 typedef struct {
2301   IN OUT    AMD_CONFIG_PARAMS   StdHeader;            ///< Standard configuration header
2302   IN        UINT32              FunctionNumber;       ///< Index of the procedure to execute
2303   IN        VOID                *RelatedDataBlock;    ///< Location of data structure the procedure will use
2304   IN        UINT32              RelatedBlockLength;   ///< Size of the related data block
2305 } AP_EXE_PARAMS;
2306
2307 /// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
2308 typedef struct {
2309   IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
2310   IN        UINT8               SocketId;       ///< Address of SPD - socket ID
2311   IN        UINT8               MemChannelId;   ///< Address of SPD - memory channel ID
2312   IN        UINT8               DimmId;         ///< Address of SPD - DIMM ID
2313   IN OUT    UINT8               *Buffer;        ///< Location where to place the SPD content
2314   IN OUT    MEM_DATA_STRUCT     *MemData;       ///< Location of the MemData structure, for reference
2315 } AGESA_READ_SPD_PARAMS;
2316
2317 /// Buffer Handles
2318 typedef enum {
2319   AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000,       ///< Assign 0x000D000 buffer handle to DMI function
2320   AMD_PSTATE_DATA_BUFFER_HANDLE,                ///< Assign 0x000D001 buffer handle to Pstate data
2321   AMD_PSTATE_ACPI_BUFFER_HANDLE,                ///< Assign 0x000D002 buffer handle to Pstate table
2322   AMD_BRAND_ID_BUFFER_HANDLE,                   ///< Assign 0x000D003 buffer handle to Brand ID
2323   AMD_ACPI_SLIT_BUFFER_HANDLE,                  ///< Assign 0x000D004 buffer handle to SLIT function
2324   AMD_SRAT_INFO_BUFFER_HANDLE,                  ///< Assign 0x000D005 buffer handle to SRAT function
2325   AMD_WHEA_BUFFER_HANDLE,                       ///< Assign 0x000D006 buffer handle to WHEA function
2326   AMD_S3_INFO_BUFFER_HANDLE,                    ///< Assign 0x000D007 buffer handle to S3 function
2327   AMD_S3_NB_INFO_BUFFER_HANDLE,                 ///< Assign 0x000D008 buffer handle to S3 NB device info
2328   AMD_ACPI_ALIB_BUFFER_HANDLE,                  ///< Assign 0x000D009 buffer handle to ALIB SSDT table
2329   AMD_ACPI_IVRS_BUFFER_HANDLE                   ///< Assign 0x000D00A buffer handle to IOMMU IVRS table
2330 } AMD_BUFFER_HANDLE;
2331 /************************************************************************
2332  *
2333  *  AGESA interface Call-Out function prototypes
2334  *
2335  ***********************************************************************/
2336
2337 VOID
2338 AgesaDoReset (
2339   IN        UINTN               ResetType,
2340   IN OUT    AMD_CONFIG_PARAMS   *StdHeader
2341   );
2342
2343 AGESA_STATUS
2344 AgesaAllocateBuffer (
2345   IN      UINTN                 FcnData,
2346   IN OUT  AGESA_BUFFER_PARAMS   *AllocParams
2347   );
2348
2349 AGESA_STATUS
2350 AgesaDeallocateBuffer (
2351   IN      UINTN                 FcnData,
2352   IN OUT  AGESA_BUFFER_PARAMS   *DeallocParams
2353   );
2354
2355 AGESA_STATUS
2356 AgesaLocateBuffer (
2357   IN      UINTN                 FcnData,
2358   IN OUT  AGESA_BUFFER_PARAMS   *LocateParams
2359   );
2360
2361 AGESA_STATUS
2362 AgesaReadSpd (
2363   IN        UINTN                 FcnData,
2364   IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
2365   );
2366
2367 AGESA_STATUS
2368 AgesaReadSpdRecovery (
2369   IN        UINTN                 FcnData,
2370   IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
2371   );
2372
2373 AGESA_STATUS
2374 AgesaHookBeforeDramInitRecovery (
2375   IN       UINTN           FcnData,
2376   IN OUT   MEM_DATA_STRUCT *MemData
2377   );
2378
2379 AGESA_STATUS
2380 AgesaRunFcnOnAp (
2381   IN        UINTN               ApicIdOfCore,
2382   IN        AP_EXE_PARAMS       *LaunchApParams
2383   );
2384
2385 AGESA_STATUS
2386 AgesaHookBeforeDramInit (
2387   IN        UINTN               SocketIdModuleId,
2388   IN OUT    MEM_DATA_STRUCT     *MemData
2389   );
2390
2391 AGESA_STATUS
2392 AgesaHookBeforeDQSTraining (
2393   IN        UINTN               SocketIdModuleId,
2394   IN OUT    MEM_DATA_STRUCT     *MemData
2395   );
2396
2397 AGESA_STATUS
2398 AgesaHookBeforeExitSelfRefresh (
2399   IN        UINTN               FcnData,
2400   IN OUT    MEM_DATA_STRUCT     *MemData
2401   );
2402
2403 AGESA_STATUS
2404 AgesaPcieSlotResetControl (
2405   IN      UINTN                 FcnData,
2406   IN      PCIe_SLOT_RESET_INFO  *ResetInfo
2407  );
2408
2409 AGESA_STATUS
2410 AgesaFchOemCallout (
2411   IN      VOID                  *FchData
2412  );
2413
2414 AGESA_STATUS
2415 AgesaExternal__TrainVrefChange (
2416   IN        UINTN               SocketIdModuleId,
2417   IN OUT    MEM_DATA_STRUCT     *MemData
2418   );
2419
2420 AGESA_STATUS
2421 AgesaGetIdsData  (
2422   IN       UINTN              Data,
2423   IN OUT   IDS_CALLOUT_STRUCT *IdsCalloutData
2424   );
2425 /************************************************************************
2426  *
2427  *  AGESA interface structure definition and function prototypes
2428  *
2429  ***********************************************************************/
2430
2431 /**********************************************************************
2432  * Platform Configuration:  The parameters in boot branch function
2433  **********************************************************************/
2434
2435 ///  The possible platform control flow settings.
2436 typedef enum  {
2437   Nfcm,                                          ///< Normal Flow Control Mode.
2438   UmaDr,                                         ///< UMA using Display Refresh flow control.
2439   UmaIfcm,                                       ///< UMA using Isochronous Flow Control.
2440   Ifcm,                                          ///< Isochronous Flow Control Mode (other than for UMA).
2441   Iommu,                                         ///< An IOMMU is in use in the system.
2442   MaxControlFlow                                 ///< Not a control flow mode, use for limit checking.
2443 } PLATFORM_CONTROL_FLOW;
2444
2445 ///  Platform Deemphasis Levels.
2446 ///
2447 /// The deemphasis level is set for the receiver, based on link characterization.  The DCV level is
2448 /// set based on the level of the far transmitter.
2449 typedef enum {
2450   DeemphasisLevelNone,                           ///< No Deemphasis.
2451   DeemphasisLevelMinus3,                         ///< Minus 3 db deemphasis.
2452   DeemphasisLevelMinus6,                         ///< Minus 6 db deemphasis.
2453   DeemphasisLevelMinus8,                         ///< Minus 8 db deemphasis.
2454   DeemphasisLevelMinus11,                        ///< Minus 11 db deemphasis.
2455   DeemphasisLevelMinus11pre8,                    ///< Minus 11, Minus 8 precursor db deemphasis.
2456   DcvLevelNone = 16,                             ///< No DCV Deemphasis.
2457   DcvLevelMinus2,                                ///< Minus 2 db DCV deemphasis.
2458   DcvLevelMinus3,                                ///< Minus 3 db DCV deemphasis.
2459   DcvLevelMinus5,                                ///< Minus 5 db DCV deemphasis.
2460   DcvLevelMinus6,                                ///< Minus 6 db DCV deemphasis.
2461   DcvLevelMinus7,                                ///< Minus 7 db DCV deemphasis.
2462   DcvLevelMinus8,                                ///< Minus 8 db DCV deemphasis.
2463   DcvLevelMinus9,                                ///< Minus 9 db DCV deemphasis.
2464   DcvLevelMinus11,                               ///< Minus 11 db DCV deemphasis.
2465   MaxPlatformDeemphasisLevel                     ///< Not a deemphasis level, use for limit checking.
2466 } PLATFORM_DEEMPHASIS_LEVEL;
2467
2468 ///  Provide Deemphasis Levels for HT Links.
2469 ///
2470 ///  For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
2471 ///  be checked for a match.  The item matches for a Socket, Link if the link frequency is
2472 ///  is in the inclusive range HighFreq:LoFreq.
2473 ///  AGESA does not set deemphasis in IO devices, only in processors.
2474
2475 typedef struct {
2476   // Match fields
2477   IN       UINT8 Socket;                                        ///< One Socket on which this Link is located
2478   IN       UINT8 Link;                                          ///< The Link on this Processor.
2479   IN       UINT8 LoFreq;                                        ///< If the link is set to this frequency or greater, apply these levels, and
2480   IN       UINT8 HighFreq;                                      ///< If the link is set to this frequency or less, apply these levels.
2481   // Value fields
2482   IN       PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;    ///< The deemphasis level for this link
2483   IN       PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;         ///< The DCV, or far transmitter deemphasis level.
2484 } CPU_HT_DEEMPHASIS_LEVEL;
2485
2486
2487 ///  The possible hardware prefetch mode settings.
2488 typedef enum  {
2489   HARDWARE_PREFETCHER_AUTO,                     ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
2490   DISABLE_L1_PREFETCHER,                        ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching.
2491   DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES,  ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
2492   DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES,  ///< Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches.
2493   DISABLE_HARDWARE_PREFETCH,                    ///< Disable hardware prefetching.
2494   MAX_HARDWARE_PREFETCH_MODE                    ///< Not a hardware prefetch mode, use for limit checking.
2495 } HARDWARE_PREFETCH_MODE;
2496
2497 ///  The possible software prefetch mode settings.
2498 typedef enum  {
2499   SOFTWARE_PREFETCHES_AUTO,                     ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
2500   DISABLE_SOFTWARE_PREFETCHES,                  ///< Disable software prefetches (convert software prefetch instructions to NOP).
2501   MAX_SOFTWARE_PREFETCH_MODE                    ///< Not a software prefetch mode, use for limit checking.
2502 } SOFTWARE_PREFETCH_MODE;
2503
2504 /// Advanced performance tunings, prefetchers.
2505 /// These settings provide for performance tuning to optimize for specific workloads.
2506 typedef struct {
2507   IN HARDWARE_PREFETCH_MODE  HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
2508   IN SOFTWARE_PREFETCH_MODE  SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions.
2509   IN DRAM_PREFETCH_MODE      DramPrefetchMode;     ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
2510 } ADVANCED_PERFORMANCE_PROFILE;
2511
2512 ///  The possible platform power policy settings.
2513 typedef enum  {
2514   Performance,                                   ///< Optimize for performance.
2515   BatteryLife,                                   ///< Optimize for battery life.
2516   MaxPowerPolicy                                 ///< Not a power policy mode, use for limit checking.
2517 } PLATFORM_POWER_POLICY;
2518
2519 ///  Platform performance settings for optimized settings.
2520 ///  Several configuration settings for the processor depend upon other parts and
2521 ///  general designer choices for the system. The determination of these data points
2522 ///  is not standard for all platforms, so the host environment needs to provide these
2523 ///  to specify how the system is to be configured.
2524 typedef struct {
2525   IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;    ///< The platform's control flow mode for optimum platform performance.
2526                                                        ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
2527   IN BOOLEAN               UseHtAssist;                ///< HyperTransport link traffic optimization.
2528                                                        ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
2529   IN BOOLEAN               UseAtmMode;                 ///< HyperTransport link traffic optimization.
2530                                                        ///< @BldCfgItem{BLDCFG_USE_ATM_MODE}
2531   IN BOOLEAN               Use32ByteRefresh;           ///< Display Refresh traffic generates 32 byte requests.
2532                                                        ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
2533   IN BOOLEAN               UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
2534                                                        ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
2535   IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile;   ///< The advanced platform performance settings.
2536   IN PLATFORM_POWER_POLICY PlatformPowerPolicy;        ///< The platform's desired power policy
2537                                                        ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
2538 } PERFORMANCE_PROFILE;
2539
2540 ///  Platform settings that describe the voltage regulator modules of the system.
2541 ///  Many power management settings are dependent upon the characteristics of the
2542 ///  on-board voltage regulator module (VRM).  The host environment needs to provide
2543 ///  these to specify how the system is to be configured.
2544 typedef struct {
2545   IN UINT32  CurrentLimit;                         ///< Vrm Current Limit.
2546                                                    ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
2547                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
2548   IN UINT32  LowPowerThreshold;                    ///< Vrm Low Power Threshold.
2549                                                    ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
2550                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
2551   IN UINT32  SlewRate;                             ///< Vrm Slew Rate.
2552                                                    ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
2553                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
2554   IN UINT32  AdditionalDelay;                      ///< Vrm Additional Delay.
2555                                                    ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY}
2556                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY}
2557   IN BOOLEAN HiSpeedEnable;                        ///< Select high speed VRM.
2558                                                    ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
2559                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
2560   IN UINT32  InrushCurrentLimit;                   ///< Vrm Inrush Current Limit.
2561                                                    ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT}
2562                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT}
2563 } PLATFORM_VRM_CONFIGURATION;
2564
2565 ///  The VRM types to characterize.
2566 typedef enum  {
2567   CoreVrm,                                       ///< VDD plane.
2568   NbVrm,                                         ///< VDDNB plane.
2569   MaxVrmType                                     ///< Not a valid VRM type, use for limit checking.
2570 } PLATFORM_VRM_TYPE;
2571
2572
2573 /// FCH Platform Configuration Policy
2574 typedef struct {
2575   IN UINT16     CfgSmbus0BaseAddress;             ///< SMBUS0 Controller Base Address
2576   IN UINT16     CfgSmbus1BaseAddress;             ///< SMBUS1 Controller Base Address
2577   IN UINT16     CfgSioPmeBaseAddress;             ///< I/O base address for LPC I/O target range
2578   IN UINT16     CfgAcpiPm1EvtBlkAddr;             ///< I/O base address of ACPI power management Event Block
2579   IN UINT16     CfgAcpiPm1CntBlkAddr;             ///< I/O base address of ACPI power management Control Block
2580   IN UINT16     CfgAcpiPmTmrBlkAddr;              ///< I/O base address of ACPI power management Timer Block
2581   IN UINT16     CfgCpuControlBlkAddr;             ///< I/O base address of ACPI power management CPU Control Block
2582   IN UINT16     CfgAcpiGpe0BlkAddr;               ///< I/O base address of ACPI power management General Purpose Event Block
2583   IN UINT16     CfgSmiCmdPortAddr;                ///< I/O base address of ACPI SMI Command Block
2584   IN UINT16     CfgAcpiPmaCntBlkAddr;             ///< I/O base address of ACPI power management additional control block
2585   IN UINT32     CfgGecShadowRomBase;              ///< 32-bit base address to the GEC shadow ROM
2586   IN UINT32     CfgWatchDogTimerBase;             ///< Watchdog Timer base address
2587   IN UINT32     CfgSpiRomBaseAddress;             ///< Base address for the SPI ROM controller
2588   IN UINT32     CfgHpetBaseAddress;               ///< HPET MMIO base address
2589   IN UINT32     CfgAzaliaSsid;                    ///< Subsystem ID of HD Audio controller
2590   IN UINT32     CfgSmbusSsid;                     ///< Subsystem ID of SMBUS controller
2591   IN UINT32     CfgIdeSsid;                       ///< Subsystem ID of IDE controller
2592   IN UINT32     CfgSataAhciSsid;                  ///< Subsystem ID of SATA controller in AHCI mode
2593   IN UINT32     CfgSataIdeSsid;                   ///< Subsystem ID of SATA controller in IDE mode
2594   IN UINT32     CfgSataRaid5Ssid;                 ///< Subsystem ID of SATA controller in RAID5 mode
2595   IN UINT32     CfgSataRaidSsid;                  ///< Subsystem ID of SATA controller in RAID mode
2596   IN UINT32     CfgEhciSsid;                      ///< Subsystem ID of EHCI
2597   IN UINT32     CfgOhciSsid;                      ///< Subsystem ID of OHCI
2598   IN UINT32     CfgLpcSsid;                       ///< Subsystem ID of LPC ISA Bridge
2599   IN UINT32     CfgSdSsid;                        ///< Subsystem ID of SecureDigital controller
2600   IN UINT32     CfgXhciSsid;                      ///< Subsystem ID of XHCI
2601   IN BOOLEAN    CfgFchPort80BehindPcib;           ///< Is port80 cycle going to the PCI bridge
2602   IN BOOLEAN    CfgFchEnableAcpiSleepTrap;        ///< ACPI sleep SMI enable/disable
2603   IN GPP_LINKMODE CfgFchGppLinkConfig;            ///< GPP link configuration
2604   IN BOOLEAN    CfgFchGppPort0Present;            ///< Is FCH GPP port 0 present
2605   IN BOOLEAN    CfgFchGppPort1Present;            ///< Is FCH GPP port 1 present
2606   IN BOOLEAN    CfgFchGppPort2Present;            ///< Is FCH GPP port 2 present
2607   IN BOOLEAN    CfgFchGppPort3Present;            ///< Is FCH GPP port 3 present
2608   IN BOOLEAN    CfgFchGppPort0HotPlug;            ///< Is FCH GPP port 0 hotplug capable
2609   IN BOOLEAN    CfgFchGppPort1HotPlug;            ///< Is FCH GPP port 1 hotplug capable
2610   IN BOOLEAN    CfgFchGppPort2HotPlug;            ///< Is FCH GPP port 2 hotplug capable
2611   IN BOOLEAN    CfgFchGppPort3HotPlug;            ///< Is FCH GPP port 3 hotplug capable
2612
2613   IN UINT8   CfgFchEsataPortBitMap;               ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
2614   IN UINT8   CfgFchIrPinControl;                  ///< Register bitfield describing Infrared Pin Control:
2615                                                   ///<   [0] - IR Enable 0
2616                                                   ///<   [1] - IR Enable 1
2617                                                   ///<   [2] - IR Tx0
2618                                                   ///<   [3] - IR Tx1
2619                                                   ///<   [4] - IR Open Drain
2620                                                   ///<   [5] - IR Enable LED
2621   IN SD_CLOCK_CONTROL CfgFchSdClockControl;       ///< FCH SD Clock Control
2622   IN SCI_MAP_CONTROL  *CfgFchSciMapControl;       ///< FCH SCI Mapping Control
2623   IN SATA_PHY_CONTROL *CfgFchSataPhyControl;      ///< FCH SATA PHY Control
2624   IN GPIO_CONTROL     *CfgFchGpioControl;         ///< FCH GPIO Control
2625 } FCH_PLATFORM_POLICY;
2626
2627
2628 /// Build Option/Configuration Boolean Structure.
2629 typedef struct {
2630   IN  AMD_CODE_HEADER VersionString;              ///< AMD embedded code version string
2631
2632   //Build Option Area
2633   IN BOOLEAN OptionUDimms;                        ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
2634   IN BOOLEAN OptionRDimms;                        ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
2635   IN BOOLEAN OptionLrDimms;                      ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
2636   IN BOOLEAN OptionEcc;                           ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
2637   IN BOOLEAN OptionBankInterleave;                ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
2638   IN BOOLEAN OptionDctInterleave;                 ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
2639   IN BOOLEAN OptionNodeInterleave;                ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
2640   IN BOOLEAN OptionParallelTraining;              ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
2641   IN BOOLEAN OptionOnlineSpare;                   ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
2642   IN BOOLEAN OptionMemRestore;                    ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
2643   IN BOOLEAN OptionMultisocket;                   ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
2644   IN BOOLEAN OptionAcpiPstates;                   ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
2645   IN BOOLEAN OptionPStatesInHpcMode;              ///< @ref BLDCFG_PSTATE_HPC_MODE "BLDCFG_PSTATE_HPC_MODE"
2646   IN BOOLEAN OptionSrat;                          ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
2647   IN BOOLEAN OptionSlit;                          ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
2648   IN BOOLEAN OptionWhea;                          ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
2649   IN BOOLEAN OptionDmi;                           ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
2650   IN BOOLEAN OptionEarlySamples;                  ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
2651   IN BOOLEAN OptionAddrToCsTranslator;            ///< ADDR_TO_CS_TRANSLATOR
2652
2653   //Build Configuration Area
2654   IN UINT64 CfgPciMmioAddress;                    ///< Pci Mmio Base Address to use for PCI Config accesses.
2655                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
2656   IN UINT32 CfgPciMmioSize;                       ///< Pci Mmio region Size.
2657                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
2658   IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
2659   IN UINT32 CfgPlatNumIoApics;                    ///< The number of IO APICS for the platform.
2660   IN UINT32 CfgMemInitPstate;                     ///< Memory Init Pstate.
2661   IN PLATFORM_C1E_MODES CfgPlatformC1eMode;       ///< Select the C1e Mode that will used.
2662   IN UINT32 CfgPlatformC1eOpData;                 ///< An IO port or additional C1e setup data, depends on C1e mode.
2663   IN UINT32 CfgPlatformC1eOpData1;                ///< An IO port or additional C1e setup data, depends on C1e mode.
2664   IN UINT32 CfgPlatformC1eOpData2;                ///< An IO port or additional C1e setup data, depends on C1e mode.
2665   IN UINT32 CfgPlatformC1eOpData3;                ///< An IO port or additional C1e setup data, depends on C1e mode.
2666   IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
2667   IN UINT32 CfgPlatformCStateOpData;              ///< An IO port or additional C-State setup data, depends on C-State mode.
2668   IN UINT16 CfgPlatformCStateIoBaseAddress;       ///< Specifies I/O ports that can be used to allow CPU to enter CStates
2669   IN PLATFORM_CPB_MODES CfgPlatformCpbMode;       ///< Enable or disable core performance boost
2670   IN PLATFORM_LOW_POWER_PSTATE_MODES CfgLowPowerPstateForProcHot; ///< Low power Pstate for PROCHOT mode
2671   IN UINT32 CfgCoreLevelingMode;                  ///< Apply any downcoring or core count leveling as specified.
2672   IN PERFORMANCE_PROFILE CfgPerformanceProfile;   ///< The platform's control flow mode and platform performance settings.
2673   IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
2674
2675   IN UINT32 CfgAmdPlatformType;                   ///< Designate the platform as a Server, Desktop, or Mobile.
2676   IN UINT32 CfgAmdPstateCapValue;                 ///< Amd pstate ceiling enabling deck
2677
2678   IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
2679                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
2680   IN BOOLEAN CfgMemoryModeUnganged;               ///< Memory Mode Unganged.
2681                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
2682   IN BOOLEAN CfgMemoryQuadRankCapable;            ///< Memory Quad Rank Capable.
2683                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
2684   IN QUANDRANK_TYPE CfgMemoryQuadrankType;        ///< Memory Quadrank Type.
2685                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
2686   IN BOOLEAN CfgMemoryRDimmCapable;               ///< Memory RDIMM Capable.
2687   IN BOOLEAN CfgMemoryLRDimmCapable;              ///< Memory LRDIMM Capable.
2688   IN BOOLEAN CfgMemoryUDimmCapable;               ///< Memory UDIMM Capable.
2689   IN BOOLEAN CfgMemorySODimmCapable;              ///< Memory SODimm Capable.
2690                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
2691   IN BOOLEAN CfgLimitMemoryToBelow1Tb;            ///< Limit memory address space to below 1TB
2692   IN BOOLEAN CfgMemoryEnableBankInterleaving;     ///< Memory Enable Bank Interleaving.
2693   IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
2694   IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
2695   IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
2696   IN POWER_DOWN_MODE CfgPowerDownMode;            ///< Power Down Mode.
2697   IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
2698   IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.
2699   IN BOOLEAN CfgBankSwizzle;                      ///< Bank Swizzle.
2700   IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select.
2701   IN MEMORY_BUS_SPEED CfgMemoryClockSelect;       ///< Memory Clock Select.
2702   IN BOOLEAN CfgDqsTrainingControl;               ///< Dqs Training Control.
2703                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
2704   IN BOOLEAN CfgIgnoreSpdChecksum;                ///< Ignore Spd Checksum.
2705                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
2706   IN BOOLEAN CfgUseBurstMode;                     ///< Use Burst Mode.
2707                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
2708   IN BOOLEAN CfgMemoryAllClocksOn;                ///< Memory All Clocks On.
2709                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
2710   IN BOOLEAN CfgEnableEccFeature;                 ///< Enable ECC Feature.
2711   IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection.
2712                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
2713   IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate.
2714                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
2715   IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate.
2716                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
2717   IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate.
2718                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
2719   IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate.
2720                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
2721   IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate.
2722                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
2723   IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood.
2724                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
2725   IN UINT16  CfgEccSymbolSize;                    ///< ECC Symbol Size.
2726                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
2727   IN UINT64  CfgHeapDramAddress;                  ///< Heap contents will be temporarily stored in this address during the transition.
2728                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
2729   IN BOOLEAN CfgNodeMem1GBAlign;                  ///< Node Mem 1GB boundary Alignment
2730   IN BOOLEAN CfgS3LateRestore;                    ///< S3 Late Restore
2731   IN BOOLEAN CfgAcpiPstateIndependent;            ///< PSD method dependent/Independent
2732   IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList;     ///< The AP's MTRR settings before final halt
2733                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
2734   IN UMA_MODE CfgUmaMode;                         ///< Uma Mode
2735   IN UINT32 CfgUmaSize;                           ///< Uma Size [31:0]=Addr[47:16]
2736   IN BOOLEAN CfgUmaAbove4G;                       ///< Uma Above 4G Support
2737   IN UMA_ALIGNMENT CfgUmaAlignment;               ///< Uma alignment
2738   IN BOOLEAN CfgProcessorScopeInSb;               ///< ACPI Processor Object in \\_SB scope
2739   IN CHAR8   CfgProcessorScopeName0;              ///< OEM specific 1st character of processor scope name.
2740   IN CHAR8   CfgProcessorScopeName1;              ///< OEM specific 2nd character of processor scope name.
2741   IN UINT8   CfgGnbHdAudio;                       ///< GNB HD Audio
2742   IN UINT8   CfgAbmSupport;                       ///< Abm Support
2743   IN UINT8   CfgDynamicRefreshRate;               ///< DRR Dynamic Refresh Rate
2744   IN UINT16  CfgLcdBackLightControl;              ///< LCD Backlight Control
2745   IN UINT8   CfgGnb3dStereoPinIndex;                ///< 3D Stereo Pin ID.
2746   IN UINT32  CfgTempPcieMmioBaseAddress;          ///< Temp pcie MMIO base Address
2747                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
2748   IN UINT32  CfgGnbIGPUSSID;                      ///< Gnb internal GPU SSID
2749                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
2750   IN UINT32  CfgGnbHDAudioSSID;                   ///< Gnb HD Audio SSID
2751                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
2752   IN UINT32  CfgGnbPcieSSID;                      ///< Gnb PCIe SSID
2753                                                   ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
2754   IN UINT16  CfgLvdsSpreadSpectrum;               ///< Lvds Spread Spectrum
2755                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
2756   IN UINT16  CfgLvdsSpreadSpectrumRate;           ///< Lvds Spread Spectrum Rate
2757                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
2758   IN FCH_PLATFORM_POLICY  *FchBldCfg;             ///< FCH platform build configuration policy
2759
2760   IN BOOLEAN    CfgIommuSupport;                  ///< IOMMU support
2761   IN UINT8      CfgLvdsPowerOnSeqDigonToDe;       ///< Panel initialization timing
2762   IN UINT8      CfgLvdsPowerOnSeqDeToVaryBl;      ///< Panel initialization timing
2763   IN UINT8      CfgLvdsPowerOnSeqDeToDigon;       ///< Panel initialization timing
2764   IN UINT8      CfgLvdsPowerOnSeqVaryBlToDe;      ///< Panel initialization timing
2765   IN UINT8      CfgLvdsPowerOnSeqOnToOffDelay;    ///< Panel initialization timing
2766   IN UINT8      CfgLvdsPowerOnSeqVaryBlToBlon;    ///< Panel initialization timing
2767   IN UINT8      CfgLvdsPowerOnSeqBlonToVaryBl;    ///< Panel initialization timing
2768   IN UINT16     CfgLvdsMaxPixelClockFreq;         ///< The maximum pixel clock frequency supported
2769   IN UINT32     CfgLcdBitDepthControlValue;       ///< The LCD bit depth control settings
2770   IN UINT8      CfgLvds24bbpPanelMode;            ///< The LVDS 24 BBP mode
2771   IN LVDS_MISC_CONTROL CfgLvdsMiscControl;        ///< THe LVDS Misc control
2772   IN UINT16     CfgPcieRefClkSpreadSpectrum;      ///< PCIe Reference Clock Spread Spectrum
2773                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
2774   IN BOOLEAN    CfgExternalVrefCtlFeature;        ///< External Vref control
2775   IN FORCE_TRAIN_MODE   CfgForceTrainMode;        ///< Force Train Mode
2776   IN BOOLEAN    CfgGnbRemoteDisplaySupport;       ///< Wireless Display Support
2777   IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList;
2778   IN BOOLEAN Reserved;                            ///< reserved...
2779 } BUILD_OPT_CFG;
2780
2781 ///  A structure containing platform specific operational characteristics. This
2782 ///  structure is initially populated by the initializer with a copy of the same
2783 ///  structure that was created at build time using the build configuration controls.
2784 typedef struct _PLATFORM_CONFIGURATION {
2785   IN PERFORMANCE_PROFILE PlatformProfile;             ///< Several configuration settings for the processor.
2786   IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
2787                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
2788                                                       ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
2789   IN UINT8               CoreLevelingMode;            ///< Indicates how to balance the number of cores per processor.
2790                                                       ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
2791   IN PLATFORM_C1E_MODES  C1eMode;                     ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
2792                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
2793   IN UINT32              C1ePlatformData;             ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
2794                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
2795   IN UINT32              C1ePlatformData1;            ///< If C1eMode is SW, specifies the address of chipset's SMI command port.
2796                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1}
2797   IN UINT32              C1ePlatformData2;            ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
2798                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2}
2799   IN UINT32              C1ePlatformData3;            ///< If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e
2800                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA3}
2801   IN PLATFORM_CSTATE_MODES  CStateMode;               ///< Specifies the method of C-State enablement - Disabled, or C6.
2802                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
2803   IN UINT32              CStatePlatformData;          ///< This element specifies some pertinent data needed for the operation of the Cstate feature
2804                                                       ///< If CStateMode is CStateModeC6, this item is reserved
2805                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
2806   IN UINT16              CStateIoBaseAddress;         ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
2807                                                       ///< can be used to allow the CPU to enter Cstates.
2808                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
2809   IN PLATFORM_CPB_MODES  CpbMode;                     ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
2810                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
2811   IN BOOLEAN             UserOptionDmi;               ///< When set to TRUE, the DMI data table is generated.
2812   IN BOOLEAN             UserOptionPState;            ///< When set to TRUE, the PState data tables are generated.
2813   IN BOOLEAN             UserOptionSrat;              ///< When set to TRUE, the SRAT data table is generated.
2814   IN BOOLEAN             UserOptionSlit;              ///< When set to TRUE, the SLIT data table is generated.
2815   IN BOOLEAN             UserOptionWhea;              ///< When set to TRUE, the WHEA data table is generated.
2816   IN PLATFORM_LOW_POWER_PSTATE_MODES  LowPowerPstateForProcHot; ///< Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
2817   IN UINT32              PowerCeiling;                ///< P-State Ceiling Enabling Deck - Max power milli-watts.
2818   IN BOOLEAN             ForcePstateIndependent;      ///< P-State _PSD independence or dependence.
2819                                                       ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
2820   IN BOOLEAN             PStatesInHpcMode;            ///< @BldCfgItem{BLDCFG_PSTATE_HPC_MODE}
2821   IN UINT32              NumberOfIoApics;             ///< Number of I/O APICs in the system
2822                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
2823   IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
2824   IN BOOLEAN             ProcessorScopeInSb;          ///< ACPI Processor Object in \\_SB scope
2825                                                       ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
2826   IN CHAR8               ProcessorScopeName0;         ///< OEM specific 1st character of processor scope name.
2827                                                       ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
2828   IN CHAR8               ProcessorScopeName1;         ///< OEM specific 2nd character of processor scope name.
2829                                                       ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
2830   IN UINT8               GnbHdAudio;                  ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
2831                                                       ///< essentially it enables function 1 of graphics device.
2832                                                       ///< @li 0 = HD Audio disable
2833                                                       ///< @li 1 = HD Audio enable
2834                                                       ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
2835   IN UINT8               AbmSupport;                  ///< Automatic adjust LVDS/eDP Back light level support.It is
2836                                                       ///< characteristic specific to display panel which used by platform design.
2837                                                       ///< @li 0 = ABM support disabled
2838                                                       ///< @li 1 = ABM support enabled
2839                                                       ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
2840   IN UINT8               DynamicRefreshRate;          ///< Adjust refresh rate on LVDS/eDP.
2841                                                       ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
2842   IN UINT16              LcdBackLightControl;         ///< The PWM frequency to LCD backlight control.
2843                                                       ///< If equal to 0 backlight not controlled by iGPU
2844                                                       ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
2845 } PLATFORM_CONFIGURATION;
2846
2847
2848 /**********************************************************************
2849  * Structures for: AmdInitLate
2850  **********************************************************************/
2851 #define PROC_VERSION_LENGTH 48
2852 #define MAX_DIMMS_PER_SOCKET 16
2853
2854 /*  Interface Parameter Structures  */
2855 /// DMI Type4 - Processor ID
2856 typedef struct {
2857   OUT UINT32                    ProcIdLsd;              ///< Lower half of 64b ID
2858   OUT UINT32                    ProcIdMsd;              ///< Upper half of 64b ID
2859 } TYPE4_PROC_ID;
2860
2861 /// DMI Type 4 - Processor information
2862 typedef struct {
2863   OUT UINT8                     T4ProcType;             ///< CPU Type
2864   OUT UINT8                     T4ProcFamily;           ///< Family 1
2865   OUT TYPE4_PROC_ID             T4ProcId;               ///< Id
2866   OUT UINT8                     T4Voltage;              ///< Voltage
2867   OUT UINT16                    T4ExternalClock;        ///< External clock
2868   OUT UINT16                    T4MaxSpeed;             ///< Max speed
2869   OUT UINT16                    T4CurrentSpeed;         ///< Current speed
2870   OUT UINT8                     T4Status;               ///< Status
2871   OUT UINT8                     T4ProcUpgrade;          ///< Up grade
2872   OUT UINT8                     T4CoreCount;            ///< Core count
2873   OUT UINT8                     T4CoreEnabled;          ///< Core Enable
2874   OUT UINT8                     T4ThreadCount;          ///< Thread count
2875   OUT UINT16                    T4ProcCharacteristics;  ///< Characteristics
2876   OUT UINT16                    T4ProcFamily2;          ///< Family 2
2877   OUT CHAR8                     T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
2878 } TYPE4_DMI_INFO;
2879
2880 /// DMI Type 7 - Cache information
2881 typedef struct _TYPE7_DMI_INFO {
2882   OUT UINT16                    T7CacheCfg;             ///< Cache cfg
2883   OUT UINT16                    T7MaxCacheSize;         ///< Max size
2884   OUT UINT16                    T7InstallSize;          ///< Install size
2885   OUT UINT16                    T7SupportedSramType;    ///< Supported Sram Type
2886   OUT UINT16                    T7CurrentSramType;      ///< Current type
2887   OUT UINT8                     T7CacheSpeed;           ///< Speed
2888   OUT UINT8                     T7ErrorCorrectionType;  ///< ECC type
2889   OUT UINT8                     T7SystemCacheType;      ///< Cache type
2890   OUT UINT8                     T7Associativity;        ///< Associativity
2891 } TYPE7_DMI_INFO;
2892
2893 /// DMI Type 16 offset 04h - Location
2894 typedef enum {
2895   OtherLocation = 0x01,                                 ///< Assign 01 to Other
2896   UnknownLocation,                                      ///< Assign 02 to Unknown
2897   SystemboardOrMotherboard,                             ///< Assign 03 to systemboard or motherboard
2898   IsaAddonCard,                                         ///< Assign 04 to ISA add-on card
2899   EisaAddonCard,                                        ///< Assign 05 to EISA add-on card
2900   PciAddonCard,                                         ///< Assign 06 to PCI add-on card
2901   McaAddonCard,                                         ///< Assign 07 to MCA add-on card
2902   PcmciaAddonCard,                                      ///< Assign 08 to PCMCIA add-on card
2903   ProprietaryAddonCard,                                 ///< Assign 09 to proprietary add-on card
2904   NuBus,                                                ///< Assign 0A to NuBus
2905   Pc98C20AddonCard,                                     ///< Assign 0A0 to PC-98/C20 add-on card
2906   Pc98C24AddonCard,                                     ///< Assign 0A1 to PC-98/C24 add-on card
2907   Pc98EAddoncard,                                       ///< Assign 0A2 to PC-98/E add-on card
2908   Pc98LocalBusAddonCard                                 ///< Assign 0A3 to PC-98/Local bus add-on card
2909 } DMI_T16_LOCATION;
2910
2911 /// DMI Type 16 offset 05h - Memory Error Correction
2912 typedef enum {
2913   OtherUse = 0x01,                                      ///< Assign 01 to Other
2914   UnknownUse,                                           ///< Assign 02 to Unknown
2915   SystemMemory,                                         ///< Assign 03 to system memory
2916   VideoMemory,                                          ///< Assign 04 to video memory
2917   FlashMemory,                                          ///< Assign 05 to flash memory
2918   NonvolatileRam,                                       ///< Assign 06 to non-volatile RAM
2919   CacheMemory                                           ///< Assign 07 to cache memory
2920 } DMI_T16_USE;
2921
2922 /// DMI Type 16 offset 07h - Maximum Capacity
2923 typedef enum {
2924   Dmi16OtherErrCorrection = 0x01,                       ///< Assign 01 to Other
2925   Dmi16UnknownErrCorrection,                            ///< Assign 02 to Unknown
2926   Dmi16NoneErrCorrection,                               ///< Assign 03 to None
2927   Dmi16Parity,                                          ///< Assign 04 to parity
2928   Dmi16SingleBitEcc,                                    ///< Assign 05 to Single-bit ECC
2929   Dmi16MultiBitEcc,                                     ///< Assign 06 to Multi-bit ECC
2930   Dmi16Crc                                              ///< Assign 07 to CRC
2931 } DMI_T16_ERROR_CORRECTION;
2932
2933 /// DMI Type 16 - Physical Memory Array
2934 typedef struct {
2935   OUT DMI_T16_LOCATION          Location;               ///< The physical location of the Memory Array,
2936                                                         ///< whether on the system board or an add-in board.
2937   OUT DMI_T16_USE               Use;                    ///< Identifies the function for which the array
2938                                                         ///< is used.
2939   OUT DMI_T16_ERROR_CORRECTION  MemoryErrorCorrection;  ///< The primary hardware error correction or
2940                                                         ///< detection method supported by this memory array.
2941   OUT UINT32                    MaximumCapacity;        ///< The maximum memory capacity, in kilobytes,
2942                                                         ///< for the array.
2943   OUT UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available
2944                                                         ///< for memory devices in this array.
2945   OUT UINT64                    ExtMaxCapacity;         ///< The maximum memory capacity, in bytes,
2946                                                         ///< for this array.
2947 } TYPE16_DMI_INFO;
2948
2949 /// DMI Type 17 offset 0Eh - Form Factor
2950 typedef enum {
2951   OtherFormFactor = 0x01,                               ///< Assign 01 to Other
2952   UnknowFormFactor,                                     ///< Assign 02 to Unknown
2953   SimmFormFactor,                                       ///< Assign 03 to SIMM
2954   SipFormFactor,                                        ///< Assign 04 to SIP
2955   ChipFormFactor,                                       ///< Assign 05 to Chip
2956   DipFormFactor,                                        ///< Assign 06 to DIP
2957   ZipFormFactor,                                        ///< Assign 07 to ZIP
2958   ProprietaryCardFormFactor,                            ///< Assign 08 to Proprietary Card
2959   DimmFormFactorFormFactor,                             ///< Assign 09 to DIMM
2960   TsopFormFactor,                                       ///< Assign 10 to TSOP
2961   RowOfChipsFormFactor,                                 ///< Assign 11 to Row of chips
2962   RimmFormFactor,                                       ///< Assign 12 to RIMM
2963   SodimmFormFactor,                                     ///< Assign 13 to SODIMM
2964   SrimmFormFactor,                                      ///< Assign 14 to SRIMM
2965   FbDimmFormFactor                                      ///< Assign 15 to FB-DIMM
2966 } DMI_T17_FORM_FACTOR;
2967
2968 /// DMI Type 17 offset 12h - Memory Type
2969 typedef enum {
2970   OtherMemType = 0x01,                                  ///< Assign 01 to Other
2971   UnknownMemType,                                       ///< Assign 02 to Unknown
2972   DramMemType,                                          ///< Assign 03 to DRAM
2973   EdramMemType,                                         ///< Assign 04 to EDRAM
2974   VramMemType,                                          ///< Assign 05 to VRAM
2975   SramMemType,                                          ///< Assign 06 to SRAM
2976   RamMemType,                                           ///< Assign 07 to RAM
2977   RomMemType,                                           ///< Assign 08 to ROM
2978   FlashMemType,                                         ///< Assign 09 to Flash
2979   EepromMemType,                                        ///< Assign 10 to EEPROM
2980   FepromMemType,                                        ///< Assign 11 to FEPROM
2981   EpromMemType,                                         ///< Assign 12 to EPROM
2982   CdramMemType,                                         ///< Assign 13 to CDRAM
2983   ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
2984   SdramMemType,                                         ///< Assign 15 to SDRAM
2985   SgramMemType,                                         ///< Assign 16 to SGRAM
2986   RdramMemType,                                         ///< Assign 17 to RDRAM
2987   DdrMemType,                                           ///< Assign 18 to DDR
2988   Ddr2MemType,                                          ///< Assign 19 to DDR2
2989   Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
2990   Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
2991   Fbd2MemType                                           ///< Assign 25 to FBD2
2992 } DMI_T17_MEMORY_TYPE;
2993
2994 /// DMI Type 17 offset 13h - Type Detail
2995 typedef struct {
2996   OUT UINT16                    Reserved1:1;            ///< Reserved
2997   OUT UINT16                    Other:1;                ///< Other
2998   OUT UINT16                    Unknown:1;              ///< Unknown
2999   OUT UINT16                    FastPaged:1;            ///< Fast-Paged
3000   OUT UINT16                    StaticColumn:1;         ///< Static column
3001   OUT UINT16                    PseudoStatic:1;         ///< Pseudo-static
3002   OUT UINT16                    Rambus:1;               ///< RAMBUS
3003   OUT UINT16                    Synchronous:1;          ///< Synchronous
3004   OUT UINT16                    Cmos:1;                 ///< CMOS
3005   OUT UINT16                    Edo:1;                  ///< EDO
3006   OUT UINT16                    WindowDram:1;           ///< Window DRAM
3007   OUT UINT16                    CacheDram:1;            ///< Cache Dram
3008   OUT UINT16                    NonVolatile:1;          ///< Non-volatile
3009   OUT UINT16                    Reserved2:3;            ///< Reserved
3010 } DMI_T17_TYPE_DETAIL;
3011
3012 /// DMI Type 17 - Memory Device
3013 typedef struct {
3014   OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
3015   OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
3016   OUT UINT16                    MemorySize;             ///< The size of the memory device.
3017   OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
3018   OUT UINT8                     DeviceSet;              ///< Identifies when the Memory Device is one of a set of
3019                                                         ///< Memory Devices that must be populated with all devices of
3020                                                         ///< the same type and size, and the set to which this device belongs.
3021   OUT CHAR8                     DeviceLocator[8];       ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
3022   OUT CHAR8                     BankLocator[10];        ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
3023   OUT DMI_T17_MEMORY_TYPE       MemoryType;             ///< The type of memory used in this device.
3024   OUT DMI_T17_TYPE_DETAIL       TypeDetail;             ///< Additional detail on the memory device type
3025   OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
3026   OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
3027   OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
3028   OUT CHAR8                     PartNumber[19];         ///< Part Number.
3029   OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
3030   OUT UINT32                    ExtSize;                ///< Extended Size.
3031   OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
3032 } TYPE17_DMI_INFO;
3033
3034 /// Memory DMI Type 17 and 20 - for memory use
3035 typedef struct {
3036   OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
3037   OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
3038   OUT UINT16                    MemorySize;             ///< The size of the memory device.
3039   OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
3040   OUT UINT8                     DeviceLocator;          ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
3041   OUT UINT8                     BankLocator;            ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
3042   OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
3043   OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
3044   OUT UINT8                     SerialNumber[4];        ///< Serial Number.
3045   OUT UINT8                     PartNumber[18];         ///< Part Number.
3046   OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
3047   OUT UINT32                    ExtSize;                ///< Extended Size.
3048   OUT UINT8                     Socket:3;               ///< Socket ID
3049   OUT UINT8                     Channel:2;              ///< Channel ID
3050   OUT UINT8                     Dimm:2;                 ///< DIMM ID
3051   OUT UINT8                     DimmPresent:1;          ///< Dimm Present
3052   OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
3053                                                         ///< of memory mapped to the referenced Memory Device.
3054   OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
3055                                                         ///< the Memory Device structure to which this address
3056                                                         ///< range is mapped.
3057   OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
3058   OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
3059                                                         ///< memory mapped to the referenced Memory Device.
3060   OUT UINT64                    ExtEndingAddr;          ///< The physical ending address, in bytes, of the last of
3061                                                         ///< a range of addresses mapped to the referenced Memory Device.
3062 } MEM_DMI_INFO;
3063
3064 /// DMI Type 19 - Memory Array Mapped Address
3065 typedef struct {
3066   OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
3067                                                         ///< of a range of memory mapped to the
3068                                                         ///< specified physical memory array.
3069   OUT UINT32                    EndingAddr;             ///< The physical ending address of the
3070                                                         ///< last kilobyte of a range of addresses
3071                                                         ///< mapped to the specified physical memory array.
3072   OUT UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
3073                                                         ///< with the physical memory array to which this
3074                                                         ///< address range is mapped.
3075   OUT UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
3076                                                         ///< form a single row of memory for the address
3077                                                         ///< partition defined by this structure.
3078   OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
3079                                                         ///< memory mapped to the specified Physical Memory Array.
3080   OUT UINT64                    ExtEndingAddr;          ///< The physical address, in bytes, of a range of
3081                                                         ///< memory mapped to the specified Physical Memory Array.
3082 } TYPE19_DMI_INFO;
3083
3084 ///DMI Type 20 - Memory Device Mapped Address
3085 typedef struct {
3086   OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
3087                                                         ///< of memory mapped to the referenced Memory Device.
3088   OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
3089                                                         ///< the Memory Device structure to which this address
3090                                                         ///< range is mapped.
3091   OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
3092                                                         ///< the Memory Device structure to which this address
3093                                                         ///< range is mapped.
3094   OUT UINT16                    MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
3095                                                         ///< with the Memory Array Mapped Address structure to
3096                                                         ///< which this device address range is mapped.
3097   OUT UINT8                     PartitionRowPosition;   ///< Identifies the position of the referenced Memory
3098                                                         ///< Device in a row of the address partition.
3099   OUT UINT8                     InterleavePosition;     ///< The position of the referenced Memory Device in
3100                                                         ///< an interleave.
3101   OUT UINT8                     InterleavedDataDepth;   ///< The maximum number of consecutive rows from the
3102                                                         ///< referenced Memory Device that are accessed in a
3103                                                         ///< single interleaved transfer.
3104   OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
3105                                                         ///< memory mapped to the referenced Memory Device.
3106   OUT UINT64                    ExtEndingAddr;          ///< The physical ending address, in bytes, of the last of
3107                                                         ///< a range of addresses mapped to the referenced Memory Device.
3108 } TYPE20_DMI_INFO;
3109
3110 /// Collection of pointers to the DMI records
3111 typedef struct {
3112   OUT TYPE4_DMI_INFO            T4[MAX_SOCKETS_SUPPORTED];    ///< Type 4 struc
3113   OUT TYPE7_DMI_INFO            T7L1[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 1
3114   OUT TYPE7_DMI_INFO            T7L2[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 2
3115   OUT TYPE7_DMI_INFO            T7L3[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 3
3116   OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
3117   OUT TYPE17_DMI_INFO           T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
3118   OUT TYPE19_DMI_INFO           T19;                          ///< Type 19 struc
3119   OUT TYPE20_DMI_INFO           T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
3120 } DMI_INFO;
3121
3122 /**********************************************************************
3123  * Interface call:  AllocateExecutionCache
3124  **********************************************************************/
3125 #define MAX_CACHE_REGIONS    3
3126
3127 /// AllocateExecutionCache sub param structure for cached memory region
3128 typedef struct {
3129   IN OUT   UINT32               ExeCacheStartAddr;      ///< Start address
3130   IN OUT   UINT32               ExeCacheSize;           ///< Size
3131 } EXECUTION_CACHE_REGION;
3132
3133 /**********************************************************************
3134  * Interface call:  AmdGetAvailableExeCacheSize
3135  **********************************************************************/
3136 /// Get available Cache remain
3137 typedef struct {
3138   IN OUT   AMD_CONFIG_PARAMS    StdHeader;              ///< Standard configuration header
3139      OUT   UINT32               AvailableExeCacheSize;  ///< Remain size
3140 } AMD_GET_EXE_SIZE_PARAMS;
3141
3142 AGESA_STATUS
3143 AmdGetAvailableExeCacheSize (
3144   IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
3145   );
3146
3147 /// Selection type for core leveling
3148 typedef enum {
3149   CORE_LEVEL_LOWEST,            ///< Level to lowest common denominator
3150   CORE_LEVEL_TWO,               ///< Level to 2 cores
3151   CORE_LEVEL_POWER_OF_TWO,      ///< Level to 1,2,4 or 8
3152   CORE_LEVEL_NONE,              ///< Do no leveling
3153   CORE_LEVEL_COMPUTE_UNIT,      ///< Level cores to one core per compute unit
3154   CORE_LEVEL_ONE,               ///< Level to 1 core
3155   CORE_LEVEL_THREE,             ///< Level to 3 cores
3156   CORE_LEVEL_FOUR,              ///< Level to 4 cores
3157   CORE_LEVEL_FIVE,              ///< Level to 5 cores
3158   CORE_LEVEL_SIX,               ///< Level to 6 cores
3159   CORE_LEVEL_SEVEN,             ///< Level to 7 cores
3160   CORE_LEVEL_EIGHT,             ///< Level to 8 cores
3161   CORE_LEVEL_NINE,              ///< Level to 9 cores
3162   CORE_LEVEL_TEN,               ///< Level to 10 cores
3163   CORE_LEVEL_ELEVEN,            ///< Level to 11 cores
3164   CORE_LEVEL_TWELVE,            ///< Level to 12 cores
3165   CORE_LEVEL_THIRTEEN,          ///< Level to 13 cores
3166   CORE_LEVEL_FOURTEEN,          ///< Level to 14 cores
3167   CORE_LEVEL_FIFTEEN,           ///< Level to 15 cores
3168   CoreLevelModeMax              ///< Used for bounds checking
3169 } CORE_LEVELING_TYPE;
3170
3171
3172
3173
3174
3175 /************************************************************************
3176  *
3177  *  AGESA Basic Level interface structure definition and function prototypes
3178  *
3179  ***********************************************************************/
3180
3181 /**********************************************************************
3182  * Interface call:  AmdCreateStruct
3183  **********************************************************************/
3184 AGESA_STATUS
3185 AmdCreateStruct (
3186   IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
3187   );
3188
3189 /**********************************************************************
3190  * Interface call:  AmdReleaseStruct
3191  **********************************************************************/
3192 AGESA_STATUS
3193 AmdReleaseStruct (
3194   IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
3195   );
3196
3197 /**********************************************************************
3198  * Interface call:  AmdInitReset
3199  **********************************************************************/
3200 /// AmdInitReset param structure
3201 typedef struct {
3202   IN       AMD_CONFIG_PARAMS         StdHeader;        ///< Standard configuration header
3203   IN       EXECUTION_CACHE_REGION    CacheRegion[3];   ///< The cached memory region
3204   IN       AMD_HT_RESET_INTERFACE    HtConfig;         ///< The interface for Ht Recovery
3205   IN       FCH_RESET_INTERFACE       FchInterface;     ///< Interface for FCH configuration
3206 } AMD_RESET_PARAMS;
3207
3208 AGESA_STATUS
3209 AmdInitReset (
3210   IN OUT   AMD_RESET_PARAMS     *ResetParams
3211   );
3212
3213
3214 /**********************************************************************
3215  * Interface call:  AmdInitEarly
3216  **********************************************************************/
3217 /// InitEarly param structure
3218 ///
3219 /// Provide defaults or customizations to each service performed in AmdInitEarly.
3220 ///
3221 typedef struct {
3222   IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
3223   IN       EXECUTION_CACHE_REGION CacheRegion[3];   ///< Execution Map Interface
3224   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
3225   IN       AMD_HT_INTERFACE       HtConfig;         ///< HyperTransport Interface
3226   IN       GNB_CONFIGURATION      GnbConfig;        ///< GNB configuration
3227 } AMD_EARLY_PARAMS;
3228
3229 AGESA_STATUS
3230 AmdInitEarly (
3231   IN OUT   AMD_EARLY_PARAMS     *EarlyParams
3232   );
3233
3234
3235 /**********************************************************************
3236  * Interface call:  AmdInitPost
3237  **********************************************************************/
3238 /// AmdInitPost param structure
3239 typedef struct {
3240   IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
3241   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
3242   IN       MEM_PARAMETER_STRUCT   MemConfig;        ///< Memory post param
3243 } AMD_POST_PARAMS;
3244
3245 AGESA_STATUS
3246 AmdInitPost (
3247   IN OUT   AMD_POST_PARAMS      *PostParams         ///< Amd Cpu init param
3248   );
3249
3250
3251 /**********************************************************************
3252  * Interface call:  AmdInitEnv
3253  **********************************************************************/
3254 /// AmdInitEnv param structure
3255 typedef struct {
3256   IN OUT   AMD_CONFIG_PARAMS      StdHeader;            ///< Standard configuration header
3257   IN       PLATFORM_CONFIGURATION PlatformConfig;       ///< platform operational characteristics.
3258   IN       GNB_ENV_CONFIGURATION  GnbEnvConfiguration;  ///< platform operational characteristics.
3259   IN       FCH_INTERFACE          FchInterface;         ///< FCH configuration
3260 } AMD_ENV_PARAMS;
3261
3262 AGESA_STATUS
3263 AmdInitEnv (
3264   IN OUT   AMD_ENV_PARAMS       *EnvParams
3265   );
3266
3267
3268 /**********************************************************************
3269  * Interface call:  AmdInitMid
3270  **********************************************************************/
3271 /// AmdInitMid param structure
3272 typedef struct {
3273   IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
3274   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
3275   IN       FCH_INTERFACE          FchInterface;     ///< FCH configuration
3276 } AMD_MID_PARAMS;
3277
3278 AGESA_STATUS
3279 AmdInitMid (
3280   IN OUT   AMD_MID_PARAMS       *MidParams
3281   );
3282
3283
3284 /**********************************************************************
3285  * Interface call:  AmdInitLate
3286  **********************************************************************/
3287 /// AmdInitLate param structure
3288 typedef struct {
3289   IN OUT   AMD_CONFIG_PARAMS      StdHeader;              ///< Standard configuration header
3290   IN       PLATFORM_CONFIGURATION PlatformConfig;         ///< platform operational characteristics.
3291   IN       IOMMU_EXCLUSION_RANGE_DESCRIPTOR  *IvrsExclusionRangeList;   ///< Pointer to array of exclusion ranges
3292      OUT   DMI_INFO               *DmiTable;              ///< DMI Interface
3293      OUT   VOID                   *AcpiPState;            ///< Acpi Pstate SSDT Table
3294      OUT   VOID                   *AcpiSrat;              ///< SRAT Table
3295      OUT   VOID                   *AcpiSlit;              ///< SLIT Table
3296      OUT   VOID                   *AcpiWheaMce;           ///< WHEA MCE Table
3297      OUT   VOID                   *AcpiWheaCmc;           ///< WHEA CMC Table
3298      OUT   VOID                   *AcpiAlib;              ///< ACPI SSDT table with ALIB implementation
3299      OUT   VOID                   *AcpiIvrs;              ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
3300 } AMD_LATE_PARAMS;
3301
3302 AGESA_STATUS
3303 AmdInitLate (
3304   IN OUT   AMD_LATE_PARAMS      *LateParams
3305   );
3306
3307 /**********************************************************************
3308  * Interface call:  AmdInitRecovery
3309  **********************************************************************/
3310 /// CPU Recovery Parameters
3311 typedef struct {
3312   IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
3313   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
3314 } AMD_CPU_RECOVERY_PARAMS;
3315
3316 /// AmdInitRecovery param structure
3317 typedef struct {
3318   IN OUT   AMD_CONFIG_PARAMS        StdHeader;            ///< Standard configuration header
3319   IN       MEM_PARAMETER_STRUCT     MemConfig;            ///< Memory post param
3320   IN       EXECUTION_CACHE_REGION   CacheRegion[3];       ///< The cached memory region. And the max cache region is 3
3321   IN       AMD_CPU_RECOVERY_PARAMS  CpuRecoveryParams;    ///< Params for CPU related recovery init.
3322 } AMD_RECOVERY_PARAMS;
3323
3324 AGESA_STATUS
3325 AmdInitRecovery (
3326   IN OUT   AMD_RECOVERY_PARAMS    *RecoveryParams
3327   );
3328
3329 /**********************************************************************
3330  * Interface call:  AmdInitResume
3331  **********************************************************************/
3332 /// AmdInitResume param structure
3333 typedef struct {
3334   IN OUT   AMD_CONFIG_PARAMS      StdHeader;      ///< Standard configuration header
3335   IN       PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
3336   IN       AMD_S3_PARAMS          S3DataBlock;    ///< Save state data
3337 } AMD_RESUME_PARAMS;
3338
3339 AGESA_STATUS
3340 AmdInitResume (
3341   IN       AMD_RESUME_PARAMS    *ResumeParams
3342   );
3343
3344
3345 /**********************************************************************
3346  * Interface call:  AmdS3LateRestore
3347  **********************************************************************/
3348 /// AmdS3LateRestore param structure
3349 typedef struct {
3350   IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
3351   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
3352   IN       AMD_S3_PARAMS          S3DataBlock;      ///< Save state data
3353 } AMD_S3LATE_PARAMS;
3354
3355 AGESA_STATUS
3356 AmdS3LateRestore (
3357   IN OUT   AMD_S3LATE_PARAMS    *S3LateParams
3358   );
3359
3360
3361 /**********************************************************************
3362  * Interface call:  AmdS3Save
3363  **********************************************************************/
3364 /// AmdS3Save param structure
3365 typedef struct {
3366   IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
3367   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
3368      OUT   AMD_S3_PARAMS          S3DataBlock;      ///< Standard header
3369   IN       FCH_INTERFACE          FchInterface;     ///< FCH configuration
3370 } AMD_S3SAVE_PARAMS;
3371
3372 AGESA_STATUS
3373 AmdS3Save (
3374   IN OUT   AMD_S3SAVE_PARAMS    *AmdS3SaveParams
3375   );
3376
3377
3378 /**********************************************************************
3379  * Interface call:  AmdLateRunApTask
3380  **********************************************************************/
3381 /**
3382  * Entry point for AP tasking.
3383  */
3384 AGESA_STATUS
3385 AmdLateRunApTask (
3386   IN       AP_EXE_PARAMS  *AmdApExeParams
3387 );
3388
3389 //
3390 // General Services API
3391 //
3392
3393 /**********************************************************************
3394  * Interface service call:  AmdGetApicId
3395  **********************************************************************/
3396 /// Request the APIC ID of a particular core.
3397
3398 typedef struct {
3399   IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
3400   IN       UINT8             Socket;           ///< The Core's Socket.
3401   IN       UINT8             Core;             ///< The Core id.
3402      OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  ApicAddress is valid.
3403      OUT   UINT8             ApicAddress;      ///< The Core's APIC ID.
3404 } AMD_APIC_PARAMS;
3405
3406 /**
3407  * Get a specified Core's APIC ID.
3408  */
3409 AGESA_STATUS
3410 AmdGetApicId (
3411   IN OUT AMD_APIC_PARAMS *AmdParamApic
3412 );
3413
3414 /**********************************************************************
3415  * Interface service call:  AmdGetPciAddress
3416  **********************************************************************/
3417 /// Request the PCI Address of a Processor Module (that is, its Northbridge)
3418
3419 typedef struct {
3420   IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
3421   IN       UINT8             Socket;           ///< The Processor's socket
3422   IN       UINT8             Module;           ///< The Module in that Processor
3423      OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  PciAddress is valid.
3424      OUT   PCI_ADDR          PciAddress;       ///< The Processor's PCI Config Space address (Function 0, Register 0)
3425 } AMD_GET_PCI_PARAMS;
3426
3427 /**
3428  * Get Processor Module's PCI Config Space address.
3429  */
3430 AGESA_STATUS
3431 AmdGetPciAddress (
3432   IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
3433 );
3434
3435 /**********************************************************************
3436  * Interface service call:  AmdIdentifyCore
3437  **********************************************************************/
3438 /// Request the identity (Socket, Module, Core) of the current Processor Core
3439
3440 typedef struct {
3441   IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
3442      OUT   UINT8             Socket;            ///< The current Core's Socket
3443      OUT   UINT8             Module;            ///< The current Core's Processor Module
3444      OUT   UINT8             Core;              ///< The current Core's core id.
3445 } AMD_IDENTIFY_PARAMS;
3446
3447 /**
3448  * "Who am I" for the current running core.
3449  */
3450 AGESA_STATUS
3451 AmdIdentifyCore (
3452   IN OUT  AMD_IDENTIFY_PARAMS *AmdParamIdentify
3453 );
3454
3455 /**********************************************************************
3456  * Interface service call:  AmdReadEventLog
3457  **********************************************************************/
3458 /// An Event Log Entry.
3459 typedef struct {
3460   IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
3461      OUT   UINT32            EventClass;        ///< The severity of this event, matches AGESA_STATUS.
3462      OUT   UINT32            EventInfo;         ///< The unique event identifier, zero means "no event".
3463      OUT   UINT32            DataParam1;        ///< Data specific to the Event.
3464      OUT   UINT32            DataParam2;        ///< Data specific to the Event.
3465      OUT   UINT32            DataParam3;        ///< Data specific to the Event.
3466      OUT   UINT32            DataParam4;        ///< Data specific to the Event.
3467 } EVENT_PARAMS;
3468
3469 /**
3470  * Read an Event from the Event Log.
3471  */
3472 AGESA_STATUS
3473 AmdReadEventLog (
3474   IN       EVENT_PARAMS *Event
3475 );
3476
3477 /**********************************************************************
3478  * Interface service call:  AmdIdentifyDimm
3479  **********************************************************************/
3480 /// Request the identity of dimm from system address
3481
3482 typedef struct {
3483   IN OUT   AMD_CONFIG_PARAMS StdHeader;            ///< Standard configuration header
3484   IN       UINT64            MemoryAddress;        ///< System Address that needs to be translated to dimm identification.
3485   OUT      UINT8             SocketId;             ///< The socket on which the targeted address locates.
3486   OUT      UINT8             MemChannelId;         ///< The channel on which the targeted address locates.
3487   OUT      UINT8             DimmId;               ///< The dimm on which the targeted address locates.
3488 } AMD_IDENTIFY_DIMM;
3489
3490 /**
3491  * Get the dimm identification for the address.
3492  */
3493 AGESA_STATUS
3494 AmdIdentifyDimm (
3495   IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
3496 );
3497
3498 AGESA_STATUS
3499 AmdIdsRunApTaskLate (
3500   IN       AP_EXE_PARAMS  *AmdApExeParams
3501   );
3502
3503
3504 #define AGESA_IDS_DFT_VAL   0xFFFF                  ///<  Default value of every uninitlized NV item, the action for it will be ignored
3505 #define AGESA_IDS_NV_END    0xFFFF                  ///< Flag specify end of option structure
3506 /// WARNING: Don't change the comment below, it used as signature for script
3507 /// AGESA IDS NV ID Definitions
3508 typedef enum {
3509   AGESA_IDS_EXT_ID_START                   = 0x0000,///< 0x0000                                                             specify the start of external NV id
3510
3511   AGESA_IDS_NV_UCODE,                               ///< 0x0001                                                            Enable or disable microcode patching
3512
3513   AGESA_IDS_NV_TARGET_PSTATE,                       ///< 0x0002                                                        Set the P-state required to be activated
3514   AGESA_IDS_NV_POSTPSTATE,                          ///< 0x0003                                           Set the P-state required to be activated through POST
3515
3516   AGESA_IDS_NV_BANK_INTERLEAVE,                     ///< 0x0004                                                               Enable or disable Bank Interleave
3517   AGESA_IDS_NV_CHANNEL_INTERLEAVE,                  ///< 0x0005                                                            Enable or disable Channel Interleave
3518   AGESA_IDS_NV_NODE_INTERLEAVE,                     ///< 0x0006                                                               Enable or disable Node Interleave
3519   AGESA_IDS_NV_MEMHOLE,                             ///< 0x0007                                                                  Enables or disable memory hole
3520
3521   AGESA_IDS_NV_SCRUB_REDIRECTION,                   ///< 0x0008                                           Enable or disable a write to dram with corrected data
3522   AGESA_IDS_NV_DRAM_SCRUB,                          ///< 0x0009                                                   Set the rate of background scrubbing for DRAM
3523   AGESA_IDS_NV_DCACHE_SCRUB,                        ///< 0x000A                                            Set the rate of background scrubbing for the DCache.
3524   AGESA_IDS_NV_L2_SCRUB,                            ///< 0x000B                                           Set the rate of background scrubbing for the L2 cache
3525   AGESA_IDS_NV_L3_SCRUB,                            ///< 0x000C                                           Set the rate of background scrubbing for the L3 cache
3526   AGESA_IDS_NV_ICACHE_SCRUB,                        ///< 0x000D                                             Set the rate of background scrubbing for the Icache
3527   AGESA_IDS_NV_SYNC_ON_ECC_ERROR,                   ///< 0x000E                                    Enable or disable the sync flood on un-correctable ECC error
3528   AGESA_IDS_NV_ECC_SYMBOL_SIZE,                     ///< 0x000F                                                                             Set ECC symbol size
3529
3530   AGESA_IDS_NV_ALL_MEMCLKS,                         ///< 0x0010                                                      Enable or disable all memory clocks enable
3531   AGESA_IDS_NV_DCT_GANGING_MODE,                    ///< 0x0011                                                                             Set the Ganged mode
3532   AGESA_IDS_NV_DRAM_BURST_LENGTH32,                 ///< 0x0012                                                                    Set the DRAM Burst Length 32
3533   AGESA_IDS_NV_MEMORY_POWER_DOWN,                   ///< 0x0013                                                        Enable or disable Memory power down mode
3534   AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE,              ///< 0x0014                                                                  Set the Memory power down mode
3535   AGESA_IDS_NV_DLL_SHUT_DOWN,                       ///< 0x0015                                                                   Enable or disable DLLShutdown
3536   AGESA_IDS_NV_ONLINE_SPARE,                        ///< 0x0016      Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
3537
3538   AGESA_IDS_NV_HT_ASSIST,                           ///< 0x0017                                                                     Enable or Disable HT Assist
3539   AGESA_IDS_NV_ATMMODE,                             ///< 0x0018                                                                      Enable or Disable ATM mode
3540
3541   AGESA_IDS_NV_HDTOUT,                              ///< 0x0019                                                                Enable or disable HDTOUT feature
3542
3543   AGESA_IDS_NV_HTLINKSOCKET,                        ///< 0x001A                                                                                  HT Link Socket
3544   AGESA_IDS_NV_HTLINKPORT,                          ///< 0x001B                                                                                    HT Link Port
3545   AGESA_IDS_NV_HTLINKFREQ,                          ///< 0x001C                                                                               HT Link Frequency
3546   AGESA_IDS_NV_HTLINKWIDTHIN,                       ///< 0x001D                                                                                HT Link In Width
3547   AGESA_IDS_NV_HTLINKWIDTHOUT,                      ///< 0x001E                                                                               HT Link Out Width
3548
3549   AGESA_IDS_NV_GNBHDAUDIOEN,                        ///< 0x001F                                                                  Enable or disable GNB HD Audio
3550
3551   AGESA_IDS_NV_CPB_EN,                              ///< 0x0020                                                                          Core Performance Boost
3552
3553   AGESA_IDS_NV_HTC_EN,                              ///< 0x0021                                                                                      HTC Enable
3554   AGESA_IDS_NV_HTC_OVERRIDE,                        ///< 0x0022                                                                                    HTC Override
3555   AGESA_IDS_NV_HTC_PSTATE_LIMIT,                    ///< 0x0023                                                                        HTC P-state limit select
3556   AGESA_IDS_NV_HTC_TEMP_HYS,                        ///< 0x0024                                                                      HTC Temperature Hysteresis
3557   AGESA_IDS_NV_HTC_ACT_TEMP,                        ///< 0x0025                                                                             HTC Activation Temp
3558
3559   AGESA_IDS_NV_POWER_POLICY,                        ///< 0x0026                                                                    Select Platform Power Policy
3560   AGESA_IDS_EXT_ID_END,                             ///< 0x0027                                                               specify the end of external NV ID
3561 } IDS_EX_NV_ID;
3562
3563
3564 #define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
3565
3566 #endif // _AGESA_H_