src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * Install of build options for a combination of package type, processor, and features.
   6  *
   7  * This file generates the defaults tables for the all platform solution
   8  * combinations.  The documented build options are imported from a user
   9  * controlled file for processing.
  10  *
  11  * @xrefitem bom "File Content Label" "Release Content"
  12  * @e project:      AGESA
  13  * @e sub-project:  Core
  14  * @e \$Revision: 49633 $   @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
  15  */
  16 /*****************************************************************************
  17  *
  18  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  19  * All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions are met:
  23  *     * Redistributions of source code must retain the above copyright
  24  *       notice, this list of conditions and the following disclaimer.
  25  *     * Redistributions in binary form must reproduce the above copyright
  26  *       notice, this list of conditions and the following disclaimer in the
  27  *       documentation and/or other materials provided with the distribution.
  28  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  29  *       its contributors may be used to endorse or promote products derived
  30  *       from this software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  36  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  39  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  ***************************************************************************/
  44
  45 #ifndef RUN_BROKEN_AGESA_TESTS
  46         #define RUN_BROKEN_AGESA_TESTS 0
  47 #endif
  48
  49 /*****************************************************************************
  50  *
  51  * Start processing the user options:  First, set default settings
  52  *
  53  ****************************************************************************/
  54
  55 /* Available options for image builds.
  56  *
  57  * As part of the image build for each image, define the options below to select the
  58  * AGESA entry points included in that image.  Turn these on in your option c file, not
  59  * here.
  60  */
  61 // #define AGESA_ENTRY_INIT_RESET                    TRUE
  62 // #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
  63 // #define AGESA_ENTRY_INIT_EARLY                    TRUE
  64 // #define AGESA_ENTRY_INIT_POST                     TRUE
  65 // #define AGESA_ENTRY_INIT_ENV                      TRUE
  66 // #define AGESA_ENTRY_INIT_MID                      TRUE
  67 // #define AGESA_ENTRY_INIT_LATE                     TRUE
  68 // #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
  69 // #define AGESA_ENTRY_INIT_RESUME                   TRUE
  70 // #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
  71 // #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
  72
  73 /*  Defaults for private/internal build control settings  */
  74 /* Available options for image builds.
  75  *
  76  * As part of the image build for each image, define the options below to select the
  77  * AGESA entry points included in that image.
  78  */
  79
  80 VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
  81   //ModuleHeaderSignature
  82   // Remove 'DOM$' as temp solution before update BinUtil.exe ,
  83   Int32FromChar ('0', '0', '0', '0'),
  84   //ModuleIdentifier[8]
  85   AGESA_ID,
  86   //ModuleVersion[12]
  87   AGESA_VERSION_STRING,
  88   //ModuleDispatcher
  89   NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
  90   //NextBlock
  91   NULL
  92 };
  93
  94 /*  Process user desired AGESA entry points  */
  95 #ifndef AGESA_ENTRY_INIT_RESET
  96   #define AGESA_ENTRY_INIT_RESET                     FALSE
  97 #endif
  98
  99 #ifndef AGESA_ENTRY_INIT_RECOVERY
 100   #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
 101 #endif
 102
 103 #ifndef AGESA_ENTRY_INIT_EARLY
 104   #define AGESA_ENTRY_INIT_EARLY                     FALSE
 105 #endif
 106
 107 #ifndef AGESA_ENTRY_INIT_POST
 108   #define AGESA_ENTRY_INIT_POST                      FALSE
 109 #endif
 110
 111 #ifndef AGESA_ENTRY_INIT_ENV
 112   #define AGESA_ENTRY_INIT_ENV                       FALSE
 113 #endif
 114
 115 #ifndef AGESA_ENTRY_INIT_MID
 116   #define AGESA_ENTRY_INIT_MID                       FALSE
 117 #endif
 118
 119 #ifndef AGESA_ENTRY_INIT_LATE
 120   #define AGESA_ENTRY_INIT_LATE                      FALSE
 121 #endif
 122
 123 #ifndef AGESA_ENTRY_INIT_S3SAVE
 124   #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
 125 #endif
 126
 127 #ifndef AGESA_ENTRY_INIT_RESUME
 128   #define AGESA_ENTRY_INIT_RESUME                    FALSE
 129 #endif
 130
 131 #ifndef AGESA_ENTRY_INIT_LATE_RESTORE
 132   #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
 133 #endif
 134
 135 #ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
 136   #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
 137 #endif
 138
 139 /*  Default the late AP entry point to off.  It can be enabled
 140     by any family that may need the late AP functionality, or
 141     by any feature code that may need it.  The IBVs no longer
 142     have control over this entry point.  */
 143 #ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
 144   #undef AGESA_ENTRY_LATE_RUN_AP_TASK
 145 #endif
 146 #define AGESA_ENTRY_LATE_RUN_AP_TASK    FALSE
 147
 148
 149
 150 /* Process solution defined socket / family installations
 151  *
 152  * As part of the release package for each image, define the options below to select the
 153  * AGESA processor support included in that image.
 154  */
 155
 156 /*  Default sockets to off  */
 157 #define OPTION_G34_SOCKET_SUPPORT    FALSE
 158 #define OPTION_C32_SOCKET_SUPPORT    FALSE
 159 #define OPTION_S1G3_SOCKET_SUPPORT   FALSE
 160 #define OPTION_S1G4_SOCKET_SUPPORT   FALSE
 161 #define OPTION_ASB2_SOCKET_SUPPORT   FALSE
 162 #define OPTION_FS1_SOCKET_SUPPORT    FALSE
 163 #define OPTION_FM1_SOCKET_SUPPORT    FALSE
 164 #define OPTION_FP1_SOCKET_SUPPORT    FALSE
 165 #define OPTION_FT1_SOCKET_SUPPORT    FALSE
 166 #define OPTION_AM3_SOCKET_SUPPORT    FALSE
 167
 168 /*  Default families to off  */
 169 #define OPTION_FAMILY10H             FALSE
 170 #define OPTION_FAMILY12H             FALSE
 171 #define OPTION_FAMILY14H             FALSE
 172 #define OPTION_FAMILY15H             FALSE
 173
 174
 175 /*  Enable the appropriate socket support  */
 176 #ifdef INSTALL_G34_SOCKET_SUPPORT
 177   #if  INSTALL_G34_SOCKET_SUPPORT == TRUE
 178     #undef OPTION_G34_SOCKET_SUPPORT
 179     #define OPTION_G34_SOCKET_SUPPORT  TRUE
 180   #endif
 181 #endif
 182
 183 #ifdef INSTALL_C32_SOCKET_SUPPORT
 184   #if  INSTALL_C32_SOCKET_SUPPORT == TRUE
 185     #undef OPTION_C32_SOCKET_SUPPORT
 186     #define OPTION_C32_SOCKET_SUPPORT  TRUE
 187   #endif
 188 #endif
 189
 190 #ifdef INSTALL_S1G3_SOCKET_SUPPORT
 191   #if  INSTALL_S1G3_SOCKET_SUPPORT == TRUE
 192     #undef OPTION_S1G3_SOCKET_SUPPORT
 193     #define OPTION_S1G3_SOCKET_SUPPORT  TRUE
 194   #endif
 195 #endif
 196
 197 #ifdef INSTALL_S1G4_SOCKET_SUPPORT
 198   #if  INSTALL_S1G4_SOCKET_SUPPORT == TRUE
 199     #undef OPTION_S1G4_SOCKET_SUPPORT
 200     #define OPTION_S1G4_SOCKET_SUPPORT  TRUE
 201   #endif
 202 #endif
 203
 204 #ifdef INSTALL_ASB2_SOCKET_SUPPORT
 205   #if  INSTALL_ASB2_SOCKET_SUPPORT == TRUE
 206     #undef OPTION_ASB2_SOCKET_SUPPORT
 207     #define OPTION_ASB2_SOCKET_SUPPORT  TRUE
 208   #endif
 209 #endif
 210
 211 #ifdef INSTALL_FS1_SOCKET_SUPPORT
 212   #if  INSTALL_FS1_SOCKET_SUPPORT == TRUE
 213     #undef OPTION_FS1_SOCKET_SUPPORT
 214     #define OPTION_FS1_SOCKET_SUPPORT  TRUE
 215   #endif
 216 #endif
 217
 218 #ifdef INSTALL_FM1_SOCKET_SUPPORT
 219   #if  INSTALL_FM1_SOCKET_SUPPORT == TRUE
 220     #undef OPTION_FM1_SOCKET_SUPPORT
 221     #define OPTION_FM1_SOCKET_SUPPORT  TRUE
 222   #endif
 223 #endif
 224
 225 #ifdef INSTALL_FP1_SOCKET_SUPPORT
 226   #if  INSTALL_FP1_SOCKET_SUPPORT == TRUE
 227     #undef OPTION_FP1_SOCKET_SUPPORT
 228     #define OPTION_FP1_SOCKET_SUPPORT  TRUE
 229   #endif
 230 #endif
 231
 232 #ifdef INSTALL_FT1_SOCKET_SUPPORT
 233   #if  INSTALL_FT1_SOCKET_SUPPORT == TRUE
 234     #undef OPTION_FT1_SOCKET_SUPPORT
 235     #define OPTION_FT1_SOCKET_SUPPORT  TRUE
 236   #endif
 237 #endif
 238
 239 #ifdef INSTALL_AM3_SOCKET_SUPPORT
 240   #if  INSTALL_AM3_SOCKET_SUPPORT == TRUE
 241     #undef OPTION_AM3_SOCKET_SUPPORT
 242     #define OPTION_AM3_SOCKET_SUPPORT  TRUE
 243   #endif
 244 #endif
 245
 246
 247 /*  Enable the appropriate family support  */
 248 // F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
 249 #ifdef INSTALL_FAMILY_10_SUPPORT
 250   #if  INSTALL_FAMILY_10_SUPPORT == TRUE
 251     #undef OPTION_FAMILY10H
 252     #define OPTION_FAMILY10H     TRUE
 253   #endif
 254 #endif
 255
 256 // F12 is supported in FP1, FS1, & FM1
 257 #ifdef INSTALL_FAMILY_12_SUPPORT
 258   #if  INSTALL_FAMILY_12_SUPPORT == TRUE
 259     #undef OPTION_FAMILY12H
 260     #define OPTION_FAMILY12H     TRUE
 261   #endif
 262 #endif
 263
 264 // F14 is supported in FT1
 265 #ifdef INSTALL_FAMILY_14_SUPPORT
 266   #if  INSTALL_FAMILY_14_SUPPORT == TRUE
 267     #undef OPTION_FAMILY14H
 268     #define OPTION_FAMILY14H     TRUE
 269   #endif
 270 #endif
 271
 272 // F15 is supported in G34, C32, & AM3
 273 #ifdef INSTALL_FAMILY_15_SUPPORT
 274   #if  INSTALL_FAMILY_15_SUPPORT == TRUE
 275     #undef OPTION_FAMILY15H
 276     #define OPTION_FAMILY15H     TRUE
 277   #endif
 278 #endif
 279
 280
 281 /*  Turn off families not required by socket designations */
 282 #if (OPTION_FAMILY10H == TRUE)
 283   #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
 284     #undef OPTION_FAMILY10H
 285     #define OPTION_FAMILY10H  FALSE
 286   #endif
 287 #endif
 288
 289 #if (OPTION_FAMILY12H == TRUE)
 290   #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
 291     #undef OPTION_FAMILY12H
 292     #define OPTION_FAMILY12H  FALSE
 293   #endif
 294 #endif
 295
 296 #if (OPTION_FAMILY14H == TRUE)
 297   #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
 298     #undef OPTION_FAMILY14H
 299     #define OPTION_FAMILY14H  FALSE
 300   #endif
 301 #endif
 302
 303 #if (OPTION_FAMILY15H == TRUE)
 304   #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
 305     #undef OPTION_FAMILY15H
 306     #define OPTION_FAMILY15H  FALSE
 307   #endif
 308 #endif
 309
 310
 311 /*  Check for invalid combinations of socket/family */
 312 #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
 313   #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
 314     #error No G34 supported families included in the build
 315   #endif
 316 #endif
 317
 318 #if (OPTION_C32_SOCKET_SUPPORT == TRUE)
 319   #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
 320     #error No C32 supported families included in the build
 321   #endif
 322 #endif
 323
 324 #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
 325   #if (OPTION_FAMILY10H == FALSE)
 326     #error No S1G3 supported families included in the build
 327   #endif
 328 #endif
 329
 330 #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
 331   #if (OPTION_FAMILY10H == FALSE)
 332     #error No S1G4 supported families included in the build
 333   #endif
 334 #endif
 335
 336 #if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
 337   #if (OPTION_FAMILY10H == FALSE)
 338     #error No ASB2 supported families included in the build
 339   #endif
 340 #endif
 341
 342 #if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
 343   #if (OPTION_FAMILY12H == FALSE)
 344     #error No FS1 supported families included in the build
 345   #endif
 346 #endif
 347
 348 #if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
 349   #if (OPTION_FAMILY12H == FALSE)
 350     #error No FM1 supported families included in the build
 351   #endif
 352 #endif
 353
 354 #if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
 355   #if (OPTION_FAMILY12H == FALSE)
 356     #error No FP1 supported families included in the build
 357   #endif
 358 #endif
 359
 360 #if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
 361   #if (OPTION_FAMILY14H == FALSE)
 362     #error No FT1 supported families included in the build
 363   #endif
 364 #endif
 365
 366 #if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
 367   #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
 368     #error No AM3 supported families included in the build
 369   #endif
 370 #endif
 371
 372
 373 /* Process AGESA private data
 374  *
 375  * Turn on appropriate CPU models and memory controllers,
 376  * as well as some other memory controls.
 377  */
 378
 379 /*  Default all models to off  */
 380 #define OPTION_FAMILY10H_BL          FALSE
 381 #define OPTION_FAMILY10H_DA          FALSE
 382 #define OPTION_FAMILY10H_HY          FALSE
 383 #define OPTION_FAMILY10H_PH          FALSE
 384 #define OPTION_FAMILY10H_RB          FALSE
 385 #define OPTION_FAMILY12H_LN          FALSE
 386 #define OPTION_FAMILY14H_ON          FALSE
 387 #define OPTION_FAMILY15H_OR          FALSE
 388
 389 /*  Default all memory controllers to off  */
 390 #define OPTION_MEMCTLR_DR            FALSE
 391 #define OPTION_MEMCTLR_HY            FALSE
 392 #define OPTION_MEMCTLR_OR            FALSE
 393 #define OPTION_MEMCTLR_C32           FALSE
 394 #define OPTION_MEMCTLR_DA            FALSE
 395 #define OPTION_MEMCTLR_LN            FALSE
 396 #define OPTION_MEMCTLR_ON            FALSE
 397 #define OPTION_MEMCTLR_Ni            FALSE
 398 #define OPTION_MEMCTLR_PH            FALSE
 399 #define OPTION_MEMCTLR_RB            FALSE
 400
 401 /*  Default all memory controls to off  */
 402 #define OPTION_HW_WRITE_LEV_TRAINING            FALSE
 403 #define OPTION_SW_WRITE_LEV_TRAINING            FALSE
 404 #define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
 405 #define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
 406 #define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   FALSE
 407 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING       FALSE
 408 #define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
 409 #define OPTION_OPT_SW_RD_WR_POS_TRAINING        FALSE
 410 #define OPTION_MAX_RD_LAT_TRAINING              FALSE
 411 #define OPTION_HW_DRAM_INIT                     FALSE
 412 #define OPTION_SW_DRAM_INIT                     FALSE
 413 #define OPTION_S3_MEM_SUPPORT                   FALSE
 414 #define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
 415 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      FALSE
 416
 417 /*  Defaults for public user options  */
 418 #define OPTION_UDIMMS                           FALSE
 419 #define OPTION_RDIMMS                           FALSE
 420 #define OPTION_SODIMMS                          FALSE
 421 #define OPTION_LRDIMMS                          FALSE
 422 #define OPTION_DDR2                             FALSE
 423 #define OPTION_DDR3                             FALSE
 424 #define OPTION_ECC                              FALSE
 425 #define OPTION_BANK_INTERLEAVE                  FALSE
 426 #define OPTION_DCT_INTERLEAVE                   FALSE
 427 #define OPTION_NODE_INTERLEAVE                  FALSE
 428 #define OPTION_PARALLEL_TRAINING                FALSE
 429 #define OPTION_ONLINE_SPARE                     FALSE
 430 #define OPTION_MEM_RESTORE                      FALSE
 431 #define OPTION_DIMM_EXCLUDE                     FALSE
 432
 433 /*  Default all CPU controls to off  */
 434 #define OPTION_MULTISOCKET                      FALSE
 435 #define OPTION_SRAT                             FALSE
 436 #define OPTION_SLIT                             FALSE
 437 #define OPTION_HT_ASSIST                        FALSE
 438 #define OPTION_ATM_MODE                         FALSE
 439 #define OPTION_CPU_CORELEVLING                  FALSE
 440 #define OPTION_MSG_BASED_C1E                    FALSE
 441 #define OPTION_CPU_CFOH                         FALSE
 442 #define OPTION_C6_STATE                         FALSE
 443 #define OPTION_IO_CSTATE                        FALSE
 444 #define OPTION_CPB                              FALSE
 445 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT   FALSE
 446 #define OPTION_S3SCRIPT                         FALSE
 447 #define OPTION_GFX_RECOVERY                     FALSE
 448
 449 /*  Default FCH controls to off  */
 450 #define FCH_SUPPORT                             FALSE
 451
 452 /*  Enable all private controls based on socket/family enables  */
 453 #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
 454   #if (OPTION_FAMILY10H == TRUE)
 455     #undef OPTION_FAMILY10H_HY
 456     #define OPTION_FAMILY10H_HY  TRUE
 457     #undef OPTION_MEMCTLR_HY
 458     #define OPTION_MEMCTLR_HY    TRUE
 459     #undef OPTION_HW_WRITE_LEV_TRAINING
 460     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 461     #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
 462     #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
 463     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 464     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 465     #undef OPTION_MAX_RD_LAT_TRAINING
 466     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 467     #undef OPTION_SW_DRAM_INIT
 468     #define OPTION_SW_DRAM_INIT  TRUE
 469     #undef OPTION_S3_MEM_SUPPORT
 470     #define OPTION_S3_MEM_SUPPORT  TRUE
 471     #undef OPTION_MULTISOCKET
 472     #define OPTION_MULTISOCKET  TRUE
 473     #undef OPTION_SRAT
 474     #define OPTION_SRAT  TRUE
 475     #undef OPTION_SLIT
 476     #define OPTION_SLIT  TRUE
 477     #undef OPTION_HT_ASSIST
 478     #define OPTION_HT_ASSIST  TRUE
 479     #undef OPTION_CPU_CORELEVLING
 480     #define OPTION_CPU_CORELEVLING  TRUE
 481     #undef OPTION_MSG_BASED_C1E
 482     #define OPTION_MSG_BASED_C1E  TRUE
 483     #undef OPTION_CPU_CFOH
 484     #define OPTION_CPU_CFOH  TRUE
 485     #undef OPTION_UDIMMS
 486     #define OPTION_UDIMMS  TRUE
 487     #undef OPTION_RDIMMS
 488     #define OPTION_RDIMMS  TRUE
 489     #undef OPTION_SODIMMS
 490     #define OPTION_SODIMMS  TRUE
 491     #undef OPTION_DDR3
 492     #define OPTION_DDR3  TRUE
 493     #undef OPTION_ECC
 494     #define OPTION_ECC  TRUE
 495     #undef OPTION_BANK_INTERLEAVE
 496     #define OPTION_BANK_INTERLEAVE  TRUE
 497     #undef OPTION_DCT_INTERLEAVE
 498     #define OPTION_DCT_INTERLEAVE  TRUE
 499     #undef OPTION_NODE_INTERLEAVE
 500     #define OPTION_NODE_INTERLEAVE  TRUE
 501     #undef OPTION_PARALLEL_TRAINING
 502     #define OPTION_PARALLEL_TRAINING  TRUE
 503     #undef OPTION_MEM_RESTORE
 504     #define OPTION_MEM_RESTORE  TRUE
 505     #undef OPTION_ONLINE_SPARE
 506     #define OPTION_ONLINE_SPARE TRUE
 507     #undef OPTION_DIMM_EXCLUDE
 508     #define OPTION_DIMM_EXCLUDE  TRUE
 509   #endif
 510   #if (OPTION_FAMILY15H == TRUE)
 511     #undef OPTION_FAMILY15H_OR
 512     #define OPTION_FAMILY15H_OR  TRUE
 513     #undef OPTION_MEMCTLR_OR
 514     #define OPTION_MEMCTLR_OR    TRUE
 515     #undef OPTION_HW_WRITE_LEV_TRAINING
 516     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 517     #undef OPTION_CONTINOUS_PATTERN_GENERATION
 518     #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
 519     #undef OPTION_HW_DQS_REC_EN_TRAINING
 520     #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
 521     #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
 522     #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
 523     #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
 524     #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
 525     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 526     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 527     #undef OPTION_MAX_RD_LAT_TRAINING
 528     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 529     #undef OPTION_SW_DRAM_INIT
 530     #define OPTION_SW_DRAM_INIT  TRUE
 531     #undef OPTION_S3_MEM_SUPPORT
 532     #define OPTION_S3_MEM_SUPPORT  TRUE
 533     #undef OPTION_MULTISOCKET
 534     #define OPTION_MULTISOCKET  TRUE
 535     #undef OPTION_C6_STATE
 536     #define OPTION_C6_STATE  TRUE
 537     #undef OPTION_IO_CSTATE
 538     #define OPTION_IO_CSTATE TRUE
 539     #undef OPTION_CPB
 540     #define OPTION_CPB  TRUE
 541     #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
 542     #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
 543     #undef OPTION_SRAT
 544     #define OPTION_SRAT  TRUE
 545     #undef OPTION_SLIT
 546     #define OPTION_SLIT  TRUE
 547     #undef OPTION_HT_ASSIST
 548     #define OPTION_HT_ASSIST  TRUE
 549     #undef OPTION_ATM_MODE
 550     #define OPTION_ATM_MODE  TRUE
 551     #undef OPTION_CPU_CORELEVLING
 552     #define OPTION_CPU_CORELEVLING  TRUE
 553     #undef OPTION_MSG_BASED_C1E
 554     #define OPTION_MSG_BASED_C1E  TRUE
 555     #undef OPTION_CPU_CFOH
 556     #define OPTION_CPU_CFOH  TRUE
 557     #undef OPTION_UDIMMS
 558     #define OPTION_UDIMMS  TRUE
 559     #undef OPTION_RDIMMS
 560     #define OPTION_RDIMMS  TRUE
 561     #undef OPTION_SODIMMS
 562     #define OPTION_SODIMMS  TRUE
 563     #undef OPTION_LRDIMMS
 564     #define OPTION_LRDIMMS  TRUE
 565     #undef OPTION_DDR3
 566     #define OPTION_DDR3  TRUE
 567     #undef OPTION_ECC
 568     #define OPTION_ECC  TRUE
 569     #undef OPTION_BANK_INTERLEAVE
 570     #define OPTION_BANK_INTERLEAVE  TRUE
 571     #undef OPTION_DCT_INTERLEAVE
 572     #define OPTION_DCT_INTERLEAVE  TRUE
 573     #undef OPTION_NODE_INTERLEAVE
 574     #define OPTION_NODE_INTERLEAVE  TRUE
 575     #undef OPTION_MEM_RESTORE
 576     #define OPTION_MEM_RESTORE  TRUE
 577     #undef OPTION_ONLINE_SPARE
 578     #define OPTION_ONLINE_SPARE TRUE
 579     #undef OPTION_DIMM_EXCLUDE
 580     #define OPTION_DIMM_EXCLUDE  TRUE
 581   #endif
 582 #endif
 583
 584 #if (OPTION_C32_SOCKET_SUPPORT == TRUE)
 585   #if (OPTION_FAMILY10H == TRUE)
 586     #undef OPTION_FAMILY10H_HY
 587     #define OPTION_FAMILY10H_HY  TRUE
 588     #undef OPTION_MEMCTLR_C32
 589     #define OPTION_MEMCTLR_C32   TRUE
 590     #undef OPTION_HW_WRITE_LEV_TRAINING
 591     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 592     #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
 593     #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
 594     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 595     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 596     #undef OPTION_MAX_RD_LAT_TRAINING
 597     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 598     #undef OPTION_SW_DRAM_INIT
 599     #define OPTION_SW_DRAM_INIT  TRUE
 600     #undef OPTION_S3_MEM_SUPPORT
 601     #define OPTION_S3_MEM_SUPPORT  TRUE
 602     #undef OPTION_ADDR_TO_CS_TRANSLATOR
 603     #define OPTION_ADDR_TO_CS_TRANSLATOR  FALSE
 604     #undef OPTION_MULTISOCKET
 605     #define OPTION_MULTISOCKET  TRUE
 606     #undef OPTION_SRAT
 607     #define OPTION_SRAT  TRUE
 608     #undef OPTION_SLIT
 609     #define OPTION_SLIT  TRUE
 610     #undef OPTION_HT_ASSIST
 611     #define OPTION_HT_ASSIST  TRUE
 612     #undef OPTION_CPU_CORELEVLING
 613     #define OPTION_CPU_CORELEVLING  TRUE
 614     #undef OPTION_MSG_BASED_C1E
 615     #define OPTION_MSG_BASED_C1E  TRUE
 616     #undef OPTION_CPU_CFOH
 617     #define OPTION_CPU_CFOH  TRUE
 618     #undef OPTION_UDIMMS
 619     #define OPTION_UDIMMS  TRUE
 620     #undef OPTION_RDIMMS
 621     #define OPTION_RDIMMS  TRUE
 622     #undef OPTION_SODIMMS
 623     #define OPTION_SODIMMS  TRUE
 624     #undef OPTION_DDR3
 625     #define OPTION_DDR3  TRUE
 626     #undef OPTION_ECC
 627     #define OPTION_ECC  TRUE
 628     #undef OPTION_BANK_INTERLEAVE
 629     #define OPTION_BANK_INTERLEAVE  TRUE
 630     #undef OPTION_DCT_INTERLEAVE
 631     #define OPTION_DCT_INTERLEAVE  TRUE
 632     #undef OPTION_NODE_INTERLEAVE
 633     #define OPTION_NODE_INTERLEAVE  TRUE
 634     #undef OPTION_PARALLEL_TRAINING
 635     #define OPTION_PARALLEL_TRAINING  TRUE
 636     #undef OPTION_MEM_RESTORE
 637     #define OPTION_MEM_RESTORE  TRUE
 638     #undef OPTION_ONLINE_SPARE
 639     #define OPTION_ONLINE_SPARE TRUE
 640     #undef OPTION_DIMM_EXCLUDE
 641     #define OPTION_DIMM_EXCLUDE  TRUE
 642   #endif
 643   #if (OPTION_FAMILY15H == TRUE)
 644     #undef OPTION_FAMILY15H_OR
 645     #define OPTION_FAMILY15H_OR  TRUE
 646     #undef OPTION_MEMCTLR_OR
 647     #define OPTION_MEMCTLR_OR    TRUE
 648     #undef OPTION_HW_WRITE_LEV_TRAINING
 649     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 650     #undef OPTION_CONTINOUS_PATTERN_GENERATION
 651     #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
 652     #undef OPTION_HW_DQS_REC_EN_TRAINING
 653     #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
 654     #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
 655     #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
 656     #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
 657     #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
 658     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 659     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 660     #undef OPTION_MAX_RD_LAT_TRAINING
 661     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 662     #undef OPTION_SW_DRAM_INIT
 663     #define OPTION_SW_DRAM_INIT  TRUE
 664     #undef OPTION_S3_MEM_SUPPORT
 665     #define OPTION_S3_MEM_SUPPORT  TRUE
 666     #undef OPTION_ADDR_TO_CS_TRANSLATOR
 667     #define OPTION_ADDR_TO_CS_TRANSLATOR  TRUE
 668     #undef OPTION_MULTISOCKET
 669     #define OPTION_MULTISOCKET  TRUE
 670     #undef OPTION_C6_STATE
 671     #define OPTION_C6_STATE  TRUE
 672     #undef OPTION_IO_CSTATE
 673     #define OPTION_IO_CSTATE TRUE
 674     #undef OPTION_CPB
 675     #define OPTION_CPB  TRUE
 676     #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
 677     #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
 678     #undef OPTION_SRAT
 679     #define OPTION_SRAT  TRUE
 680     #undef OPTION_SLIT
 681     #define OPTION_SLIT  TRUE
 682     #undef OPTION_HT_ASSIST
 683     #define OPTION_HT_ASSIST  TRUE
 684     #undef OPTION_ATM_MODE
 685     #define OPTION_ATM_MODE  TRUE
 686     #undef OPTION_CPU_CORELEVLING
 687     #define OPTION_CPU_CORELEVLING  TRUE
 688     #undef OPTION_MSG_BASED_C1E
 689     #define OPTION_MSG_BASED_C1E  TRUE
 690     #undef OPTION_CPU_CFOH
 691     #define OPTION_CPU_CFOH  TRUE
 692     #undef OPTION_UDIMMS
 693     #define OPTION_UDIMMS  TRUE
 694     #undef OPTION_RDIMMS
 695     #define OPTION_RDIMMS  TRUE
 696     #undef OPTION_SODIMMS
 697     #define OPTION_SODIMMS  TRUE
 698     #undef OPTION_LRDIMMS
 699     #define OPTION_LRDIMMS  TRUE
 700     #undef OPTION_DDR3
 701     #define OPTION_DDR3  TRUE
 702     #undef OPTION_ECC
 703     #define OPTION_ECC  TRUE
 704     #undef OPTION_BANK_INTERLEAVE
 705     #define OPTION_BANK_INTERLEAVE  TRUE
 706     #undef OPTION_DCT_INTERLEAVE
 707     #define OPTION_DCT_INTERLEAVE  TRUE
 708     #undef OPTION_NODE_INTERLEAVE
 709     #define OPTION_NODE_INTERLEAVE  TRUE
 710     #undef OPTION_MEM_RESTORE
 711     #define OPTION_MEM_RESTORE  TRUE
 712     #undef OPTION_ONLINE_SPARE
 713     #define OPTION_ONLINE_SPARE TRUE
 714     #undef OPTION_DIMM_EXCLUDE
 715     #define OPTION_DIMM_EXCLUDE  TRUE
 716   #endif
 717 #endif
 718
 719 #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
 720   #if (OPTION_FAMILY10H == TRUE)
 721     #undef OPTION_FAMILY10H_BL
 722     #define OPTION_FAMILY10H_BL  TRUE
 723     #undef OPTION_FAMILY10H_DA
 724     #define OPTION_FAMILY10H_DA  TRUE
 725     #undef OPTION_MEMCTLR_DA
 726     #define OPTION_MEMCTLR_DA    TRUE
 727     #undef OPTION_HW_WRITE_LEV_TRAINING
 728     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 729     #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
 730     #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
 731     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 732     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 733     #undef OPTION_MAX_RD_LAT_TRAINING
 734     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 735     #undef OPTION_SW_DRAM_INIT
 736     #define OPTION_SW_DRAM_INIT  TRUE
 737     #undef OPTION_S3_MEM_SUPPORT
 738     #define OPTION_S3_MEM_SUPPORT  TRUE
 739     #undef OPTION_CPU_CORELEVLING
 740     #define OPTION_CPU_CORELEVLING  TRUE
 741     #undef OPTION_CPU_CFOH
 742     #define OPTION_CPU_CFOH  TRUE
 743     #undef OPTION_UDIMMS
 744     #define OPTION_UDIMMS  TRUE
 745     #undef OPTION_SODIMMS
 746     #define OPTION_SODIMMS  TRUE
 747     #undef OPTION_DDR3
 748     #define OPTION_DDR3  TRUE
 749     #undef OPTION_ECC
 750     #define OPTION_ECC  TRUE
 751     #undef OPTION_BANK_INTERLEAVE
 752     #define OPTION_BANK_INTERLEAVE  TRUE
 753     #undef OPTION_DCT_INTERLEAVE
 754     #define OPTION_DCT_INTERLEAVE  TRUE
 755     #undef OPTION_NODE_INTERLEAVE
 756     #define OPTION_NODE_INTERLEAVE  TRUE
 757     #undef OPTION_PARALLEL_TRAINING
 758     #define OPTION_PARALLEL_TRAINING  TRUE
 759     #undef OPTION_MEM_RESTORE
 760     #define OPTION_MEM_RESTORE  TRUE
 761     #undef OPTION_ONLINE_SPARE
 762     #define OPTION_ONLINE_SPARE TRUE
 763     #undef OPTION_DIMM_EXCLUDE
 764     #define OPTION_DIMM_EXCLUDE  TRUE
 765   #endif
 766 #endif
 767
 768 #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
 769   #if (OPTION_FAMILY10H == TRUE)
 770     #undef OPTION_FAMILY10H_BL
 771     #define OPTION_FAMILY10H_BL  TRUE
 772     #undef OPTION_FAMILY10H_DA
 773     #define OPTION_FAMILY10H_DA  TRUE
 774     #undef OPTION_MEMCTLR_DA
 775     #define OPTION_MEMCTLR_DA    TRUE
 776     #undef OPTION_HW_WRITE_LEV_TRAINING
 777     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 778     #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
 779     #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
 780     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 781     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 782     #undef OPTION_MAX_RD_LAT_TRAINING
 783     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 784     #undef OPTION_SW_DRAM_INIT
 785     #define OPTION_SW_DRAM_INIT  TRUE
 786     #undef OPTION_S3_MEM_SUPPORT
 787     #define OPTION_S3_MEM_SUPPORT  TRUE
 788     #undef OPTION_CPU_CORELEVLING
 789     #define OPTION_CPU_CORELEVLING  TRUE
 790     #undef OPTION_CPU_CFOH
 791     #define OPTION_CPU_CFOH  TRUE
 792     #undef OPTION_UDIMMS
 793     #define OPTION_UDIMMS  TRUE
 794     #undef OPTION_SODIMMS
 795     #define OPTION_SODIMMS  TRUE
 796     #undef OPTION_DDR3
 797     #define OPTION_DDR3  TRUE
 798     #undef OPTION_ECC
 799     #define OPTION_ECC  TRUE
 800     #undef OPTION_BANK_INTERLEAVE
 801     #define OPTION_BANK_INTERLEAVE  TRUE
 802     #undef OPTION_DCT_INTERLEAVE
 803     #define OPTION_DCT_INTERLEAVE  TRUE
 804     #undef OPTION_NODE_INTERLEAVE
 805     #define OPTION_NODE_INTERLEAVE  TRUE
 806     #undef OPTION_MEM_RESTORE
 807     #define OPTION_MEM_RESTORE  TRUE
 808     #undef OPTION_DIMM_EXCLUDE
 809     #define OPTION_DIMM_EXCLUDE  TRUE
 810   #endif
 811 #endif
 812
 813 #if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
 814   #if (OPTION_FAMILY10H == TRUE)
 815     #undef OPTION_FAMILY10H_BL
 816     #define OPTION_FAMILY10H_BL  TRUE
 817     #undef OPTION_FAMILY10H_DA
 818     #define OPTION_FAMILY10H_DA  TRUE
 819     #undef OPTION_MEMCTLR_Ni
 820     #define OPTION_MEMCTLR_Ni    TRUE
 821     #undef OPTION_HW_WRITE_LEV_TRAINING
 822     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 823     #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
 824     #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
 825     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 826     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 827     #undef OPTION_MAX_RD_LAT_TRAINING
 828     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 829     #undef OPTION_SW_DRAM_INIT
 830     #define OPTION_SW_DRAM_INIT  TRUE
 831     #undef OPTION_S3_MEM_SUPPORT
 832     #define OPTION_S3_MEM_SUPPORT  TRUE
 833     #undef OPTION_CPU_CORELEVLING
 834     #define OPTION_CPU_CORELEVLING  TRUE
 835     #undef OPTION_CPU_CFOH
 836     #define OPTION_CPU_CFOH  TRUE
 837     #undef OPTION_UDIMMS
 838     #define OPTION_UDIMMS  TRUE
 839     #undef OPTION_SODIMMS
 840     #define OPTION_SODIMMS  TRUE
 841     #undef OPTION_DDR3
 842     #define OPTION_DDR3  TRUE
 843     #undef OPTION_ECC
 844     #define OPTION_ECC  TRUE
 845     #undef OPTION_BANK_INTERLEAVE
 846     #define OPTION_BANK_INTERLEAVE  TRUE
 847     #undef OPTION_DCT_INTERLEAVE
 848     #define OPTION_DCT_INTERLEAVE  TRUE
 849     #undef OPTION_NODE_INTERLEAVE
 850     #define OPTION_NODE_INTERLEAVE  TRUE
 851     #undef OPTION_MEM_RESTORE
 852     #define OPTION_MEM_RESTORE  TRUE
 853     #undef OPTION_DIMM_EXCLUDE
 854     #define OPTION_DIMM_EXCLUDE  TRUE
 855   #endif
 856 #endif
 857
 858 #if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
 859   #if (OPTION_FAMILY12H == TRUE)
 860     #undef OPTION_FAMILY12H_LN
 861     #define OPTION_FAMILY12H_LN  TRUE
 862     #undef OPTION_MEMCTLR_LN
 863     #define OPTION_MEMCTLR_LN    TRUE
 864     #undef OPTION_HW_WRITE_LEV_TRAINING
 865     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 866     #undef OPTION_CONTINOUS_PATTERN_GENERATION
 867     #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
 868     #undef OPTION_HW_DQS_REC_EN_TRAINING
 869     #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
 870     #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
 871     #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
 872     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 873     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 874     #undef OPTION_MAX_RD_LAT_TRAINING
 875     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 876     #undef OPTION_SW_DRAM_INIT
 877     #define OPTION_SW_DRAM_INIT  TRUE
 878     #undef OPTION_S3_MEM_SUPPORT
 879     #define OPTION_S3_MEM_SUPPORT  TRUE
 880     #undef OPTION_GFX_RECOVERY
 881     #define OPTION_GFX_RECOVERY  TRUE
 882     #undef OPTION_C6_STATE
 883     #define OPTION_C6_STATE  TRUE
 884     #undef OPTION_IO_CSTATE
 885     #define OPTION_IO_CSTATE TRUE
 886     #undef OPTION_CPB
 887     #define OPTION_CPB  TRUE
 888     #undef OPTION_S3SCRIPT
 889     #define OPTION_S3SCRIPT  TRUE
 890     #undef OPTION_UDIMMS
 891     #define OPTION_UDIMMS  TRUE
 892     #undef OPTION_SODIMMS
 893     #define OPTION_SODIMMS  TRUE
 894     #undef OPTION_DDR3
 895     #define OPTION_DDR3  TRUE
 896     #undef OPTION_BANK_INTERLEAVE
 897     #define OPTION_BANK_INTERLEAVE  TRUE
 898     #undef OPTION_DCT_INTERLEAVE
 899     #define OPTION_DCT_INTERLEAVE  TRUE
 900     #undef OPTION_MEM_RESTORE
 901     #define OPTION_MEM_RESTORE  TRUE
 902     #undef OPTION_DIMM_EXCLUDE
 903     #define OPTION_DIMM_EXCLUDE  TRUE
 904   #endif
 905 #endif
 906
 907 #if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
 908   #if (OPTION_FAMILY12H == TRUE)
 909     #undef OPTION_FAMILY12H_LN
 910     #define OPTION_FAMILY12H_LN  TRUE
 911     #undef OPTION_MEMCTLR_LN
 912     #define OPTION_MEMCTLR_LN    TRUE
 913     #undef OPTION_HW_WRITE_LEV_TRAINING
 914     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 915     #undef OPTION_CONTINOUS_PATTERN_GENERATION
 916     #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
 917     #undef OPTION_HW_DQS_REC_EN_TRAINING
 918     #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
 919     #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
 920     #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
 921     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 922     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 923     #undef OPTION_MAX_RD_LAT_TRAINING
 924     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 925     #undef OPTION_SW_DRAM_INIT
 926     #define OPTION_SW_DRAM_INIT  TRUE
 927     #undef OPTION_S3_MEM_SUPPORT
 928     #define OPTION_S3_MEM_SUPPORT  TRUE
 929     #undef OPTION_GFX_RECOVERY
 930     #define OPTION_GFX_RECOVERY  TRUE
 931     #undef OPTION_C6_STATE
 932     #define OPTION_C6_STATE  TRUE
 933     #undef OPTION_IO_CSTATE
 934     #define OPTION_IO_CSTATE TRUE
 935     #undef OPTION_CPB
 936     #define OPTION_CPB  TRUE
 937     #undef OPTION_S3SCRIPT
 938     #define OPTION_S3SCRIPT  TRUE
 939     #undef OPTION_UDIMMS
 940     #define OPTION_UDIMMS  TRUE
 941     #undef OPTION_SODIMMS
 942     #define OPTION_SODIMMS  TRUE
 943     #undef OPTION_DDR3
 944     #define OPTION_DDR3  TRUE
 945     #undef OPTION_BANK_INTERLEAVE
 946     #define OPTION_BANK_INTERLEAVE  TRUE
 947     #undef OPTION_DCT_INTERLEAVE
 948     #define OPTION_DCT_INTERLEAVE  TRUE
 949     #undef OPTION_MEM_RESTORE
 950     #define OPTION_MEM_RESTORE  TRUE
 951     #undef OPTION_DIMM_EXCLUDE
 952     #define OPTION_DIMM_EXCLUDE  TRUE
 953   #endif
 954 #endif
 955
 956 #if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
 957   #if (OPTION_FAMILY12H == TRUE)
 958     #undef OPTION_FAMILY12H_LN
 959     #define OPTION_FAMILY12H_LN  TRUE
 960     #undef OPTION_MEMCTLR_LN
 961     #define OPTION_MEMCTLR_LN    TRUE
 962     #undef OPTION_HW_WRITE_LEV_TRAINING
 963     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
 964     #undef OPTION_CONTINOUS_PATTERN_GENERATION
 965     #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
 966     #undef OPTION_HW_DQS_REC_EN_TRAINING
 967     #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
 968     #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
 969     #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
 970     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
 971     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
 972     #undef OPTION_MAX_RD_LAT_TRAINING
 973     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
 974     #undef OPTION_SW_DRAM_INIT
 975     #define OPTION_SW_DRAM_INIT  TRUE
 976     #undef OPTION_S3_MEM_SUPPORT
 977     #define OPTION_S3_MEM_SUPPORT  TRUE
 978     #undef OPTION_ADDR_TO_CS_TRANSLATOR
 979     #define OPTION_ADDR_TO_CS_TRANSLATOR  TRUE
 980     #undef OPTION_GFX_RECOVERY
 981     #define OPTION_GFX_RECOVERY  TRUE
 982     #undef OPTION_C6_STATE
 983     #define OPTION_C6_STATE  TRUE
 984     #undef OPTION_IO_CSTATE
 985     #define OPTION_IO_CSTATE TRUE
 986     #undef OPTION_CPB
 987     #define OPTION_CPB  TRUE
 988     #undef OPTION_S3SCRIPT
 989     #define OPTION_S3SCRIPT  TRUE
 990     #undef OPTION_UDIMMS
 991     #define OPTION_UDIMMS  TRUE
 992     #undef OPTION_SODIMMS
 993     #define OPTION_SODIMMS  TRUE
 994     #undef OPTION_DDR3
 995     #define OPTION_DDR3  TRUE
 996     #undef OPTION_BANK_INTERLEAVE
 997     #define OPTION_BANK_INTERLEAVE  TRUE
 998     #undef OPTION_DCT_INTERLEAVE
 999     #define OPTION_DCT_INTERLEAVE  TRUE
1000     #undef OPTION_MEM_RESTORE
1001     #define OPTION_MEM_RESTORE  TRUE
1002     #undef OPTION_ONLINE_SPARE
1003     #define OPTION_ONLINE_SPARE TRUE
1004     #undef OPTION_DIMM_EXCLUDE
1005     #define OPTION_DIMM_EXCLUDE  TRUE
1006   #endif
1007 #endif
1008
1009 #if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
1010   #if (OPTION_FAMILY14H == TRUE)
1011     #undef OPTION_FAMILY14H_ON
1012     #define OPTION_FAMILY14H_ON  TRUE
1013     #undef OPTION_MEMCTLR_ON
1014     #define OPTION_MEMCTLR_ON    TRUE
1015     #undef OPTION_HW_WRITE_LEV_TRAINING
1016     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
1017     #undef OPTION_CONTINOUS_PATTERN_GENERATION
1018     #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
1019     #undef OPTION_MAX_RD_LAT_TRAINING
1020     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
1021     #undef OPTION_HW_DQS_REC_EN_TRAINING
1022     #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
1023     #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1024     #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      FALSE
1025     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1026     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
1027     #undef OPTION_SW_DRAM_INIT
1028     #define OPTION_SW_DRAM_INIT  TRUE
1029     #undef OPTION_S3_MEM_SUPPORT
1030     #define OPTION_S3_MEM_SUPPORT  TRUE
1031     #undef OPTION_GFX_RECOVERY
1032     #define OPTION_GFX_RECOVERY  TRUE
1033     #undef OPTION_C6_STATE
1034     #define OPTION_C6_STATE  TRUE
1035     #undef OPTION_IO_CSTATE
1036     #define OPTION_IO_CSTATE TRUE
1037     #undef OPTION_CPB
1038     #define OPTION_CPB TRUE
1039     #undef OPTION_S3SCRIPT
1040     #define OPTION_S3SCRIPT  TRUE
1041     #undef OPTION_UDIMMS
1042     #define OPTION_UDIMMS  TRUE
1043     #undef OPTION_SODIMMS
1044     #define OPTION_SODIMMS  TRUE
1045     #undef OPTION_DDR3
1046     #define OPTION_DDR3  TRUE
1047     #undef OPTION_BANK_INTERLEAVE
1048     #define OPTION_BANK_INTERLEAVE  TRUE
1049     #undef OPTION_MEM_RESTORE
1050     #define OPTION_MEM_RESTORE  TRUE
1051     #undef OPTION_DIMM_EXCLUDE
1052     #define OPTION_DIMM_EXCLUDE  TRUE
1053   #endif
1054 #endif
1055
1056 #if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
1057   #if (OPTION_FAMILY10H == TRUE)
1058     #undef OPTION_FAMILY10H_BL
1059     #define OPTION_FAMILY10H_BL  TRUE
1060     #undef OPTION_FAMILY10H_DA
1061     #define OPTION_FAMILY10H_DA  TRUE
1062     #undef OPTION_FAMILY10H_PH
1063     #define OPTION_FAMILY10H_PH  TRUE
1064     #undef OPTION_FAMILY10H_RB
1065     #define OPTION_FAMILY10H_RB  TRUE
1066     #undef OPTION_MEMCTLR_RB
1067     #define OPTION_MEMCTLR_RB   TRUE
1068     #undef OPTION_MEMCTLR_DA
1069     #define OPTION_MEMCTLR_DA   TRUE
1070     #undef OPTION_MEMCTLR_PH
1071     #define OPTION_MEMCTLR_PH   TRUE
1072     #undef OPTION_HW_WRITE_LEV_TRAINING
1073     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
1074     #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
1075     #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
1076     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1077     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
1078     #undef OPTION_MAX_RD_LAT_TRAINING
1079     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
1080     #undef OPTION_SW_DRAM_INIT
1081     #define OPTION_SW_DRAM_INIT  TRUE
1082     #undef OPTION_S3_MEM_SUPPORT
1083     #define OPTION_S3_MEM_SUPPORT  TRUE
1084     #undef OPTION_CPU_CORELEVLING
1085     #define OPTION_CPU_CORELEVLING  TRUE
1086     #undef OPTION_CPU_CFOH
1087     #define OPTION_CPU_CFOH  TRUE
1088     #undef OPTION_IO_CSTATE
1089     #define OPTION_IO_CSTATE TRUE
1090     #undef OPTION_CPB
1091     #define OPTION_CPB  TRUE
1092     #undef OPTION_UDIMMS
1093     #define OPTION_UDIMMS  TRUE
1094     #undef OPTION_SODIMMS
1095     #define OPTION_SODIMMS  TRUE
1096     #undef OPTION_DDR3
1097     #define OPTION_DDR3  TRUE
1098     #undef OPTION_ECC
1099     #define OPTION_ECC  TRUE
1100     #undef OPTION_BANK_INTERLEAVE
1101     #define OPTION_BANK_INTERLEAVE  TRUE
1102     #undef OPTION_DCT_INTERLEAVE
1103     #define OPTION_DCT_INTERLEAVE  TRUE
1104     #undef OPTION_NODE_INTERLEAVE
1105     #define OPTION_NODE_INTERLEAVE  TRUE
1106     #undef OPTION_PARALLEL_TRAINING
1107     #define OPTION_PARALLEL_TRAINING  TRUE
1108     #undef OPTION_MEM_RESTORE
1109     #define OPTION_MEM_RESTORE  TRUE
1110     #undef OPTION_ONLINE_SPARE
1111     #define OPTION_ONLINE_SPARE TRUE
1112     #undef OPTION_DIMM_EXCLUDE
1113     #define OPTION_DIMM_EXCLUDE  TRUE
1114   #endif
1115   #if (OPTION_FAMILY15H == TRUE)
1116     #undef OPTION_FAMILY15H_OR
1117     #define OPTION_FAMILY15H_OR  TRUE
1118     #undef OPTION_MEMCTLR_OR
1119     #define OPTION_MEMCTLR_OR    TRUE
1120     #undef OPTION_HW_WRITE_LEV_TRAINING
1121     #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
1122     #undef OPTION_CONTINOUS_PATTERN_GENERATION
1123     #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
1124     #undef OPTION_HW_DQS_REC_EN_TRAINING
1125     #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
1126     #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1127     #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
1128     #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1129     #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
1130     #undef OPTION_MAX_RD_LAT_TRAINING
1131     #define OPTION_MAX_RD_LAT_TRAINING  TRUE
1132     #undef OPTION_SW_DRAM_INIT
1133     #define OPTION_SW_DRAM_INIT  TRUE
1134     #undef OPTION_C6_STATE
1135     #define OPTION_C6_STATE  TRUE
1136     #undef OPTION_IO_CSTATE
1137     #define OPTION_IO_CSTATE TRUE
1138     #undef OPTION_CPB
1139     #define OPTION_CPB  TRUE
1140     #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
1141     #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
1142     #undef OPTION_S3_MEM_SUPPORT
1143     #define OPTION_S3_MEM_SUPPORT  TRUE
1144     #undef OPTION_ADDR_TO_CS_TRANSLATOR
1145     #define OPTION_ADDR_TO_CS_TRANSLATOR  TRUE
1146     #undef OPTION_ATM_MODE
1147     #define OPTION_ATM_MODE TRUE
1148     #undef OPTION_CPU_CORELEVLING
1149     #define OPTION_CPU_CORELEVLING  TRUE
1150     #undef OPTION_CPU_CFOH
1151     #define OPTION_CPU_CFOH  TRUE
1152     #undef OPTION_MSG_BASED_C1E
1153     #define OPTION_MSG_BASED_C1E  TRUE
1154     #undef OPTION_UDIMMS
1155     #define OPTION_UDIMMS  TRUE
1156     #undef OPTION_RDIMMS
1157     #define OPTION_RDIMMS  TRUE
1158     #undef OPTION_LRDIMMS
1159     #define OPTION_LRDIMMS  TRUE
1160     #undef OPTION_SODIMMS
1161     #define OPTION_SODIMMS  TRUE
1162     #undef OPTION_DDR3
1163     #define OPTION_DDR3  TRUE
1164     #undef OPTION_ECC
1165     #define OPTION_ECC  TRUE
1166     #undef OPTION_BANK_INTERLEAVE
1167     #define OPTION_BANK_INTERLEAVE  TRUE
1168     #undef OPTION_DCT_INTERLEAVE
1169     #define OPTION_DCT_INTERLEAVE  TRUE
1170     #undef OPTION_NODE_INTERLEAVE
1171     #define OPTION_NODE_INTERLEAVE  TRUE
1172     #undef OPTION_MEM_RESTORE
1173     #define OPTION_MEM_RESTORE  TRUE
1174     #undef OPTION_ONLINE_SPARE
1175     #define OPTION_ONLINE_SPARE TRUE
1176     #undef OPTION_DIMM_EXCLUDE
1177     #define OPTION_DIMM_EXCLUDE  TRUE
1178   #endif
1179 #endif
1180
1181 #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
1182   #undef  GNB_SUPPORT
1183   #define GNB_SUPPORT   TRUE
1184 #endif
1185
1186 #define OPTION_ACPI_PSTATES             TRUE
1187 #define OPTION_WHEA                     TRUE
1188 #define OPTION_DMI                      TRUE
1189 #define OPTION_EARLY_SAMPLES            FALSE
1190 #define CFG_ACPI_PSTATES_PPC            TRUE
1191 #define CFG_ACPI_PSTATES_PCT            TRUE
1192 #define CFG_ACPI_PSTATES_PSD            TRUE
1193 #define CFG_ACPI_PSTATES_PSS            TRUE
1194 #define CFG_ACPI_PSTATES_XPSS           TRUE
1195 #define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
1196 #define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
1197 #define CFG_VRM_NB_HIGH_SPEED_ENABLE    FALSE
1198 #define OPTION_ALIB                     TRUE
1199 /*---------------------------------------------------------------------------
1200  *       Processing the options:  Second, process the user's selections
1201  *--------------------------------------------------------------------------*/
1202 #ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
1203   #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
1204     #undef  OPTION_MULTISOCKET
1205     #define OPTION_MULTISOCKET          FALSE
1206   #endif
1207 #endif
1208 #ifdef BLDOPT_REMOVE_ECC_SUPPORT
1209   #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
1210     #undef  OPTION_ECC
1211     #define OPTION_ECC        FALSE
1212   #endif
1213 #endif
1214 #ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
1215   #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
1216     #undef  OPTION_UDIMMS
1217     #define OPTION_UDIMMS               FALSE
1218   #endif
1219 #endif
1220 #ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
1221   #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
1222     #undef  OPTION_RDIMMS
1223     #define OPTION_RDIMMS               FALSE
1224   #endif
1225 #endif
1226 #ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
1227   #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
1228     #undef  OPTION_SODIMMS
1229     #define OPTION_SODIMMS               FALSE
1230   #endif
1231 #endif
1232 #ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
1233   #if  BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1234     #undef  OPTION_LRDIMMS
1235     #define OPTION_LRDIMMS               FALSE
1236   #endif
1237 #endif
1238 #ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
1239   #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
1240     #undef  OPTION_BANK_INTERLEAVE
1241     #define OPTION_BANK_INTERLEAVE      FALSE
1242   #endif
1243 #endif
1244 #ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
1245   #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
1246     #undef  OPTION_DCT_INTERLEAVE
1247     #define OPTION_DCT_INTERLEAVE       FALSE
1248   #endif
1249 #endif
1250 #ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
1251   #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
1252     #undef  OPTION_NODE_INTERLEAVE
1253     #define OPTION_NODE_INTERLEAVE      FALSE
1254   #endif
1255 #endif
1256 #ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
1257   #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
1258     #undef  OPTION_PARALLEL_TRAINING
1259     #define OPTION_PARALLEL_TRAINING    FALSE
1260   #endif
1261 #endif
1262 #ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
1263   #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
1264     #undef  OPTION_ONLINE_SPARE
1265     #define OPTION_ONLINE_SPARE         FALSE
1266   #endif
1267 #endif
1268 #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
1269   #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
1270     #undef  OPTION_MEM_RESTORE
1271     #define OPTION_MEM_RESTORE         FALSE
1272   #endif
1273 #endif
1274 #ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
1275   #if  BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
1276     #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1277     #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      FALSE
1278   #endif
1279 #endif
1280 #ifdef BLDOPT_REMOVE_ACPI_PSTATES
1281   #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
1282     #undef  OPTION_ACPI_PSTATES
1283     #define OPTION_ACPI_PSTATES         FALSE
1284   #endif
1285 #endif
1286 #ifdef BLDOPT_REMOVE_SRAT
1287   #if  BLDOPT_REMOVE_SRAT == TRUE
1288     #undef  OPTION_SRAT
1289     #define OPTION_SRAT                 FALSE
1290   #endif
1291 #endif
1292 #ifdef BLDOPT_REMOVE_SLIT
1293   #if  BLDOPT_REMOVE_SLIT == TRUE
1294     #undef  OPTION_SLIT
1295     #define OPTION_SLIT                 FALSE
1296   #endif
1297 #endif
1298 #ifdef BLDOPT_REMOVE_WHEA
1299   #if  BLDOPT_REMOVE_WHEA == TRUE
1300     #undef  OPTION_WHEA
1301     #define OPTION_WHEA                 FALSE
1302   #endif
1303 #endif
1304 #ifdef BLDOPT_REMOVE_DMI
1305   #if  BLDOPT_REMOVE_DMI == TRUE
1306     #undef  OPTION_DMI
1307     #define OPTION_DMI                  FALSE
1308   #endif
1309 #endif
1310 #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
1311   #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
1312     #undef  OPTION_ADDR_TO_CS_TRANSLATOR
1313     #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
1314   #endif
1315 #endif
1316
1317 #ifdef BLDOPT_REMOVE_HT_ASSIST
1318   #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
1319     #undef  OPTION_HT_ASSIST
1320     #define OPTION_HT_ASSIST      FALSE
1321   #endif
1322 #endif
1323
1324 #ifdef BLDOPT_REMOVE_ATM_MODE
1325   #if  BLDOPT_REMOVE_ATM_MODE == TRUE
1326     #undef  OPTION_ATM_MODE
1327     #define OPTION_ATM_MODE      FALSE
1328   #endif
1329 #endif
1330
1331 #ifdef BLDOPT_REMOVE_MSG_BASED_C1E
1332   #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
1333     #undef  OPTION_MSG_BASED_C1E
1334     #define OPTION_MSG_BASED_C1E      FALSE
1335   #endif
1336 #endif
1337
1338 #ifdef BLDOPT_REMOVE_C6_STATE
1339   #if  BLDOPT_REMOVE_C6_STATE == TRUE
1340     #undef  OPTION_C6_STATE
1341     #define OPTION_C6_STATE      FALSE
1342   #endif
1343 #endif
1344
1345 #ifdef BLDOPT_REMOVE_GFX_RECOVERY
1346   #if  BLDOPT_REMOVE_GFX_RECOVERY == TRUE
1347     #undef  OPTION_GFX_RECOVERY
1348     #define OPTION_GFX_RECOVERY         FALSE
1349   #endif
1350 #endif
1351
1352 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
1353   #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
1354     #undef  CFG_ACPI_PSTATES_PPC
1355     #define CFG_ACPI_PSTATES_PPC        FALSE
1356   #endif
1357 #endif
1358
1359 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
1360   #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
1361     #undef  CFG_ACPI_PSTATES_PCT
1362     #define CFG_ACPI_PSTATES_PCT        FALSE
1363   #endif
1364 #endif
1365
1366 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
1367   #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
1368     #undef  CFG_ACPI_PSTATES_PSD
1369     #define CFG_ACPI_PSTATES_PSD        FALSE
1370   #endif
1371 #endif
1372
1373 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
1374   #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
1375     #undef  CFG_ACPI_PSTATES_PSS
1376     #define CFG_ACPI_PSTATES_PSS        FALSE
1377   #endif
1378 #endif
1379
1380 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
1381   #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
1382     #undef  CFG_ACPI_PSTATES_XPSS
1383     #define CFG_ACPI_PSTATES_XPSS       FALSE
1384   #endif
1385 #endif
1386
1387 #ifdef BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT
1388   #if  BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT  == TRUE
1389     #undef  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
1390     #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT    FALSE
1391   #endif
1392 #endif
1393
1394 #ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
1395   #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
1396     #undef  CFG_ACPI_PSTATE_PSD_INDPX
1397     #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
1398   #endif
1399 #endif
1400
1401 #ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
1402   #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
1403     #undef  CFG_VRM_HIGH_SPEED_ENABLE
1404     #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
1405   #endif
1406 #endif
1407
1408 #ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
1409   #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
1410     #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
1411     #define CFG_VRM_NB_HIGH_SPEED_ENABLE    TRUE
1412   #endif
1413 #endif
1414
1415 #ifdef BLDCFG_STARTING_BUSNUM
1416   #define CFG_STARTING_BUSNUM         (BLDCFG_STARTING_BUSNUM)
1417 #else
1418   #define CFG_STARTING_BUSNUM         (0)
1419 #endif
1420
1421 #ifdef BLDCFG_AMD_PLATFORM_TYPE
1422   #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
1423 #else
1424   #define CFG_AMD_PLATFORM_TYPE              0
1425 #endif
1426
1427 CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
1428
1429 #ifdef BLDCFG_MAXIMUM_BUSNUM
1430   #define CFG_MAXIMUM_BUSNUM          (BLDCFG_MAXIMUM_BUSNUM)
1431 #else
1432   #define CFG_MAXIMUM_BUSNUM          (0xF8)
1433 #endif
1434
1435 #ifdef BLDCFG_ALLOCATED_BUSNUM
1436   #define CFG_ALLOCATED_BUSNUM        (BLDCFG_ALLOCATED_BUSNUM)
1437 #else
1438   #define CFG_ALLOCATED_BUSNUM        (0x20)
1439 #endif
1440
1441 #ifdef BLDCFG_BUID_SWAP_LIST
1442   #define CFG_BUID_SWAP_LIST         (BLDCFG_BUID_SWAP_LIST)
1443 #else
1444   #define CFG_BUID_SWAP_LIST         (NULL)
1445 #endif
1446
1447 #ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
1448   #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
1449 #else
1450   #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (NULL)
1451 #endif
1452
1453 #ifdef BLDCFG_HTFABRIC_LIMITS_LIST
1454   #define CFG_HTFABRIC_LIMITS_LIST         (BLDCFG_HTFABRIC_LIMITS_LIST)
1455 #else
1456   #define CFG_HTFABRIC_LIMITS_LIST         (NULL)
1457 #endif
1458
1459 #ifdef BLDCFG_HTCHAIN_LIMITS_LIST
1460   #define CFG_HTCHAIN_LIMITS_LIST         (BLDCFG_HTCHAIN_LIMITS_LIST)
1461 #else
1462   #define CFG_HTCHAIN_LIMITS_LIST         (NULL)
1463 #endif
1464
1465 #ifdef BLDCFG_BUS_NUMBERS_LIST
1466   #define CFG_BUS_NUMBERS_LIST         (BLDCFG_BUS_NUMBERS_LIST)
1467 #else
1468   #define CFG_BUS_NUMBERS_LIST         (NULL)
1469 #endif
1470
1471 #ifdef BLDCFG_IGNORE_LINK_LIST
1472   #define CFG_IGNORE_LINK_LIST         (BLDCFG_IGNORE_LINK_LIST)
1473 #else
1474   #define CFG_IGNORE_LINK_LIST         (NULL)
1475 #endif
1476
1477 #ifdef BLDCFG_LINK_SKIP_REGANG_LIST
1478   #define CFG_LINK_SKIP_REGANG_LIST         (BLDCFG_LINK_SKIP_REGANG_LIST)
1479 #else
1480   #define CFG_LINK_SKIP_REGANG_LIST         (NULL)
1481 #endif
1482
1483 #ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
1484   #define CFG_SET_HTCRC_SYNC_FLOOD         (BLDCFG_SET_HTCRC_SYNC_FLOOD)
1485 #else
1486   #define CFG_SET_HTCRC_SYNC_FLOOD         (FALSE)
1487 #endif
1488
1489 #ifdef BLDCFG_USE_UNIT_ID_CLUMPING
1490   #define CFG_USE_UNIT_ID_CLUMPING         (BLDCFG_USE_UNIT_ID_CLUMPING)
1491 #else
1492   #define CFG_USE_UNIT_ID_CLUMPING         (FALSE)
1493 #endif
1494
1495 #ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
1496   #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
1497 #else
1498   #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (NULL)
1499 #endif
1500
1501 #ifdef BLDCFG_USE_HT_ASSIST
1502   #define CFG_USE_HT_ASSIST               (BLDCFG_USE_HT_ASSIST)
1503 #else
1504   #define CFG_USE_HT_ASSIST               (TRUE)
1505 #endif
1506
1507 #ifdef BLDCFG_USE_ATM_MODE
1508   #define CFG_USE_ATM_MODE                (BLDCFG_USE_ATM_MODE)
1509 #else
1510   #define CFG_USE_ATM_MODE                (TRUE)
1511 #endif
1512
1513 #ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
1514   #define CFG_PLATFORM_CONTROL_FLOW_MODE  (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
1515 #else
1516   #define CFG_PLATFORM_CONTROL_FLOW_MODE  (Nfcm)
1517 #endif
1518
1519 #ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
1520   #define CFG_PLATFORM_DEEMPHASIS_LIST  (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
1521 #else
1522   #define CFG_PLATFORM_DEEMPHASIS_LIST  (NULL)
1523 #endif
1524
1525 #ifdef BLDCFG_VRM_ADDITIONAL_DELAY
1526   #define CFG_VRM_ADDITIONAL_DELAY      (BLDCFG_VRM_ADDITIONAL_DELAY)
1527 #else
1528   #define CFG_VRM_ADDITIONAL_DELAY      (0)
1529 #endif
1530
1531 #ifdef BLDCFG_VRM_CURRENT_LIMIT
1532   #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
1533 #else
1534   #define CFG_VRM_CURRENT_LIMIT            0
1535 #endif
1536
1537 #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
1538   #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
1539 #else
1540   #define CFG_VRM_LOW_POWER_THRESHOLD      0
1541 #endif
1542
1543 #ifdef BLDCFG_VRM_SLEW_RATE
1544   #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
1545 #else
1546   #define CFG_VRM_SLEW_RATE                DFLT_VRM_SLEW_RATE
1547 #endif
1548
1549 #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1550   #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1551 #else
1552   #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
1553 #endif
1554
1555 #ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
1556   #define CFG_VRM_NB_ADDITIONAL_DELAY      (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
1557 #else
1558   #define CFG_VRM_NB_ADDITIONAL_DELAY      (0)
1559 #endif
1560
1561 #ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
1562   #define CFG_VRM_NB_CURRENT_LIMIT         BLDCFG_VRM_NB_CURRENT_LIMIT
1563 #else
1564   #define CFG_VRM_NB_CURRENT_LIMIT         (0)
1565 #endif
1566
1567 #ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1568   #define CFG_VRM_NB_LOW_POWER_THRESHOLD   BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1569 #else
1570   #define CFG_VRM_NB_LOW_POWER_THRESHOLD   (0)
1571 #endif
1572
1573 #ifdef BLDCFG_VRM_NB_SLEW_RATE
1574   #define CFG_VRM_NB_SLEW_RATE             BLDCFG_VRM_NB_SLEW_RATE
1575 #else
1576   #define CFG_VRM_NB_SLEW_RATE             DFLT_VRM_SLEW_RATE
1577 #endif
1578
1579 #ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1580   #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT  BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1581 #else
1582   #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT  (0)
1583 #endif
1584
1585
1586 #ifdef BLDCFG_PLAT_NUM_IO_APICS
1587   #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
1588 #else
1589   #define CFG_PLAT_NUM_IO_APICS            0
1590 #endif
1591
1592 #ifdef BLDCFG_MEM_INIT_PSTATE
1593   #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
1594 #else
1595   #define CFG_MEM_INIT_PSTATE              0
1596 #endif
1597
1598 #ifdef BLDCFG_PLATFORM_C1E_MODE
1599   #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
1600 #else
1601   #define CFG_C1E_MODE                        C1eModeDisabled
1602 #endif
1603
1604 #ifdef BLDCFG_PLATFORM_C1E_OPDATA
1605   #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
1606 #else
1607   #define CFG_C1E_OPDATA                      0
1608 #endif
1609
1610 #ifdef BLDCFG_PLATFORM_C1E_OPDATA1
1611   #define CFG_C1E_OPDATA1                     BLDCFG_PLATFORM_C1E_OPDATA1
1612 #else
1613   #define CFG_C1E_OPDATA1                     0
1614 #endif
1615
1616 #ifdef BLDCFG_PLATFORM_C1E_OPDATA2
1617   #define CFG_C1E_OPDATA2                     BLDCFG_PLATFORM_C1E_OPDATA2
1618 #else
1619   #define CFG_C1E_OPDATA2                     0
1620 #endif
1621
1622 #ifdef BLDCFG_PLATFORM_C1E_OPDATA3
1623   #define CFG_C1E_OPDATA3                     BLDCFG_PLATFORM_C1E_OPDATA3
1624 #else
1625   #define CFG_C1E_OPDATA3                     0
1626 #endif
1627
1628 #ifdef BLDCFG_PLATFORM_CSTATE_MODE
1629   #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
1630 #else
1631   #define CFG_CSTATE_MODE                     CStateModeDisabled
1632 #endif
1633
1634 #ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
1635   #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
1636 #else
1637   #define CFG_CSTATE_OPDATA                   0
1638 #endif
1639
1640 #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1641   #define CFG_CSTATE_IO_BASE_ADDRESS       BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1642 #else
1643   #define CFG_CSTATE_IO_BASE_ADDRESS       0
1644 #endif
1645
1646 #ifdef BLDCFG_PLATFORM_CPB_MODE
1647   #define CFG_CPB_MODE                        BLDCFG_PLATFORM_CPB_MODE
1648 #else
1649   #define CFG_CPB_MODE                        CpbModeAuto
1650 #endif
1651
1652 #ifdef BLDCFG_CORE_LEVELING_MODE
1653   #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
1654 #else
1655   #define CFG_CORE_LEVELING_MODE           0
1656 #endif
1657
1658 #ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
1659   #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
1660 #else
1661   #define CFG_AMD_PSTATE_CAP_VALUE           0
1662 #endif
1663
1664 #ifdef BLDCFG_HEAP_DRAM_ADDRESS
1665   #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
1666 #else
1667   #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
1668 #endif
1669
1670 #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1671   #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1672 #else
1673   #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
1674 #endif
1675
1676 #ifdef BLDCFG_MEMORY_MODE_UNGANGED
1677   #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
1678 #else
1679   #define CFG_MEMORY_MODE_UNGANGED              TRUE
1680 #endif
1681
1682 #ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1683   #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1684 #else
1685   #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
1686 #endif
1687
1688 #ifdef BLDCFG_MEMORY_QUADRANK_TYPE
1689   #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
1690 #else
1691   #define CFG_MEMORY_QUADRANK_TYPE              DFLT_MEMORY_QUADRANK_TYPE
1692 #endif
1693
1694 #ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
1695   #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
1696 #else
1697   #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
1698 #endif
1699
1700 #ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
1701   #define CFG_MEMORY_LRDIMM_CAPABLE              BLDCFG_MEMORY_LRDIMM_CAPABLE
1702 #else
1703   #define CFG_MEMORY_LRDIMM_CAPABLE              TRUE
1704 #endif
1705
1706 #ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
1707   #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
1708 #else
1709   #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
1710 #endif
1711
1712 #ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
1713   #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
1714 #else
1715   #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
1716 #endif
1717
1718 #ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1719   #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1720 #else
1721   #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
1722 #endif
1723
1724 #ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1725   #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1726 #else
1727   #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
1728 #endif
1729
1730 #ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1731   #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1732 #else
1733   #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
1734 #endif
1735
1736 #ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1737   #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1738 #else
1739   #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
1740 #endif
1741
1742 #ifdef BLDCFG_MEMORY_POWER_DOWN
1743   #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
1744 #else
1745   #define CFG_MEMORY_POWER_DOWN                 FALSE
1746 #endif
1747
1748 #ifdef BLDCFG_POWER_DOWN_MODE
1749   #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
1750 #else
1751   #define CFG_POWER_DOWN_MODE                   POWER_DOWN_MODE_AUTO
1752 #endif
1753
1754 #ifdef BLDCFG_ONLINE_SPARE
1755   #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
1756 #else
1757   #define CFG_ONLINE_SPARE                      FALSE
1758 #endif
1759
1760 #ifdef BLDCFG_MEMORY_PARITY_ENABLE
1761   #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
1762 #else
1763   #define CFG_MEMORY_PARITY_ENABLE              FALSE
1764 #endif
1765
1766 #ifdef BLDCFG_BANK_SWIZZLE
1767   #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
1768 #else
1769   #define CFG_BANK_SWIZZLE                      TRUE
1770 #endif
1771
1772 #ifdef BLDCFG_TIMING_MODE_SELECT
1773   #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
1774 #else
1775   #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
1776 #endif
1777
1778 #ifdef BLDCFG_MEMORY_CLOCK_SELECT
1779   #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
1780 #else
1781   #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
1782 #endif
1783
1784 #ifdef BLDCFG_DQS_TRAINING_CONTROL
1785   #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
1786 #else
1787   #define CFG_DQS_TRAINING_CONTROL              TRUE
1788 #endif
1789
1790 #ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1791   #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
1792 #else
1793   #define CFG_IGNORE_SPD_CHECKSUM               FALSE
1794 #endif
1795
1796 #ifdef BLDCFG_USE_BURST_MODE
1797   #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
1798 #else
1799   #define CFG_USE_BURST_MODE                    FALSE
1800 #endif
1801
1802 #ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1803   #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
1804 #else
1805   #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
1806 #endif
1807
1808 #ifdef BLDCFG_ENABLE_ECC_FEATURE
1809   #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
1810 #else
1811   #define CFG_ENABLE_ECC_FEATURE                TRUE
1812 #endif
1813
1814 #ifdef BLDCFG_ECC_REDIRECTION
1815   #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
1816 #else
1817   #define CFG_ECC_REDIRECTION                   FALSE
1818 #endif
1819
1820 #ifdef BLDCFG_SCRUB_DRAM_RATE
1821   #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
1822 #else
1823   #define CFG_SCRUB_DRAM_RATE         DFLT_SCRUB_DRAM_RATE
1824 #endif
1825
1826 #ifdef BLDCFG_SCRUB_L2_RATE
1827   #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
1828 #else
1829   #define CFG_SCRUB_L2_RATE           DFLT_SCRUB_L2_RATE
1830 #endif
1831
1832 #ifdef BLDCFG_SCRUB_L3_RATE
1833   #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
1834 #else
1835   #define CFG_SCRUB_L3_RATE           DFLT_SCRUB_L3_RATE
1836 #endif
1837
1838 #ifdef BLDCFG_SCRUB_IC_RATE
1839   #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
1840 #else
1841   #define CFG_SCRUB_IC_RATE           DFLT_SCRUB_IC_RATE
1842 #endif
1843
1844 #ifdef BLDCFG_SCRUB_DC_RATE
1845   #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
1846 #else
1847   #define CFG_SCRUB_DC_RATE           DFLT_SCRUB_DC_RATE
1848 #endif
1849
1850 #ifdef BLDCFG_ECC_SYNC_FLOOD
1851   #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
1852 #else
1853   #define CFG_ECC_SYNC_FLOOD          TRUE
1854 #endif
1855
1856 #ifdef BLDCFG_ECC_SYMBOL_SIZE
1857   #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
1858 #else
1859   #define CFG_ECC_SYMBOL_SIZE         0
1860 #endif
1861
1862 #ifdef BLDCFG_1GB_ALIGN
1863   #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
1864 #else
1865   #define CFG_1GB_ALIGN               FALSE
1866 #endif
1867
1868 #ifdef BLDCFG_UMA_ALLOCATION_MODE
1869   #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
1870 #else
1871   #define CFG_UMA_MODE                UMA_AUTO
1872 #endif
1873
1874 #ifdef BLDCFG_UMA_ALLOCATION_SIZE
1875   #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
1876 #else
1877   #define CFG_UMA_SIZE                0
1878 #endif
1879
1880 #ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1881   #define CFG_UMA_ABOVE4G           BLDCFG_UMA_ABOVE4G_SUPPORT
1882 #else
1883   #define CFG_UMA_ABOVE4G           FALSE
1884 #endif
1885
1886 #ifdef BLDCFG_UMA_ALIGNMENT
1887   #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
1888 #else
1889   #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
1890 #endif
1891
1892 #ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1893   #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
1894 #else
1895   #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
1896 #endif
1897
1898 #ifdef BLDCFG_S3_LATE_RESTORE
1899   #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
1900 #else
1901   #define CFG_S3_LATE_RESTORE         TRUE
1902 #endif
1903
1904 #ifdef BLDCFG_USE_32_BYTE_REFRESH
1905   #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
1906 #else
1907   #define CFG_USE_32_BYTE_REFRESH  (FALSE)
1908 #endif
1909
1910 #ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1911   #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1912 #else
1913   #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
1914 #endif
1915
1916 #ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1917   #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
1918 #else
1919   #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
1920 #endif
1921
1922 #ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1923   #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
1924 #else
1925   #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
1926 #endif
1927
1928 #ifdef BLDCFG_CFG_GNB_HD_AUDIO
1929   #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
1930 #else
1931   #define CFG_GNB_HD_AUDIO                   TRUE
1932 #endif
1933
1934 #ifdef BLDCFG_CFG_ABM_SUPPORT
1935   #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
1936 #else
1937   #define CFG_ABM_SUPPORT                    FALSE
1938 #endif
1939
1940 #ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1941   #define CFG_DINAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1942 #else
1943   #define CFG_DYNAMIC_REFRESH_RATE           0
1944 #endif
1945
1946 #ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1947   #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1948 #else
1949   #define CFG_LCD_BACK_LIGHT_CONTROL         0
1950 #endif
1951
1952 #ifdef BLDCFG_STEREO_3D_PINOUT
1953   #define CFG_GNB_STEREO_3D_PINOUT           BLDCFG_STEREO_3D_PINOUT
1954 #else
1955   #define CFG_GNB_STEREO_3D_PINOUT           0
1956 #endif
1957
1958 #ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1959   #define CFG_GNB_IGPU_SSID                  BLDCFG_IGPU_SUBSYSTEM_ID
1960 #else
1961   #define CFG_GNB_IGPU_SSID                  0
1962 #endif
1963
1964 #ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1965   #define CFG_GNB_HDAUDIO_SSID               BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1966 #else
1967   #define CFG_GNB_HDAUDIO_SSID               0
1968 #endif
1969
1970 #ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1971   #define CFG_GNB_PCIE_SSID                  BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1972 #else
1973   #define CFG_GNB_PCIE_SSID                  0x12341022
1974 #endif
1975
1976 #ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1977   #define CFG_GFX_LVDS_SPREAD_SPECTRUM               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1978 #else
1979   #define CFG_GFX_LVDS_SPREAD_SPECTRUM               0
1980 #endif
1981
1982 #ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1983   #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1984 #else
1985   #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               0
1986 #endif
1987
1988 #ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1989   #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1990 #else
1991   #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               0
1992 #endif
1993
1994 #ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1995   #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1996 #else
1997   #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
1998 #endif
1999
2000 #ifdef BLDOPT_REMOVE_EARLY_SAMPLES
2001   #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
2002     #undef  OPTION_EARLY_SAMPLES
2003     #define OPTION_EARLY_SAMPLES        FALSE
2004   #else
2005     #undef  OPTION_EARLY_SAMPLES
2006     #define OPTION_EARLY_SAMPLES        TRUE
2007   #endif
2008 #endif
2009
2010 #ifdef BLDOPT_REMOVE_ALIB
2011   #if  BLDOPT_REMOVE_ALIB == TRUE
2012     #undef  OPTION_ALIB
2013     #define OPTION_ALIB                 FALSE
2014   #else
2015     #undef  OPTION_ALIB
2016     #define OPTION_ALIB                 TRUE
2017   #endif
2018 #endif
2019
2020 #ifdef BLDCFG_IOMMU_SUPPORT
2021   #define CFG_IOMMU_SUPPORT             BLDCFG_IOMMU_SUPPORT
2022 #else
2023   #define CFG_IOMMU_SUPPORT             TRUE
2024 #endif
2025
2026 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
2027   #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE             BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
2028 #else
2029   #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE             0
2030 #endif
2031
2032 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
2033   #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL           BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
2034 #else
2035   #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL           0
2036 #endif
2037
2038 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
2039   #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON             BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
2040 #else
2041   #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON             0
2042 #endif
2043
2044 #ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
2045   #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE          BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
2046 #else
2047   #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE          0
2048 #endif
2049
2050 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
2051   #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY         BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
2052 #else
2053   #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY         0
2054 #endif
2055
2056 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
2057   #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
2058 #else
2059   #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         0
2060 #endif
2061
2062 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
2063   #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
2064 #else
2065   #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         0
2066 #endif
2067
2068 #ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
2069   #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ             BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
2070 #else
2071   #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ             0
2072 #endif
2073
2074 #ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
2075   #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE           BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
2076 #else
2077   #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE           0
2078 #endif
2079
2080
2081 // BLDCFG_LVDS_24BBP_PANEL_MODE
2082 // This specifies the LVDS 24 BBP mode.
2083 // 0 - Use LDI mode (default).
2084 // 1 - Use FPDI mode.
2085 #ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
2086   #define CFG_LVDS_24BBP_PANEL_MODE                 BLDCFG_LVDS_24BBP_PANEL_MODE
2087 #else
2088   #define CFG_LVDS_24BBP_PANEL_MODE                 0
2089 #endif
2090 /*---------------------------------------------------------------------------
2091  *       Processing the options:  Third, perform the option cross checks
2092  *--------------------------------------------------------------------------*/
2093 // Assure that at least one type of memory support is included
2094 #if OPTION_UDIMMS == FALSE
2095   #if OPTION_RDIMMS == FALSE
2096     #if OPTION_SODIMMS == FALSE
2097       #if OPTION_LRDIMMS == FALSE
2098         #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
2099       #endif
2100     #endif
2101   #endif
2102 #endif
2103 // Ensure at least one dimm type is capable
2104 #if CFG_MEMORY_RDIMM_CAPABLE == FALSE
2105   #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
2106     #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
2107       #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2108         #error   BLDCFG: No dimm type is capable
2109       #endif
2110     #endif
2111   #endif
2112 #endif
2113 // Check LRDIMM CODE and LRDIMM CFG item
2114 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2115   #if  BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
2116     #error   Warning: LRDIMM capability is false, but LRIDMM support code included
2117   #endif
2118 #endif
2119 //  Turn off multi-socket based features if only one node...
2120 #if OPTION_MULTISOCKET == FALSE
2121   #undef  OPTION_PARALLEL_TRAINING
2122   #define OPTION_PARALLEL_TRAINING    FALSE
2123   #undef  OPTION_NODE_INTERLEAVE
2124   #define OPTION_NODE_INTERLEAVE      FALSE
2125 #endif
2126 // Ensure that at least one write leveling option is selected
2127 #if OPTION_DDR3 == TRUE
2128   #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
2129     #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
2130       #error  No Write leveling option selected for DDR3
2131     #endif
2132   #endif
2133   #if OPTION_SW_DRAM_INIT == FALSE
2134     #error   Software dram init must be enabled for DDR3 dimms
2135   #endif
2136 #endif
2137 // Ensure at least one DQS receiver training option is selected
2138 #if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
2139   #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2140     #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2141       #error    No DQS receiver training option has been slected
2142     #endif
2143   #endif
2144 #endif
2145 // Ensure at least one Rd Wr position training option has been selected
2146 #if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
2147   #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
2148     #error    No Rd Wr position training option has been selected
2149   #endif
2150 #endif
2151 // Ensure at least one dram init option has been selected
2152 #if OPTION_HW_DRAM_INIT == FALSE
2153   #if OPTION_SW_DRAM_INIT == FALSE
2154     #error    No Dram init option has been selected
2155   #endif
2156 #endif
2157 /* As an ENUM, DDRXXX_FREQUENCY is not defined when the c preprocessor runs.
2158  * Removing this test for coreboot.
2159  */
2160 #if RUN_BROKEN_AGESA_TESTS
2161 // Ensure the frequency limit is valid
2162 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
2163   #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
2164     #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
2165       #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
2166         #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
2167           #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
2168             #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
2169               #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
2170                 #error    BLDCFG: Unsupported memory bus frequency
2171               #endif
2172             #endif
2173           #endif
2174         #endif
2175       #endif
2176     #endif
2177   #endif
2178 #endif
2179
2180 #endif
2181 /* As an ENUM, TIMING_MODE_XXX is not defined when the c preprocessor runs.
2182  * Removing this test for coreboot.
2183  */
2184 #if RUN_BROKEN_AGESA_TESTS
2185
2186 // Ensure timing mode is valid
2187 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
2188   #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
2189     #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
2190       #error    BLDCFG: Invalid timing mode is set
2191     #endif
2192   #endif
2193 #endif
2194
2195 #endif
2196 // Ensure the scrub rate is valid
2197 #if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
2198   #error    BLDCFG: Unsupported dram scrub rate set
2199 #endif
2200 #if CFG_SCRUB_L2_RATE > 0x16
2201   #error   BLDCFG: Unsupported L2 scrubber rate set
2202 #endif
2203 #if CFG_SCRUB_L3_RATE > 0x16
2204   #error   BLDCFG: unsupported L3 scrubber rate set
2205 #endif
2206 #if CFG_SCRUB_IC_RATE > 0x16
2207   #error    BLDCFG: Unsupported Instruction cache scrub rate set
2208 #endif
2209 #if CFG_SCRUB_DC_RATE > 0x16
2210   #error   BLDCFG: Unsupported Dcache scrub rate set
2211 #endif
2212 /* As an ENUM, QUADRANK_XXX is not defined when the c preprocessor runs.
2213  * Removing this test for coreboot.
2214  */
2215 #if RUN_BROKEN_AGESA_TESTS
2216
2217 // Ensure Quad rank dimm type is valid
2218 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
2219   #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
2220     #error     BLDCFG: Invalid quad rank dimm type set
2221   #endif
2222 #endif
2223
2224 #endif
2225 // Ensure ECC symbol size is valid
2226 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
2227   #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
2228     #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
2229       #error   BLDCFG: Invalid Ecc symbol size set
2230     #endif
2231   #endif
2232 #endif
2233 /* As an ENUM, POWER_DOWN_BY_XXX is not defined when the c preprocessor runs.
2234  * Removing this test for coreboot.
2235  */
2236 #if RUN_BROKEN_AGESA_TESTS
2237
2238 // Ensure power down mode is valid
2239 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
2240   #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
2241     #error     BLDCFG: Invalid power down mode set
2242   #endif
2243 #endif
2244
2245 #endif
2246 /*****************************************************************************
2247  *
2248  * Process the option logic, setting local control variables
2249  *
2250  ****************************************************************************/
2251 #if OPTION_ACPI_PSTATES == TRUE
2252   #define OPTFCN_ACPI_TABLES           CreateAcpiTablesMain
2253   #define OPTFCN_GATHER_DATA           PStateGatherData
2254   #if OPTION_MULTISOCKET == TRUE
2255     #define OPTFCN_PSTATE_LEVELING     PStateLeveling
2256   #else
2257     #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
2258   #endif
2259 #else
2260   #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
2261   #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
2262   #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
2263 #endif
2264
2265
2266 /*****************************************************************************
2267  *
2268  * Include the structure definitions for the defaults table structures
2269  *
2270  ****************************************************************************/
2271 #include  "Options.h"
2272 #include  "OptionCpuFamiliesInstall.h"
2273 #include  "OptionsHt.h"
2274 #include  "OptionHtInstall.h"
2275 #include  "OptionMemory.h"
2276 #include  "PlatformMemoryConfiguration.h"
2277 #include  "OptionMemoryInstall.h"
2278 #include  "OptionMemoryRecovery.h"
2279 #include  "OptionMemoryRecoveryInstall.h"
2280 #include  "OptionCpuFeaturesInstall.h"
2281 #include  "OptionDmi.h"
2282 #include  "OptionDmiInstall.h"
2283 #include  "OptionPstate.h"
2284 #include  "OptionPstateInstall.h"
2285 #include  "OptionWhea.h"
2286 #include  "OptionWheaInstall.h"
2287 #include  "OptionSrat.h"
2288 #include  "OptionSratInstall.h"
2289 #include  "OptionSlit.h"
2290 #include  "OptionSlitInstall.h"
2291 #include  "OptionMultiSocket.h"
2292 #include  "OptionMultiSocketInstall.h"
2293 #include  "OptionIdsInstall.h"
2294 #include  "OptionGfxRecovery.h"
2295 #include  "OptionGfxRecoveryInstall.h"
2296 #include  "OptionGnb.h"
2297 #include  "OptionGnbInstall.h"
2298 #include  "OptionS3ScriptInstall.h"
2299 #include  "OptionFchInstall.h"
2300
2301
2302 /*****************************************************************************
2303  *
2304  *  Generate the output structures (defaults tables)
2305  *
2306  ****************************************************************************/
2307 BUILD_OPT_CFG UserOptions = {
2308   {                                             // AGESA version string
2309     AGESA_CODE_SIGNATURE,                       //    code header Signature
2310     AGESA_PACKAGE_STRING,                       //    8 character ID
2311     AGESA_VERSION_STRING,                       //    12 character version string
2312     0                                           //    null string terminator
2313   },
2314   //Build Option Area
2315   OPTION_UDIMMS,                        //UDIMMS
2316   OPTION_RDIMMS,                        //RDIMMS
2317   OPTION_LRDIMMS,                       //LRDIMMS
2318   OPTION_ECC,                           //ECC
2319   OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
2320   OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
2321   OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
2322   OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
2323   OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
2324   OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
2325   OPTION_MULTISOCKET,                   //MULTISOCKET
2326   OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
2327   OPTION_SRAT,                          //SRAT
2328   OPTION_SLIT,                          //SLIT
2329   OPTION_WHEA,                          //WHEA
2330   OPTION_DMI,                           //DMI
2331   OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
2332   OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
2333
2334   //Build Configuration Area
2335   CFG_PCI_MMIO_BASE,
2336   CFG_PCI_MMIO_SIZE,
2337   {
2338     // CoreVrm
2339     {
2340       CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
2341       CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
2342       CFG_VRM_SLEW_RATE,                  // VrmSlewRate
2343       CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
2344       CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
2345       CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
2346     },
2347     // NbVrm
2348     {
2349       CFG_VRM_NB_CURRENT_LIMIT,           // VrmNbCurrentLimit
2350       CFG_VRM_NB_LOW_POWER_THRESHOLD,     // VrmNbLowPowerThershold
2351       CFG_VRM_NB_SLEW_RATE,               // VrmNbSlewRate
2352       CFG_VRM_NB_ADDITIONAL_DELAY,        // VrmNbAdditionalDelay
2353       CFG_VRM_NB_HIGH_SPEED_ENABLE,       // VrmNbHiSpeedEnable
2354       CFG_VRM_NB_INRUSH_CURRENT_LIMIT     // VrmNbInrushCurrentLimit
2355     }
2356   },
2357   CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
2358   CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
2359   CFG_C1E_MODE,                         //C1eMode
2360   CFG_C1E_OPDATA,                       //C1ePlatformData
2361   CFG_C1E_OPDATA1,                      //C1ePlatformData1
2362   CFG_C1E_OPDATA2,                      //C1ePlatformData2
2363   CFG_C1E_OPDATA3,                      //C1ePlatformData3
2364   CFG_CSTATE_MODE,                      //CStateMode
2365   CFG_CSTATE_OPDATA,                    //CStatePlatformData
2366   CFG_CSTATE_IO_BASE_ADDRESS,           //CStateIoBaseAddress
2367   CFG_CPB_MODE,                         //CpbMode
2368   CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
2369   {
2370     CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
2371     CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
2372     CFG_USE_ATM_MODE,                     // CfgUseAtmMode
2373     CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
2374     CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
2375     CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
2376   },
2377   (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,         // Deemphasis settings
2378   CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
2379   CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
2380
2381   CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
2382   CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
2383   CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
2384   CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
2385   CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
2386   CFG_MEMORY_LRDIMM_CAPABLE,            // CfgMemoryLRDimmCapable
2387   CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
2388   CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
2389   CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
2390   CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
2391   CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
2392   CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
2393   CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
2394   CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
2395   CFG_ONLINE_SPARE,                     // CfgOnlineSpare
2396   CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
2397   CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
2398   CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
2399   CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
2400   CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
2401   CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
2402   CFG_USE_BURST_MODE,                   // CfgUseBurstMode
2403   CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
2404   CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
2405   CFG_ECC_REDIRECTION,                  // CfgEccRedirection
2406   CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
2407   CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
2408   CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
2409   CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
2410   CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
2411   CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
2412   CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
2413   CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
2414   CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
2415   CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
2416   CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
2417   (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
2418   CFG_UMA_MODE,                         // CfgUmaMode
2419   CFG_UMA_SIZE,                         // CfgUmaSize
2420   CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
2421   CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
2422   CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
2423   CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
2424   CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
2425   CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
2426   CFG_ABM_SUPPORT,                      // CfgAbmSupport
2427   CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
2428   CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
2429   CFG_GNB_STEREO_3D_PINOUT,             // CfgGnb3dStereoPinIndex
2430   CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
2431   CFG_GNB_IGPU_SSID,                    // CfgGnbIGPUSSID
2432   CFG_GNB_HDAUDIO_SSID,                 // CfgGnbHDAudioSSID
2433   CFG_GNB_PCIE_SSID,                    // CfgGnbPcieSSID
2434   CFG_GFX_LVDS_SPREAD_SPECTRUM,         // CfgLvdsSpreadSpectrum
2435   CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE,    // CfgLvdsSpreadSpectrumRate
2436
2437   CFG_SMBUS0_BASE_ADDRESS,              // CfgSmbus0BaseAddress
2438   CFG_SMBUS1_BASE_ADDRESS,              // CfgSmbus1BaseAddress
2439   CFG_SIO_PME_BASE_ADDRESS,             // CfgSioPmeBaseAddress
2440   CFG_ACPI_PM1_EVT_BLOCK_ADDRESS,       // CfgAcpiPm1EvtBlkAddr
2441   CFG_ACPI_PM1_CNT_BLOCK_ADDRESS,       // CfgAcpiPm1CntBlkAddr
2442   CFG_ACPI_PM_TMR_BLOCK_ADDRESS,        // CfgAcpiPmTmrBlkAddr
2443   CFG_ACPI_CPU_CNT_BLOCK_ADDRESS,       // CfgCpuControlBlkAddr
2444   CFG_ACPI_GPE0_BLOCK_ADDRESS,          // CfgAcpiGpe0BlkAddr
2445   CFG_SMI_CMD_PORT_ADDRESS,             // CfgSmiCmdPortAddr
2446   CFG_ACPI_PMA_CNTBLK_ADDRESS,          // CfgAcpiPmaCntBlkAddr
2447   CFG_GEC_SHADOW_ROM_BASE,              // CfgGecShadowRomBase
2448   CFG_WATCHDOG_TIMER_BASE,              // CfgWatchDogTimerBase
2449   CFG_SPI_ROM_BASE_ADDRESS,             // CfgSpiRomBaseAddress
2450   CFG_HPET_BASE_ADDRESS,                // CfgHpetBaseAddress
2451   CFG_AZALIA_SSID,                      // CfgAzaliaSsid
2452   CFG_SMBUS_SSID,                       // CfgSmbusSsid
2453   CFG_IDE_SSID,                         // CfgIdeSsid
2454   CFG_SATA_AHCI_SSID,                   // CfgSataAhciSsid
2455   CFG_SATA_IDE_SSID,                    // CfgSataIdeSsid
2456   CFG_SATA_RAID5_SSID,                  // CfgSataRaid5Ssid
2457   CFG_SATA_RAID_SSID,                   // CfgSataRaidSsid
2458   CFG_EHCI_SSID,                        // CfgEhcidSsid
2459   CFG_OHCI_SSID,                        // CfgOhcidSsid
2460   CFG_LPC_SSID,                         // CfgLpcSsid
2461   CFG_FCH_GPP_LINK_CONFIG,              // CfgFchGppLinkConfig
2462   CFG_FCH_GPP_PORT0_PRESENT,            // CfgFchGppPort0Present
2463   CFG_FCH_GPP_PORT1_PRESENT,            // CfgFchGppPort1Present
2464   CFG_FCH_GPP_PORT2_PRESENT,            // CfgFchGppPort2Present
2465   CFG_FCH_GPP_PORT3_PRESENT,            // CfgFchGppPort3Present
2466   CFG_FCH_GPP_PORT0_HOTPLUG,            // CfgFchGppPort0HotPlug
2467   CFG_FCH_GPP_PORT1_HOTPLUG,            // CfgFchGppPort1HotPlug
2468   CFG_FCH_GPP_PORT2_HOTPLUG,            // CfgFchGppPort2HotPlug
2469   CFG_FCH_GPP_PORT3_HOTPLUG,            // CfgFchGppPort3HotPlug
2470
2471
2472   CFG_IOMMU_SUPPORT,                    // CfgIommuSupport
2473   CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE,    // CfgLvdsPowerOnSeqDigonToDe
2474   CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL,  // CfgLvdsPowerOnSeqDeToVaryBl
2475   CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON,    // CfgLvdsPowerOnSeqDeToDigon
2476   CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe
2477   CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay
2478   CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon
2479   CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl
2480   CFG_LVDS_MAX_PIXEL_CLOCK_FREQ,        // CfgLvdsMaxPixelClockFreq
2481   CFG_LCD_BIT_DEPTH_CONTROL_VALUE,      // CfgLcdBitDepthControlValue
2482   CFG_LVDS_24BBP_PANEL_MODE,            // CfgLvds24bbpPanelMode
2483   CFG_PCIE_REFCLK_SPREAD_SPECTRUM,      // CfgPcieRefClkSpreadSpectrum
2484   0,                                    //reserved...
2485 };
2486
2487 CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
2488 {
2489   #if AGESA_ENTRY_INIT_RESET == TRUE
2490     { AMD_INIT_RESET,
2491       sizeof (AMD_RESET_PARAMS),
2492       (PF_AGESA_FUNCTION) AmdInitResetConstructor,
2493       (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2494       AMD_INIT_RESET_HANDLE
2495     },
2496   #endif
2497
2498   #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2499     { AMD_INIT_RECOVERY,
2500       sizeof (AMD_RECOVERY_PARAMS),
2501       (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
2502       (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2503       AMD_INIT_POST_HANDLE
2504     },
2505   #endif
2506
2507   #if AGESA_ENTRY_INIT_EARLY == TRUE
2508     { AMD_INIT_EARLY,
2509       sizeof (AMD_EARLY_PARAMS),
2510       (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
2511       (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2512       AMD_INIT_EARLY_HANDLE
2513     },
2514   #endif
2515
2516   #if AGESA_ENTRY_INIT_ENV == TRUE
2517     { AMD_INIT_ENV,
2518       sizeof (AMD_ENV_PARAMS),
2519       (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
2520       (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2521       AMD_INIT_ENV_HANDLE
2522     },
2523   #endif
2524
2525   #if AGESA_ENTRY_INIT_LATE == TRUE
2526     { AMD_INIT_LATE,
2527       sizeof (AMD_LATE_PARAMS),
2528       (PF_AGESA_FUNCTION) AmdInitLateInitializer,
2529       (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
2530       AMD_INIT_LATE_HANDLE
2531     },
2532   #endif
2533
2534   #if AGESA_ENTRY_INIT_MID == TRUE
2535     { AMD_INIT_MID,
2536       sizeof (AMD_MID_PARAMS),
2537       (PF_AGESA_FUNCTION) AmdInitMidInitializer,
2538       (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2539       AMD_INIT_MID_HANDLE
2540     },
2541   #endif
2542
2543   #if AGESA_ENTRY_INIT_POST == TRUE
2544     { AMD_INIT_POST,
2545       sizeof (AMD_POST_PARAMS),
2546       (PF_AGESA_FUNCTION) AmdInitPostInitializer,
2547       (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
2548       AMD_INIT_POST_HANDLE
2549     },
2550   #endif
2551
2552   #if AGESA_ENTRY_INIT_RESUME == TRUE
2553     { AMD_INIT_RESUME,
2554       sizeof (AMD_RESUME_PARAMS),
2555       (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
2556       (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
2557       AMD_INIT_RESUME_HANDLE
2558     },
2559   #endif
2560
2561   #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2562     { AMD_S3LATE_RESTORE,
2563       sizeof (AMD_S3LATE_PARAMS),
2564       (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
2565       (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2566       AMD_S3_LATE_RESTORE_HANDLE
2567     },
2568   #endif
2569
2570   #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2571     { AMD_S3_SAVE,
2572       sizeof (AMD_S3SAVE_PARAMS),
2573       (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
2574       (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
2575       AMD_S3_SAVE_HANDLE
2576     },
2577   #endif
2578
2579   #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2580     { AMD_LATE_RUN_AP_TASK,
2581       sizeof (AP_EXE_PARAMS),
2582       (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
2583       (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2584       AMD_LATE_RUN_AP_TASK_HANDLE
2585     },
2586   #endif
2587   { 0, 0, NULL }
2588 };
2589
2590 CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
2591
2592 CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
2593 {
2594   { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
2595   { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
2596
2597   #if AGESA_ENTRY_INIT_RESET == TRUE
2598     { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
2599   #endif
2600
2601   #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2602     { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
2603   #endif
2604
2605   #if AGESA_ENTRY_INIT_EARLY == TRUE
2606     { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
2607   #endif
2608
2609   #if AGESA_ENTRY_INIT_POST == TRUE
2610     { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
2611   #endif
2612
2613   #if AGESA_ENTRY_INIT_ENV == TRUE
2614     { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
2615   #endif
2616
2617   #if AGESA_ENTRY_INIT_MID == TRUE
2618     { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
2619   #endif
2620
2621   #if AGESA_ENTRY_INIT_LATE == TRUE
2622     { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
2623   #endif
2624
2625   #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2626     { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
2627   #endif
2628
2629   #if AGESA_ENTRY_INIT_RESUME == TRUE
2630     { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
2631   #endif
2632
2633   #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2634     { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
2635   #endif
2636
2637   #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
2638     { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
2639     { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
2640     { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
2641     { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
2642     { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
2643     { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
2644   #endif
2645
2646   #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2647     { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
2648   #endif
2649   { 0, NULL }
2650 };
2651
2652 CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
2653 {
2654   IDS_LATE_RUN_AP_TASK
2655   // Get DMI info
2656   CPU_DMI_AP_GET_TYPE4_TYPE7
2657   // Probe filter enable
2658   L3_FEAT_AP_DISABLE_CACHE
2659   L3_FEAT_AP_ENABLE_CACHE
2660
2661   { 0, NULL }
2662 };
2663
2664 #if AGESA_ENTRY_INIT_EARLY == TRUE
2665   #if IDSOPT_IDS_ENABLED == TRUE
2666     #if IDSOPT_TRACING_ENABLED == TRUE
2667       #define MAKE_DBG_STR(x, y)  MAKE_AS_A_STRING(x : y)
2668       CONST CHAR8 *BldOptDebugOutput[] = {
2669         #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
2670           //Build Option Area
2671           MAKE_DBG_STR (\nOptUDIMM,             OPTION_UDIMMS)
2672           MAKE_DBG_STR (\nOptRDIMM,             OPTION_RDIMMS)
2673           MAKE_DBG_STR (\nOptLRDIMM,            OPTION_LRDIMMS)
2674           MAKE_DBG_STR (\nOptECC,               OPTION_ECC)
2675           MAKE_DBG_STR (\nOptCsIntlv,           OPTION_BANK_INTERLEAVE)
2676           MAKE_DBG_STR (\nOptDctIntlv,          OPTION_DCT_INTERLEAVE)
2677           MAKE_DBG_STR (\nOptNodeIntlv,         OPTION_NODE_INTERLEAVE)
2678           //MAKE_DBG_STR (\nOptParallelTraining,  OPTION_PARALLEL_TRAINING)
2679           MAKE_DBG_STR (\nOptOnlineSpare,       OPTION_ONLINE_SPARE)
2680           MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
2681           MAKE_DBG_STR (\nOptMemRestore,        OPTION_MEM_RESTORE)
2682           MAKE_DBG_STR (\nOptMultiSocket,       OPTION_MULTISOCKET)
2683           MAKE_DBG_STR (\nOptPstates,           OPTION_ACPI_PSTATES)
2684           MAKE_DBG_STR (\nOptSRAT,              OPTION_SRAT)
2685           MAKE_DBG_STR (\nOptSLIT,              OPTION_SLIT)
2686           MAKE_DBG_STR (\nOptWHEA,              OPTION_WHEA)
2687           MAKE_DBG_STR (\nOptDMI,               OPTION_DMI)
2688           MAKE_DBG_STR (\nOptEarlySamples,      OPTION_EARLY_SAMPLES),
2689
2690           //Build Configuration Area
2691           // CoreVrm
2692           MAKE_DBG_STR (\nVrmCurrentLimit      , CFG_VRM_CURRENT_LIMIT)
2693           MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
2694           MAKE_DBG_STR (\nVrmSlewRate          , CFG_VRM_SLEW_RATE)
2695           MAKE_DBG_STR (\nVrmAdditionalDelay   , CFG_VRM_ADDITIONAL_DELAY)
2696           MAKE_DBG_STR (\nVrmHiSpeedEnable     , CFG_VRM_HIGH_SPEED_ENABLE)
2697           MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
2698           // NbVrm
2699           MAKE_DBG_STR (\nNbVrmCurrentLimit      , CFG_VRM_NB_CURRENT_LIMIT)
2700           MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
2701           MAKE_DBG_STR (\nNbVrmSlewRate          , CFG_VRM_NB_SLEW_RATE)
2702           MAKE_DBG_STR (\nNbVrmAdditionalDelay   , CFG_VRM_NB_ADDITIONAL_DELAY)
2703           MAKE_DBG_STR (\nNbVrmHiSpeedEnable     , CFG_VRM_NB_HIGH_SPEED_ENABLE)
2704           MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
2705
2706           MAKE_DBG_STR (\nNumIoApics            , CFG_PLAT_NUM_IO_APICS)
2707           MAKE_DBG_STR (\nMemInitPstate         , CFG_MEM_INIT_PSTATE)
2708           MAKE_DBG_STR (\nC1eMode               , CFG_C1E_MODE)
2709           MAKE_DBG_STR (\nC1eOpData             , CFG_C1E_OPDATA)
2710           MAKE_DBG_STR (\nC1eOpdata1            , CFG_C1E_OPDATA1)
2711           MAKE_DBG_STR (\nC1eOpdata2            , CFG_C1E_OPDATA2)
2712           MAKE_DBG_STR (\nC1eOpdata3            , CFG_C1E_OPDATA3)
2713           MAKE_DBG_STR (\nCStateMode            , CFG_CSTATE_MODE)
2714           MAKE_DBG_STR (\nCStateOpData          , CFG_CSTATE_OPDATA)
2715           MAKE_DBG_STR (\nCStateIoBaseAddr      , CFG_CSTATE_IO_BASE_ADDRESS)
2716           MAKE_DBG_STR (\nCpbMode               , CFG_CPB_MODE)
2717           MAKE_DBG_STR (\nCoreLevelingMode      , CFG_CORE_LEVELING_MODE),
2718
2719           MAKE_DBG_STR (\nControlFlowMode       , CFG_PLATFORM_CONTROL_FLOW_MODE)
2720           MAKE_DBG_STR (\nUseHtAssist           , CFG_USE_HT_ASSIST)
2721           MAKE_DBG_STR (\nUseAtmMode            , CFG_USE_ATM_MODE)
2722           MAKE_DBG_STR (\nUse32ByteRefresh      , CFG_USE_32_BYTE_REFRESH)
2723           MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2724           MAKE_DBG_STR (\nPowerPolicy           , CFG_PLATFORM_POWER_POLICY_MOD)
2725
2726           MAKE_DBG_STR (\nDeemphasisList        , CFG_PLATFORM_DEEMPHASIS_LIST)
2727
2728           MAKE_DBG_STR (\nPciMmioAddr           , CFG_PCI_MMIO_BASE)
2729           MAKE_DBG_STR (\nPciMmioSize           , CFG_PCI_MMIO_SIZE)
2730           MAKE_DBG_STR (\nPlatformType          , CFG_AMD_PLATFORM_TYPE)
2731           MAKE_DBG_STR (\nPstateCapValue        , CFG_AMD_PSTATE_CAP_VALUE),
2732
2733           MAKE_DBG_STR (\nMemBusFreqLimit       , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2734           MAKE_DBG_STR (\nTimingModeSelect      , CFG_TIMING_MODE_SELECT)
2735           MAKE_DBG_STR (\nMemoryClockSelect     , CFG_MEMORY_CLOCK_SELECT)
2736
2737           MAKE_DBG_STR (\nMemUnganged           , CFG_MEMORY_MODE_UNGANGED)
2738           MAKE_DBG_STR (\nQRCap                 , CFG_MEMORY_QUAD_RANK_CAPABLE)
2739           MAKE_DBG_STR (\nQRType                , CFG_MEMORY_QUADRANK_TYPE)
2740           MAKE_DBG_STR (\nRDimmCap              , CFG_MEMORY_RDIMM_CAPABLE)
2741           MAKE_DBG_STR (\nLRDimmCap             , CFG_MEMORY_LRDIMM_CAPABLE)
2742           MAKE_DBG_STR (\nUDimmCap              , CFG_MEMORY_UDIMM_CAPABLE)
2743           MAKE_DBG_STR (\nSODimmCap             , CFG_MEMORY_SODIMM_CAPABLE)
2744           MAKE_DBG_STR (\nDqsTrainingControl    , CFG_DQS_TRAINING_CONTROL)
2745           MAKE_DBG_STR (\nIgnoreSpdChecksum     , CFG_IGNORE_SPD_CHECKSUM)
2746           MAKE_DBG_STR (\nUseBurstMode          , CFG_USE_BURST_MODE)
2747           MAKE_DBG_STR (\nAllMemClkOn           , CFG_MEMORY_ALL_CLOCKS_ON),
2748
2749           MAKE_DBG_STR (\nPowerDownEn           , CFG_MEMORY_POWER_DOWN)
2750           MAKE_DBG_STR (\nPowerDownMode         , CFG_POWER_DOWN_MODE)
2751           MAKE_DBG_STR (\nOnlineSpare           , CFG_ONLINE_SPARE)
2752           MAKE_DBG_STR (\nAddrParityEn          , CFG_MEMORY_PARITY_ENABLE)
2753           MAKE_DBG_STR (\nBankSwizzle           , CFG_BANK_SWIZZLE)
2754           MAKE_DBG_STR (\nLimitBelow1TB         , CFG_LIMIT_MEMORY_TO_BELOW_1TB)
2755           MAKE_DBG_STR (\nCsIntlvEn             , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2756           MAKE_DBG_STR (\nNodeIntlvEn           , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2757           MAKE_DBG_STR (\nDctIntlvEn            , CFG_MEMORY_CHANNEL_INTERLEAVING),
2758
2759           MAKE_DBG_STR (\nUmaMode                , CFG_UMA_MODE)
2760           MAKE_DBG_STR (\nUmaSize                , CFG_UMA_SIZE)
2761           MAKE_DBG_STR (\nUmaAbove4G             , CFG_UMA_ABOVE4G)
2762           MAKE_DBG_STR (\nUmaAlignment           , CFG_UMA_ALIGNMENT)
2763
2764           MAKE_DBG_STR (\nEccEn                 , CFG_ENABLE_ECC_FEATURE)
2765           MAKE_DBG_STR (\nEccRedirect           , CFG_ECC_REDIRECTION)
2766           MAKE_DBG_STR (\nScrubDramRate         , CFG_SCRUB_DRAM_RATE)
2767           MAKE_DBG_STR (\nScrubL2Rate           , CFG_SCRUB_L2_RATE)
2768           MAKE_DBG_STR (\nScrubL3Rate           , CFG_SCRUB_L3_RATE)
2769           MAKE_DBG_STR (\nScrubIcRate           , CFG_SCRUB_IC_RATE)
2770           MAKE_DBG_STR (\nScrubDcRate           , CFG_SCRUB_DC_RATE)
2771           MAKE_DBG_STR (\nEccSyncFlood          , CFG_ECC_SYNC_FLOOD)
2772           MAKE_DBG_STR (\nEccSymbolSize         , CFG_ECC_SYMBOL_SIZE)
2773           MAKE_DBG_STR (\nHeapDramAddress       , CFG_HEAP_DRAM_ADDRESS)
2774           MAKE_DBG_STR (\nNodeMem1GBAlign       , CFG_1GB_ALIGN),
2775
2776           MAKE_DBG_STR (\nS3LateRestore         , CFG_S3_LATE_RESTORE)
2777           MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2778
2779           MAKE_DBG_STR (\nApMtrrSettingsList     , CFG_AP_MTRR_SETTINGS_LIST)
2780
2781           MAKE_DBG_STR (\nProcessorScopeInSb     , CFG_PROCESSOR_SCOPE_IN_SB)
2782           MAKE_DBG_STR (\nProcessorScopeName0    , CFG_PROCESSOR_SCOPE_NAME0)
2783           MAKE_DBG_STR (\nProcessorScopeName1    , CFG_PROCESSOR_SCOPE_NAME1)
2784           MAKE_DBG_STR (\nGnbHdAudio             , CFG_GNB_HD_AUDIO)
2785           MAKE_DBG_STR (\nAbmSupport             , CFG_ABM_SUPPORT)
2786           MAKE_DBG_STR (\nDynamicRefreshRate     , CFG_DYNAMIC_REFRESH_RATE)
2787           MAKE_DBG_STR (\nLcdBackLightControl    , CFG_LCD_BACK_LIGHT_CONTROL)
2788           MAKE_DBG_STR (\nGnb3dStereoPinIndex    , CFG_GNB_STEREO_3D_PINOUT)
2789           MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2790           MAKE_DBG_STR (\nCfgGnbIGPUSSID         , CFG_GNB_IGPU_SSID)
2791           MAKE_DBG_STR (\nCfgGnbHDAudioSSID      , CFG_GNB_HDAUDIO_SSID)
2792           MAKE_DBG_STR (\nCfgGnbPcieSSID         , CFG_GNB_PCIE_SSID)
2793           MAKE_DBG_STR (\nCfgIommuSupport        , CFG_IOMMU_SUPPORT)
2794           MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum  , CFG_GFX_LVDS_SPREAD_SPECTRUM)
2795           MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE)
2796           MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe    , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE)
2797           MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl   , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL)
2798           MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon    , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON)
2799           MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe   , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE)
2800           MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY)
2801           MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON)
2802           MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL)
2803           MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq      , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ)
2804           MAKE_DBG_STR (\nCfgLcdBitDepthControlValue    , CFG_LCD_BIT_DEPTH_CONTROL_VALUE)
2805           MAKE_DBG_STR (\nCfgLvds24bbpPanelMode         , CFG_LVDS_24BBP_PANEL_MODE),
2806           MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum   , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
2807         #endif
2808         NULL
2809       };
2810     #endif
2811   #endif
2812 #endif