src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * Install of build option: Memory
   6  *
   7  * Contains AMD AGESA install macros and test conditions. Output is the
   8  * defaults tables reflecting the User's build options selection.
   9  *
  10  * @xrefitem bom "File Content Label" "Release Content"
  11  * @e project:      AGESA
  12  * @e sub-project:  Options
  13  * @e \$Revision: 49545 $   @e \$Date: 2011-03-25 05:58:58 +0800 (Fri, 25 Mar 2011) $
  14  */
  15 /*****************************************************************************
  16  *
  17  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  18  * All rights reserved.
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions are met:
  22  *     * Redistributions of source code must retain the above copyright
  23  *       notice, this list of conditions and the following disclaimer.
  24  *     * Redistributions in binary form must reproduce the above copyright
  25  *       notice, this list of conditions and the following disclaimer in the
  26  *       documentation and/or other materials provided with the distribution.
  27  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  28  *       its contributors may be used to endorse or promote products derived
  29  *       from this software without specific prior written permission.
  30  *
  31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  32  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  33  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  34  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  35  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  37  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  38  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  40  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  ***************************************************************************/
  43
  44 #ifndef _OPTION_MEMORY_INSTALL_H_
  45 #define _OPTION_MEMORY_INSTALL_H_
  46
  47 #ifndef RUN_BROKEN_AGESA_TESTS
  48         #define RUN_BROKEN_AGESA_TESTS 0
  49 #endif
  50
  51 /*-------------------------------------------------------------------------------
  52  *  This option file is designed to be included into the platform solution install
  53  *  file. The platform solution install file will define the options status.
  54  *  Check to validate the definition
  55  */
  56
  57 /*----------------------------------------------------------------------------------
  58  * FEATURE BLOCK FUNCTIONS
  59  *
  60  *  This section defines function names that depend upon options that are selected
  61  *  in the platform solution install file.
  62  */
  63 BOOLEAN MemFDefRet (
  64   IN OUT   MEM_NB_BLOCK *NBPtr
  65   )
  66 {
  67   return FALSE;
  68 }
  69
  70 BOOLEAN MemMDefRet (
  71   IN   MEM_MAIN_DATA_BLOCK *MMPtr
  72   )
  73 {
  74   return TRUE;
  75 }
  76
  77 BOOLEAN MemMDefRetFalse (
  78   IN   MEM_MAIN_DATA_BLOCK *MMPtr
  79   )
  80 {
  81   return FALSE;
  82 }
  83
  84 /* -----------------------------------------------------------------------------*/
  85 /**
  86  *
  87  *
  88  *   This function initializes the northbridge block for dimm identification translator
  89  *
  90  *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
  91  *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
  92  *     @param[in,out]   NodeID   - ID of current node to construct
  93  *     @return          TRUE     - This is the correct constructor for the targeted node.
  94  *     @return          FALSE    - This isn't the correct constructor for the targeted node.
  95  */
  96 BOOLEAN MemNIdentifyDimmConstructorRetDef (
  97   IN OUT   MEM_NB_BLOCK *NBPtr,
  98   IN OUT   MEM_DATA_STRUCT *MemPtr,
  99   IN       UINT8 NodeID
 100   )
 101 {
 102   return FALSE;
 103 }
 104 /*----------------------------------------------------------------------------------
 105  * TABLE FEATURE BLOCK FUNCTIONS
 106  *
 107  *  This section defines function names that depend upon options that are selected
 108  *  in the platform solution install file.
 109  */
 110 UINT8 MemFTableDefRet (
 111   IN OUT   MEM_TABLE_ALIAS **MTPtr
 112   )
 113 {
 114   return 0;
 115 }
 116 /*----------------------------------------------------------------------------------
 117  * FEATURE S3 BLOCK FUNCTIONS
 118  *
 119  *  This section defines function names that depend upon options that are selected
 120  *  in the platform solution install file.
 121  */
 122 BOOLEAN MemFS3DefConstructorRet (
 123   IN OUT   VOID *S3NBPtr,
 124   IN OUT   MEM_DATA_STRUCT *MemPtr,
 125   IN       UINT8 NodeID
 126   )
 127 {
 128   return TRUE;
 129 }
 130
 131 #if (OPTION_MEMCTLR_DR == TRUE)
 132   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 133     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 134       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr;
 135       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr
 136     #else
 137       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
 138     #endif
 139   #else
 140     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
 141   #endif
 142   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 143     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr;
 144     #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr
 145   #else
 146     #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef
 147   #endif
 148 #endif
 149
 150 #if (OPTION_MEMCTLR_DA == TRUE  || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
 151   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 152     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 153       #if (OPTION_MEMCTLR_Ni == TRUE)
 154         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi;
 155         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi
 156       #else
 157         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
 158       #endif
 159       #if (OPTION_MEMCTLR_DA == TRUE)
 160         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA;
 161         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA
 162       #else
 163         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
 164       #endif
 165       #if (OPTION_MEMCTLR_PH == TRUE)
 166         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh;
 167         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh
 168       #else
 169         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
 170       #endif
 171       #if (OPTION_MEMCTLR_RB == TRUE)
 172         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb;
 173         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb
 174       #else
 175         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
 176       #endif
 177     #endif
 178   #else
 179     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
 180     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
 181     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
 182     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
 183   #endif
 184   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 185     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA;
 186     #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA
 187     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb;
 188     #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb
 189     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh;
 190     #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh
 191   #else
 192     #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef
 193     #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef
 194     #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef
 195   #endif
 196 #endif
 197
 198 #if (OPTION_MEMCTLR_OR == TRUE)
 199   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 200     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 201       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr;
 202       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr
 203     #else
 204       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
 205     #endif
 206   #else
 207     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
 208   #endif
 209   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 210     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr;
 211     #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr
 212   #else
 213     #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef
 214   #endif
 215 #endif
 216
 217 #if (OPTION_MEMCTLR_HY == TRUE)
 218   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 219     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 220       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy;
 221       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy
 222     #else
 223       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
 224     #endif
 225   #else
 226     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
 227   #endif
 228   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 229     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy;
 230     #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy
 231   #else
 232     #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef
 233   #endif
 234 #endif
 235
 236 #if (OPTION_MEMCTLR_C32 == TRUE)
 237   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 238     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 239       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32;
 240       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32
 241     #else
 242       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
 243     #endif
 244   #else
 245     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
 246   #endif
 247   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 248     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32;
 249     #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32
 250   #else
 251     #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef
 252   #endif
 253 #endif
 254
 255 #if (OPTION_MEMCTLR_LN == TRUE)
 256   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 257     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 258       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN;
 259       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN
 260     #else
 261       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
 262     #endif
 263   #else
 264     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
 265   #endif
 266   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 267     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN;
 268     #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN
 269   #else
 270     #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef
 271   #endif
 272 #endif
 273
 274 #if (OPTION_MEMCTLR_ON == TRUE)
 275   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 276     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 277       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON;
 278       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON
 279     #else
 280       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
 281     #endif
 282   #else
 283     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
 284   #endif
 285   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 286     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON;
 287     #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON
 288   #else
 289     #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef
 290   #endif
 291 #endif
 292
 293 /*----------------------------------------------------------------------------------
 294  * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
 295  *
 296  *----------------------------------------------------------------------------------
 297 */
 298 #define MEM_NB_SUPPORT_DR
 299 #define MEM_NB_SUPPORT_RB
 300 #define MEM_NB_SUPPORT_DA
 301 #define MEM_NB_SUPPORT_Ni
 302 #define MEM_NB_SUPPORT_PH
 303 #define MEM_NB_SUPPORT_HY
 304 #define MEM_NB_SUPPORT_LN
 305 #define MEM_NB_SUPPORT_OR
 306 #define MEM_NB_SUPPORT_C32
 307 #define MEM_NB_SUPPORT_ON
 308 #define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
 309
 310 #if (AGESA_ENTRY_INIT_POST == TRUE)
 311   /*----------------------------------------------------------------------------------
 312    * FLOW CONTROL FUNCTION
 313    *
 314    *  This section selects the function that controls the memory initialization sequence
 315    *  based upon the number of processor families that the BIOS will support.
 316    */
 317
 318   extern MEM_FLOW_CFG MemMFlowDef;
 319   #if (OPTION_MEMCTLR_DR == TRUE)
 320     extern MEM_FLOW_CFG MemMFlowDr;
 321     #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
 322   #else
 323     #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
 324   #endif
 325   #if (OPTION_MEMCTLR_DA == TRUE)
 326     extern MEM_FLOW_CFG MemMFlowDA;
 327     #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
 328   #else
 329     #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
 330   #endif
 331   #if (OPTION_MEMCTLR_HY == TRUE)
 332     extern MEM_FLOW_CFG MemMFlowHy;
 333     #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
 334   #else
 335     #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
 336   #endif
 337   #if (OPTION_MEMCTLR_OR == TRUE)
 338     extern MEM_FLOW_CFG MemMFlowOr;
 339     #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
 340   #else
 341     #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
 342   #endif
 343   #if (OPTION_MEMCTLR_LN == TRUE)
 344     extern MEM_FLOW_CFG MemMFlowLN;
 345     #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN,
 346   #else
 347     #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef,
 348   #endif
 349   #if (OPTION_MEMCTLR_C32 == TRUE)
 350     extern MEM_FLOW_CFG MemMFlowC32;
 351     #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
 352   #else
 353     #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
 354   #endif
 355   #if (OPTION_MEMCTLR_ON == TRUE)
 356     extern MEM_FLOW_CFG MemMFlowON;
 357     #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
 358   #else
 359     #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
 360   #endif
 361   #if (OPTION_MEMCTLR_Ni == TRUE)
 362     extern MEM_FLOW_CFG MemMFlowDA;
 363     #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
 364   #else
 365     #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
 366   #endif
 367   #if (OPTION_MEMCTLR_RB == TRUE)
 368     extern MEM_FLOW_CFG MemMFlowRb;
 369     #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
 370   #else
 371     #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
 372   #endif
 373   #if (OPTION_MEMCTLR_PH == TRUE)
 374     extern MEM_FLOW_CFG MemMFlowPh;
 375     #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
 376   #else
 377     #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
 378   #endif
 379
 380   MEM_FLOW_CFG* memFlowControlInstalled[] = {
 381     MEM_MAIN_FLOW_CONTROL_PTR_Dr
 382     MEM_MAIN_FLOW_CONTROL_PTR_DA
 383     MEM_MAIN_FLOW_CONTROL_PTR_RB
 384     MEM_MAIN_FLOW_CONTROL_PTR_PH
 385     MEM_MAIN_FLOW_CONTROL_PTR_Hy
 386     MEM_MAIN_FLOW_CONTROL_PTR_OR
 387     MEM_MAIN_FLOW_CONTROL_PTR_LN
 388     MEM_MAIN_FLOW_CONTROL_PTR_C32
 389     MEM_MAIN_FLOW_CONTROL_PTR_ON
 390     MEM_MAIN_FLOW_CONTROL_PTR_Ni
 391     NULL
 392   };
 393
 394   #if (OPTION_ONLINE_SPARE == TRUE)
 395     extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
 396     #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
 397     extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
 398     #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
 399   #else
 400     #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
 401     #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
 402   #endif
 403
 404   #if (OPTION_MEM_RESTORE == TRUE)
 405     extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
 406     extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
 407     #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
 408     #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
 409   #else
 410     #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
 411     #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
 412   #endif
 413
 414   #if (OPTION_BANK_INTERLEAVE == TRUE)
 415     extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
 416     #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
 417     extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
 418     #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
 419   #else
 420     #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
 421     #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
 422   #endif
 423
 424   #if (OPTION_NODE_INTERLEAVE == TRUE)
 425     extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
 426     #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
 427     extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
 428     extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
 429     #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
 430     #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
 431   #else
 432     #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
 433     #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
 434     #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
 435   #endif
 436
 437   #if (OPTION_DCT_INTERLEAVE == TRUE)
 438     extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
 439     #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
 440   #else
 441     #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
 442   #endif
 443
 444   #if (OPTION_ECC == TRUE)
 445     extern OPTION_MEM_FEATURE_MAIN MemMEcc;
 446     #define MEM_MAIN_FEATURE_ECC  MemMEcc
 447     extern OPTION_MEM_FEATURE_NB MemFCheckECC;
 448     extern OPTION_MEM_FEATURE_NB MemFInitECC;
 449     #define MEM_FEATURE_CK_ECC   MemFCheckECC
 450     #define MEM_FEATURE_ECC   MemFInitECC
 451     #define MEM_FEATURE_ECCX8  MemMDefRet
 452   #else
 453     #define MEM_MAIN_FEATURE_ECC  MemMDefRet
 454     #define MEM_FEATURE_CK_ECC   MemFDefRet
 455     #define MEM_FEATURE_ECC   MemFDefRet
 456     #define MEM_FEATURE_ECCX8  MemMDefRet
 457   #endif
 458
 459   extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
 460   #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
 461
 462   #if (OPTION_DMI == TRUE)
 463     #if (OPTION_DDR3 == TRUE)
 464       extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
 465       #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
 466     #else
 467       extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
 468       #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
 469     #endif
 470   #else
 471     #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
 472   #endif
 473
 474   #if (OPTION_DDR3 == TRUE)
 475     extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
 476     extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
 477     extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
 478     #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
 479     #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
 480     #define MEM_FEATURE_LVDDR3 MemFLvDdr3
 481   #else
 482     #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
 483     #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
 484     #define MEM_FEATURE_LVDDR3 MemFDefRet
 485   #endif
 486
 487   extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
 488   #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
 489
 490   extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
 491   #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
 492
 493   extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 494   #if (OPTION_PARALLEL_TRAINING == TRUE)
 495     extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
 496     #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
 497   #else
 498     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 499   #endif
 500
 501   #if (OPTION_DIMM_EXCLUDE == TRUE)
 502     extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
 503     #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
 504     extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
 505     #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
 506   #else
 507     #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
 508     #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
 509   #endif
 510
 511   /*----------------------------------------------------------------------------------
 512    * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
 513    *
 514    *----------------------------------------------------------------------------------
 515   */
 516   #if OPTION_DDR2 == TRUE
 517     extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
 518     #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
 519     #if (OPTION_HW_DRAM_INIT == TRUE)
 520       extern MEM_TECH_FEAT MemTDramInitHw;
 521       #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
 522     #else
 523       #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTFeatDef
 524     #endif
 525     #if (OPTION_SW_DRAM_INIT == TRUE)
 526       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
 527     #else
 528       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
 529     #endif
 530   #else
 531     #define MEM_TECH_CONSTRUCTOR_DDR2
 532   #endif
 533   #if OPTION_DDR3 == TRUE
 534     extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
 535     #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
 536     #if (OPTION_HW_DRAM_INIT == TRUE)
 537       extern MEM_TECH_FEAT MemTDramInitHw;
 538       #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
 539     #else
 540       #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
 541     #endif
 542     #if (OPTION_SW_DRAM_INIT == TRUE)
 543       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
 544     #else
 545       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
 546     #endif
 547   #else
 548     #define MEM_TECH_CONSTRUCTOR_DDR3
 549   #endif
 550
 551   /*---------------------------------------------------------------------------------------------------
 552    * FEATURE BLOCKS
 553    *
 554    *  This section instantiates a feature block structure for each memory controller installed
 555    *  by the platform solution install file.
 556    *---------------------------------------------------------------------------------------------------
 557    */
 558
 559   /*---------------------------------------------------------------------------------------------------
 560    * DEERHOUND FEATURE BLOCK
 561    *---------------------------------------------------------------------------------------------------
 562    */
 563   #if (OPTION_MEMCTLR_DR == TRUE)
 564     #if OPTION_DDR2
 565       #undef MEM_TECH_FEATURE_DRAMINIT
 566       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 567     #endif
 568     #if OPTION_DDR3
 569       #undef MEM_TECH_FEATURE_DRAMINIT
 570       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 571     #endif
 572
 573     #undef MEM_TECH_FEATURE_CPG
 574     #define MEM_TECH_FEATURE_CPG    MemFDefRet
 575
 576     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 577       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 578       #undef MEM_TECH_FEATURE_HWRXEN
 579       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 580     #else
 581       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 582       #undef MEM_TECH_FEATURE_HWRXEN
 583       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 584     #endif
 585
 586     #undef MEM_MAIN_FEATURE_TRAINING
 587     #undef MEM_FEATURE_TRAINING
 588 //    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 589     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 590     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 591     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 592
 593     MEM_FEAT_BLOCK_NB  MemFeatBlockDr = {
 594       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 595       MEM_FEATURE_ONLINE_SPARE,
 596       MEM_FEATURE_BANK_INTERLEAVE,
 597       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 598       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
 599       MEM_FEATURE_NODE_INTERLEAVE,
 600       MEM_FEATURE_CHANNEL_INTERLEAVE,
 601       MemFDefRet,
 602       MEM_FEATURE_CK_ECC,
 603       MEM_FEATURE_ECC,
 604       MEM_FEATURE_TRAINING,
 605       MEM_FEATURE_LVDDR3,
 606       MemFDefRet,
 607       MEM_TECH_FEATURE_DRAMINIT,
 608       MEM_FEATURE_DIMM_EXCLUDE,
 609       MemFDefRet,
 610       MEM_TECH_FEATURE_CPG,
 611       MEM_TECH_FEATURE_HWRXEN
 612     };
 613
 614     #undef MEM_NB_SUPPORT_DR
 615     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR;
 616     extern MEM_INITIALIZER MemNInitDefaultsDR;
 617
 618
 619     #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
 620   #endif // OPTION_MEMCTRL_DR
 621
 622   /*---------------------------------------------------------------------------------------------------
 623    * DASHOUND FEATURE BLOCK
 624    *---------------------------------------------------------------------------------------------------
 625    */
 626   #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
 627     #if OPTION_DDR2
 628       #undef MEM_TECH_FEATURE_DRAMINIT
 629       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 630     #endif
 631     #if OPTION_DDR3
 632       #undef MEM_TECH_FEATURE_DRAMINIT
 633       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 634     #endif
 635
 636     #undef MEM_TECH_FEATURE_CPG
 637     #define MEM_TECH_FEATURE_CPG    MemFDefRet
 638
 639     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 640       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 641       #undef MEM_TECH_FEATURE_HWRXEN
 642       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 643     #else
 644       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 645       #undef MEM_TECH_FEATURE_HWRXEN
 646       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 647     #endif
 648
 649     #undef MEM_MAIN_FEATURE_TRAINING
 650     #undef MEM_FEATURE_TRAINING
 651 //    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 652     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 653     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 654     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 655
 656     #if (OPTION_MEMCTLR_Ni == TRUE)
 657       MEM_FEAT_BLOCK_NB  MemFeatBlockNi = {
 658         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 659         MemFDefRet,
 660         MEM_FEATURE_BANK_INTERLEAVE,
 661         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 662         MemFDefRet,
 663         MemFDefRet,
 664         MEM_FEATURE_CHANNEL_INTERLEAVE,
 665         MEM_FEATURE_REGION_INTERLEAVE,
 666         MEM_FEATURE_CK_ECC,
 667         MEM_FEATURE_ECC,
 668         MEM_FEATURE_TRAINING,
 669         MEM_FEATURE_LVDDR3,
 670         MemFDefRet,
 671         MEM_TECH_FEATURE_DRAMINIT,
 672         MEM_FEATURE_DIMM_EXCLUDE,
 673         MemFDefRet,
 674         MEM_TECH_FEATURE_CPG,
 675         MEM_TECH_FEATURE_HWRXEN
 676       };
 677
 678       #undef MEM_NB_SUPPORT_Ni
 679       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi;
 680       extern MEM_INITIALIZER MemNInitDefaultsNi;
 681
 682       #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA },
 683     #endif
 684
 685     #if (OPTION_MEMCTLR_PH == TRUE)
 686       MEM_FEAT_BLOCK_NB  MemFeatBlockPh = {
 687         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 688         MemFDefRet,
 689         MEM_FEATURE_BANK_INTERLEAVE,
 690         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 691         MemFDefRet,
 692         MemFDefRet,
 693         MEM_FEATURE_CHANNEL_INTERLEAVE,
 694         MEM_FEATURE_REGION_INTERLEAVE,
 695         MEM_FEATURE_CK_ECC,
 696         MEM_FEATURE_ECC,
 697         MEM_FEATURE_TRAINING,
 698         MEM_FEATURE_LVDDR3,
 699         MemFDefRet,
 700         MEM_TECH_FEATURE_DRAMINIT,
 701         MEM_FEATURE_DIMM_EXCLUDE,
 702         MemFDefRet,
 703         MEM_TECH_FEATURE_CPG,
 704         MEM_TECH_FEATURE_HWRXEN
 705       };
 706
 707       #undef MEM_NB_SUPPORT_PH
 708       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh;
 709       extern MEM_INITIALIZER MemNInitDefaultsPh;
 710
 711       #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
 712     #endif
 713
 714     #if (OPTION_MEMCTLR_RB == TRUE)
 715       MEM_FEAT_BLOCK_NB  MemFeatBlockRb = {
 716         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 717         MemFDefRet,
 718         MEM_FEATURE_BANK_INTERLEAVE,
 719         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 720         MemFDefRet,
 721         MemFDefRet,
 722         MEM_FEATURE_CHANNEL_INTERLEAVE,
 723         MEM_FEATURE_REGION_INTERLEAVE,
 724         MEM_FEATURE_CK_ECC,
 725         MEM_FEATURE_ECC,
 726         MEM_FEATURE_TRAINING,
 727         MEM_FEATURE_LVDDR3,
 728         MemFDefRet,
 729         MEM_TECH_FEATURE_DRAMINIT,
 730         MEM_FEATURE_DIMM_EXCLUDE,
 731         MemFDefRet,
 732         MEM_TECH_FEATURE_CPG,
 733         MEM_TECH_FEATURE_HWRXEN
 734       };
 735
 736       #undef MEM_NB_SUPPORT_RB
 737       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb;
 738       extern MEM_INITIALIZER MemNInitDefaultsRb;
 739
 740       #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
 741     #endif
 742
 743     #if (OPTION_MEMCTLR_DA == TRUE)
 744       MEM_FEAT_BLOCK_NB  MemFeatBlockDA = {
 745         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 746         MemFDefRet,
 747         MEM_FEATURE_BANK_INTERLEAVE,
 748         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 749         MemFDefRet,
 750         MemFDefRet,
 751         MEM_FEATURE_CHANNEL_INTERLEAVE,
 752         MEM_FEATURE_REGION_INTERLEAVE,
 753         MEM_FEATURE_CK_ECC,
 754         MEM_FEATURE_ECC,
 755         MEM_FEATURE_TRAINING,
 756         MEM_FEATURE_LVDDR3,
 757         MemFDefRet,
 758         MEM_TECH_FEATURE_DRAMINIT,
 759         MEM_FEATURE_DIMM_EXCLUDE,
 760         MemFDefRet,
 761         MEM_TECH_FEATURE_CPG,
 762         MEM_TECH_FEATURE_HWRXEN
 763       };
 764
 765       #undef MEM_NB_SUPPORT_DA
 766       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA;
 767       extern MEM_INITIALIZER MemNInitDefaultsDA;
 768
 769       #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
 770     #endif
 771   #endif // OPTION_MEMCTRL_DA
 772
 773   /*---------------------------------------------------------------------------------------------------
 774    * HYDRA FEATURE BLOCK
 775    *---------------------------------------------------------------------------------------------------
 776    */
 777   #if (OPTION_MEMCTLR_HY == TRUE)
 778     #if OPTION_DDR2
 779       #undef MEM_TECH_FEATURE_DRAMINIT
 780       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 781     #endif
 782     #if OPTION_DDR3
 783       #undef MEM_TECH_FEATURE_DRAMINIT
 784       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 785     #endif
 786
 787     #undef MEM_TECH_FEATURE_CPG
 788     #define MEM_TECH_FEATURE_CPG    MemFDefRet
 789
 790     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 791       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 792       #undef MEM_TECH_FEATURE_HWRXEN
 793       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 794     #else
 795       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 796       #undef MEM_TECH_FEATURE_HWRXEN
 797       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 798     #endif
 799
 800
 801     #undef MEM_MAIN_FEATURE_TRAINING
 802     #undef MEM_FEATURE_TRAINING
 803 //    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 804     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 805     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 806     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 807
 808     MEM_FEAT_BLOCK_NB  MemFeatBlockHy = {
 809       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 810       MEM_FEATURE_ONLINE_SPARE,
 811       MEM_FEATURE_BANK_INTERLEAVE,
 812       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 813       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
 814       MEM_FEATURE_NODE_INTERLEAVE,
 815       MEM_FEATURE_CHANNEL_INTERLEAVE,
 816       MemFDefRet,
 817       MEM_FEATURE_CK_ECC,
 818       MEM_FEATURE_ECC,
 819       MEM_FEATURE_TRAINING,
 820       MEM_FEATURE_LVDDR3,
 821       MEM_FEATURE_ONDIMMTHERMAL,
 822       MEM_TECH_FEATURE_DRAMINIT,
 823       MEM_FEATURE_DIMM_EXCLUDE,
 824       MemFDefRet,
 825       MEM_TECH_FEATURE_CPG,
 826       MEM_TECH_FEATURE_HWRXEN
 827     };
 828
 829     #undef MEM_NB_SUPPORT_HY
 830     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY;
 831     extern MEM_INITIALIZER MemNInitDefaultsHY;
 832     #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
 833   #endif // OPTION_MEMCTRL_HY
 834   /*---------------------------------------------------------------------------------------------------
 835    * LLANO FEATURE BLOCK
 836    *---------------------------------------------------------------------------------------------------
 837    */
 838   #if (OPTION_MEMCTLR_LN == TRUE)
 839     #if OPTION_DDR2
 840       #undef MEM_TECH_FEATURE_DRAMINIT
 841       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 842     #endif
 843     #if OPTION_DDR3
 844       #undef MEM_TECH_FEATURE_DRAMINIT
 845       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 846     #endif
 847
 848     #if (OPTION_EARLY_SAMPLES == TRUE)
 849       extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN;
 850       #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportLN
 851     #else
 852       #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
 853     #endif
 854
 855     #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
 856       extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
 857       #undef MEM_TECH_FEATURE_CPG
 858       #define MEM_TECH_FEATURE_CPG    MemNInitCPGClientNb
 859     #else
 860       #undef MEM_TECH_FEATURE_CPG
 861       #define MEM_TECH_FEATURE_CPG    MemFDefRet
 862     #endif
 863
 864     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 865       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 866       #undef MEM_TECH_FEATURE_HWRXEN
 867       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 868     #else
 869       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 870       #undef MEM_TECH_FEATURE_HWRXEN
 871       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 872     #endif
 873
 874     #undef MEM_MAIN_FEATURE_TRAINING
 875     #undef MEM_FEATURE_TRAINING
 876 //    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 877     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 878     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 879     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 880
 881     MEM_FEAT_BLOCK_NB  MemFeatBlockLn = {
 882       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 883       MemFDefRet,
 884       MEM_FEATURE_BANK_INTERLEAVE,
 885       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 886       MemFDefRet,
 887       MemFDefRet,
 888       MEM_FEATURE_CHANNEL_INTERLEAVE,
 889       MEM_FEATURE_REGION_INTERLEAVE,
 890       MEM_FEATURE_CK_ECC,
 891       MemFDefRet,
 892       MEM_FEATURE_TRAINING,
 893       MEM_FEATURE_LVDDR3,
 894       MEM_FEATURE_ONDIMMTHERMAL,
 895       MEM_TECH_FEATURE_DRAMINIT,
 896       MEM_FEATURE_DIMM_EXCLUDE,
 897       MEM_EARLY_SAMPLE_SUPPORT,
 898       MEM_TECH_FEATURE_CPG,
 899       MEM_TECH_FEATURE_HWRXEN
 900     };
 901     #undef MEM_NB_SUPPORT_LN
 902     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN;
 903     extern MEM_INITIALIZER MemNInitDefaultsLN;
 904     #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
 905
 906   #endif // OPTION_MEMCTRL_LN
 907
 908   /*---------------------------------------------------------------------------------------------------
 909    * ONTARIO FEATURE BLOCK
 910    *---------------------------------------------------------------------------------------------------
 911    */
 912   #if (OPTION_MEMCTLR_ON == TRUE)
 913     #if OPTION_DDR2
 914       #undef MEM_TECH_FEATURE_DRAMINIT
 915       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 916     #endif
 917     #if OPTION_DDR3
 918       #undef MEM_TECH_FEATURE_DRAMINIT
 919       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 920     #endif
 921
 922     #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
 923       extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
 924       #undef MEM_TECH_FEATURE_CPG
 925       #define MEM_TECH_FEATURE_CPG    MemNInitCPGClientNb
 926     #else
 927       #undef MEM_TECH_FEATURE_CPG
 928       #define MEM_TECH_FEATURE_CPG    MemFDefRet
 929     #endif
 930
 931     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 932       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 933       #undef MEM_TECH_FEATURE_HWRXEN
 934       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 935     #else
 936       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 937       #undef MEM_TECH_FEATURE_HWRXEN
 938       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 939     #endif
 940
 941     #undef MEM_MAIN_FEATURE_TRAINING
 942     #undef MEM_FEATURE_TRAINING
 943     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 944     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 945     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 946
 947     #if (OPTION_EARLY_SAMPLES == TRUE)
 948       extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON;
 949       #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportON
 950     #else
 951       #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
 952     #endif
 953
 954     MEM_FEAT_BLOCK_NB  MemFeatBlockOn = {
 955       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 956       MemFDefRet,
 957       MEM_FEATURE_BANK_INTERLEAVE,
 958       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 959       MemFDefRet,
 960       MemFDefRet,
 961       MemFDefRet,
 962       MemFDefRet,
 963       MemFDefRet,
 964       MemFDefRet,
 965       MEM_FEATURE_TRAINING,
 966       MEM_FEATURE_LVDDR3,
 967       MEM_FEATURE_ONDIMMTHERMAL,
 968       MEM_TECH_FEATURE_DRAMINIT,
 969       MEM_FEATURE_DIMM_EXCLUDE,
 970       MEM_EARLY_SAMPLE_SUPPORT,
 971       MEM_TECH_FEATURE_CPG,
 972       MEM_TECH_FEATURE_HWRXEN
 973     };
 974
 975     #undef MEM_NB_SUPPORT_ON
 976     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON;
 977     extern MEM_INITIALIZER MemNInitDefaultsON;
 978     #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
 979
 980   #endif // OPTION_MEMCTRL_ON
 981
 982   /*---------------------------------------------------------------------------------------------------
 983    * OROCHI FEATURE BLOCK
 984    *---------------------------------------------------------------------------------------------------
 985    */
 986   #if (OPTION_MEMCTLR_OR == TRUE)
 987     #if OPTION_DDR2
 988       #undef MEM_TECH_FEATURE_DRAMINIT
 989       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 990     #endif
 991     #if OPTION_DDR3
 992       #undef MEM_MAIN_FEATURE_LVDDR3
 993       extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
 994       #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
 995       #undef MEM_TECH_FEATURE_DRAMINIT
 996       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 997     #endif
 998
 999     #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT)
1000       #undef MEM_FEATURE_REGION_INTERLEAVE
1001       #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet
1002     #endif
1003
1004     #if (OPTION_EARLY_SAMPLES == TRUE)
1005       extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr;
1006       #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportOr
1007     #else
1008       #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
1009     #endif
1010
1011     #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
1012       extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
1013       #undef MEM_TECH_FEATURE_CPG
1014       #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
1015     #else
1016       #undef MEM_TECH_FEATURE_CPG
1017       #define MEM_TECH_FEATURE_CPG    MemFDefRet
1018     #endif
1019
1020     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1021       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
1022       #undef MEM_TECH_FEATURE_HWRXEN
1023       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
1024     #else
1025       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
1026       #undef MEM_TECH_FEATURE_HWRXEN
1027       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
1028     #endif
1029
1030
1031     #undef MEM_MAIN_FEATURE_TRAINING
1032     #undef MEM_FEATURE_TRAINING
1033 //    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
1034     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
1035     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
1036     #define MEM_FEATURE_TRAINING  MemFStandardTraining
1037
1038     MEM_FEAT_BLOCK_NB  MemFeatBlockOr = {
1039       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
1040       MEM_FEATURE_ONLINE_SPARE,
1041       MEM_FEATURE_BANK_INTERLEAVE,
1042       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
1043       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
1044       MEM_FEATURE_NODE_INTERLEAVE,
1045       MEM_FEATURE_CHANNEL_INTERLEAVE,
1046       MEM_FEATURE_REGION_INTERLEAVE,
1047       MEM_FEATURE_CK_ECC,
1048       MEM_FEATURE_ECC,
1049       MEM_FEATURE_TRAINING,
1050       MEM_FEATURE_LVDDR3,
1051       MEM_FEATURE_ONDIMMTHERMAL,
1052       MEM_TECH_FEATURE_DRAMINIT,
1053       MEM_FEATURE_DIMM_EXCLUDE,
1054       MEM_EARLY_SAMPLE_SUPPORT,
1055       MEM_TECH_FEATURE_CPG,
1056       MEM_TECH_FEATURE_HWRXEN
1057     };
1058
1059     #undef MEM_NB_SUPPORT_OR
1060     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR;
1061     extern MEM_INITIALIZER MemNInitDefaultsOR;
1062     #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
1063   #endif // OPTION_MEMCTRL_OR
1064
1065   /*---------------------------------------------------------------------------------------------------
1066    * C32 FEATURE BLOCK
1067    *---------------------------------------------------------------------------------------------------
1068    */
1069   #if (OPTION_MEMCTLR_C32 == TRUE)
1070     #if OPTION_DDR2
1071       #undef MEM_TECH_FEATURE_DRAMINIT
1072       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
1073     #endif
1074     #if OPTION_DDR3
1075       #undef MEM_TECH_FEATURE_DRAMINIT
1076       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
1077     #endif
1078
1079     #undef MEM_TECH_FEATURE_CPG
1080     #define MEM_TECH_FEATURE_CPG    MemFDefRet
1081
1082     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1083       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
1084       #undef MEM_TECH_FEATURE_HWRXEN
1085       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
1086     #else
1087       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
1088       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
1089     #endif
1090
1091     #undef MEM_MAIN_FEATURE_TRAINING
1092     #undef MEM_FEATURE_TRAINING
1093 //    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
1094     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
1095     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
1096     #define MEM_FEATURE_TRAINING  MemFStandardTraining
1097
1098     MEM_FEAT_BLOCK_NB  MemFeatBlockC32 = {
1099       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
1100       MEM_FEATURE_ONLINE_SPARE,
1101       MEM_FEATURE_BANK_INTERLEAVE,
1102       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
1103       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
1104       MEM_FEATURE_NODE_INTERLEAVE,
1105       MEM_FEATURE_CHANNEL_INTERLEAVE,
1106       MemFDefRet,
1107       MEM_FEATURE_CK_ECC,
1108       MEM_FEATURE_ECC,
1109       MEM_FEATURE_TRAINING,
1110       MEM_FEATURE_LVDDR3,
1111       MEM_FEATURE_ONDIMMTHERMAL,
1112       MEM_TECH_FEATURE_DRAMINIT,
1113       MEM_FEATURE_DIMM_EXCLUDE,
1114       MemFDefRet,
1115       MEM_TECH_FEATURE_CPG,
1116       MEM_TECH_FEATURE_HWRXEN
1117     };
1118
1119     #undef MEM_NB_SUPPORT_C32
1120     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32;
1121     extern MEM_INITIALIZER MemNInitDefaultsC32;
1122     #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
1123   #endif // OPTION_MEMCTRL_C32
1124
1125   /*---------------------------------------------------------------------------------------------------
1126    * MAIN FEATURE BLOCK
1127    *---------------------------------------------------------------------------------------------------
1128    */
1129   MEM_FEAT_BLOCK_MAIN MemFeatMain = {
1130     MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
1131     MEM_MAIN_FEATURE_TRAINING,
1132     MEM_MAIN_FEATURE_DIMM_EXCLUDE,
1133     MEM_MAIN_FEATURE_ONLINE_SPARE,
1134     MEM_MAIN_FEATURE_NODE_INTERLEAVE,
1135     MEM_MAIN_FEATURE_ECC,
1136     MEM_MAIN_FEATURE_MEM_CLEAR,
1137     MEM_MAIN_FEATURE_MEM_DMI,
1138     MEM_MAIN_FEATURE_LVDDR3,
1139     MEM_MAIN_FEATURE_UMAALLOC,
1140     MEM_MAIN_FEATURE_MEM_SAVE,
1141     MEM_MAIN_FEATURE_MEM_RESTORE
1142   };
1143
1144
1145   /*---------------------------------------------------------------------------------------------------
1146    * Technology Training SPECIFIC CONFIGURATION
1147    *
1148    *
1149    *---------------------------------------------------------------------------------------------------
1150    */
1151   #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
1152   #if OPTION_MEMCTLR_DR
1153     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
1154     #if OPTION_DDR2
1155       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1156       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1157       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1158       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1159       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1160       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1161         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1162         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1163         #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTTrainDQSEdgeDetect
1164       #else
1165         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1166         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1167         #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1168           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1169         #else
1170           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTFeatDef
1171         #endif
1172       #endif
1173       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1174         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1175       #else
1176         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1177       #endif
1178       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1179         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1180       #else
1181         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1182       #endif
1183       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1184         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1185       #else
1186         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1187       #endif
1188       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1189         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1190       #else
1191         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1192       #endif
1193       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1194         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1195       #else
1196         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1197       #endif
1198       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Dr = {
1199         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1200         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1201         TECH_TRAIN_SW_WL_DDR2,
1202         TECH_TRAIN_HW_WL_P1_DDR2,
1203         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1204         TECH_TRAIN_HW_WL_P2_DDR2,
1205         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1206         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1207         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1208         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1209         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1210         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1211         TECH_TRAIN_MAX_RD_LAT_DDR2,
1212         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2
1213       };
1214       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1215       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1216       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1217       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr },
1218     #else
1219       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1220       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1221       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1222       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1223       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1224       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1225       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1226       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1227       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1228       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1229       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1230       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1231       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1232       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1233     #endif
1234     #if OPTION_DDR3
1235       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1236       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1237       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1238       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1239       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1240         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1241         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1242       #else
1243         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1244         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1245       #endif
1246       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1247         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1248       #else
1249         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1250       #endif
1251       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1252         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
1253         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
1254         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
1255           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1256           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
1257         #else
1258           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1259             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1260           #else
1261             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1262           #endif
1263         #endif
1264       #else
1265         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1266         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1267         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1268           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1269         #else
1270           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1271         #endif
1272       #endif
1273       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1274         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1275       #else
1276         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1277       #endif
1278       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1279         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1280       #else
1281         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1282       #endif
1283       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1284         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1285       #else
1286         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1287       #endif
1288       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1289         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1290       #else
1291         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1292       #endif
1293       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1294         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1295       #else
1296         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1297       #endif
1298 //      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
1299       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1300 //      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
1301       extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
1302       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Dr = {
1303         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1304         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1305         TECH_TRAIN_SW_WL_DDR3,
1306         TECH_TRAIN_HW_WL_P1_DDR3,
1307         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1308         TECH_TRAIN_HW_WL_P2_DDR3,
1309         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1310         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1311         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1312         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1313         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1314         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1315         TECH_TRAIN_MAX_RD_LAT_DDR3,
1316         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1317       };
1318       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr },
1319     #else
1320       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1321       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1322       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1323       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1324       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1325       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1326       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1327       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1328       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1329       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1330       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1331       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1332       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1333       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1334       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1335       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1336     #endif
1337   #else
1338     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1339     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1340   #endif
1341
1342   #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB)
1343     #if OPTION_DDR2
1344       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1345       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1346       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1347       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1348       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1349       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1350         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1351         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1352         #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1353       #else
1354         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1355         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1356         #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1357           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1358         #else
1359           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTFeatDef
1360         #endif
1361       #endif
1362       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1363         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1364       #else
1365         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1366       #endif
1367       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1368         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1369       #else
1370         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1371       #endif
1372       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1373         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1374       #else
1375         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1376       #endif
1377       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1378         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1379       #else
1380         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1381       #endif
1382       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1383         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1384       #else
1385         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1386       #endif
1387       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2DA = {
1388         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1389         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1390         TECH_TRAIN_SW_WL_DDR2,
1391         TECH_TRAIN_HW_WL_P1_DDR2,
1392         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1393         TECH_TRAIN_HW_WL_P2_DDR2,
1394         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1395         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1396         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1397         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1398         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1399         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1400         TECH_TRAIN_MAX_RD_LAT_DDR2,
1401         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2
1402       };
1403       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2PH = {
1404         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1405         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1406         TECH_TRAIN_SW_WL_DDR2,
1407         TECH_TRAIN_HW_WL_P1_DDR2,
1408         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1409         TECH_TRAIN_HW_WL_P2_DDR2,
1410         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1411         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1412         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1413         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1414         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1415         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1416         TECH_TRAIN_MAX_RD_LAT_DDR2,
1417         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2
1418       };
1419       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Rb = {
1420         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1421         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1422         TECH_TRAIN_SW_WL_DDR2,
1423         TECH_TRAIN_HW_WL_P1_DDR2,
1424         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1425         TECH_TRAIN_HW_WL_P2_DDR2,
1426         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1427         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1428         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1429         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1430         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1431         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1432         TECH_TRAIN_MAX_RD_LAT_DDR2,
1433         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2
1434       };
1435       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Ni = {
1436         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1437         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1438         TECH_TRAIN_SW_WL_DDR2,
1439         TECH_TRAIN_HW_WL_P1_DDR2,
1440         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1441         TECH_TRAIN_HW_WL_P2_DDR2,
1442         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1443         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1444         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1445         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1446         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1447         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1448         TECH_TRAIN_MAX_RD_LAT_DDR2,
1449         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2
1450       };
1451       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1452       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1453       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1454       #if (OPTION_MEMCTLR_DA)
1455         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA
1456         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA },
1457       #else
1458         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1459       #endif
1460       #if (OPTION_MEMCTLR_PH)
1461         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh
1462         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH },
1463       #else
1464         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1465       #endif
1466       #if (OPTION_MEMCTLR_RB)
1467         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb
1468         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb },
1469       #else
1470         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1471       #endif
1472
1473       #if (OPTION_MEMCTLR_Ni)
1474         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi
1475         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni },
1476       #else
1477         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1478       #endif
1479     #else
1480       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1481       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1482       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1483       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1484       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1485       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1486       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1487       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1488       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1489       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1490       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1491       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1492       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1493       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1494       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1495       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1496       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1497     #endif
1498     #if OPTION_DDR3
1499       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1500       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1501       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1502       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1503       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1504         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1505         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1506       #else
1507         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1508         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1509       #endif
1510       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1511         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1512       #else
1513         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1514       #endif
1515       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1516         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1517           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1518         #endif
1519         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
1520         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1521           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1522         #endif
1523         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
1524         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
1525           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1526           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1527         #else
1528           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1529             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1530           #else
1531             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1532           #endif
1533         #endif
1534       #else
1535         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1536         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1537         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1538           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1539           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1540         #else
1541           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1542         #endif
1543       #endif
1544       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1545         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1546       #else
1547         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1548       #endif
1549       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1550         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1551       #else
1552         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1553       #endif
1554       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1555         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1556       #else
1557         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1558       #endif
1559       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1560         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1561       #else
1562         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1563       #endif
1564       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1565         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1566       #else
1567         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1568       #endif
1569       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3DA = {
1570         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1571         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1572         TECH_TRAIN_SW_WL_DDR3,
1573         TECH_TRAIN_HW_WL_P1_DDR3,
1574         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1575         TECH_TRAIN_HW_WL_P2_DDR3,
1576         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1577         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1578         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1579         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1580         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1581         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1582         TECH_TRAIN_MAX_RD_LAT_DDR3,
1583         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1584       };
1585       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ph = {
1586         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1587         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1588         TECH_TRAIN_SW_WL_DDR3,
1589         TECH_TRAIN_HW_WL_P1_DDR3,
1590         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1591         TECH_TRAIN_HW_WL_P2_DDR3,
1592         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1593         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1594         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1595         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1596         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1597         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1598         TECH_TRAIN_MAX_RD_LAT_DDR3,
1599         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1600       };
1601       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Rb = {
1602         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1603         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1604         TECH_TRAIN_SW_WL_DDR3,
1605         TECH_TRAIN_HW_WL_P1_DDR3,
1606         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1607         TECH_TRAIN_HW_WL_P2_DDR3,
1608         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1609         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1610         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1611         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1612         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1613         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1614         TECH_TRAIN_MAX_RD_LAT_DDR3,
1615         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1616       };
1617       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ni = {
1618         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1619         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1620         TECH_TRAIN_SW_WL_DDR3,
1621         TECH_TRAIN_HW_WL_P1_DDR3,
1622         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1623         TECH_TRAIN_HW_WL_P2_DDR3,
1624         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1625         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1626         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1627         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1628         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1629         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1630         TECH_TRAIN_MAX_RD_LAT_DDR3,
1631         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1632       };
1633 //      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
1634       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1635 //      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
1636       #if (OPTION_MEMCTLR_DA)
1637         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA;
1638         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA },
1639       #else
1640         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1641       #endif
1642       #if (OPTION_MEMCTLR_PH)
1643         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh;
1644         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph },
1645       #else
1646         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1647       #endif
1648       #if (OPTION_MEMCTLR_RB)
1649         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb;
1650         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb },
1651       #else
1652         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1653       #endif
1654       #if (OPTION_MEMCTLR_Ni)
1655         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi;
1656         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni },
1657       #else
1658         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1659       #endif
1660     #else
1661       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1662       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1663       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1664       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1665       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1666       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1667       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1668       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1669       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1670       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1671       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1672       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1673       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1674       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1675       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1676       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1677       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1678       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1679       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1680     #endif
1681   #else
1682     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1683     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1684     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1685     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1686     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1687     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1688     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1689     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1690   #endif
1691
1692   #if OPTION_MEMCTLR_HY
1693     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy;
1694     #if OPTION_DDR2
1695       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1696       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1697       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1698       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1699       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1700       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1701         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1702         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1703         #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1704       #else
1705         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1706         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1707         #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1708           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1709         #else
1710           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTFeatDef
1711         #endif
1712       #endif
1713       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1714         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1715       #else
1716         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1717       #endif
1718       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1719         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1720       #else
1721         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1722       #endif
1723       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1724         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1725       #else
1726         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1727       #endif
1728       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1729         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1730       #else
1731         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1732       #endif
1733       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1734         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1735       #else
1736         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1737       #endif
1738       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Hy = {
1739         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1740         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1741         TECH_TRAIN_SW_WL_DDR2,
1742         TECH_TRAIN_HW_WL_P1_DDR2,
1743         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1744         TECH_TRAIN_HW_WL_P2_DDR2,
1745         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1746         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1747         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1748         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1749         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1750         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1751         TECH_TRAIN_MAX_RD_LAT_DDR2,
1752         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2
1753       };
1754       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1755       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1756       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1757       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy },
1758     #else
1759       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1760       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1761       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1762       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1763       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1764       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1765       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1766       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1767       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1768       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1769       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1770       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1771       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1772       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1773     #endif
1774     #if OPTION_DDR3
1775       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1776       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1777       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1778       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1779       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1780         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1781         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1782       #else
1783         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1784         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1785       #endif
1786       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1787         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1788       #else
1789         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1790       #endif
1791       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1792         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1793           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1794         #endif
1795         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
1796         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1797           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1798         #endif
1799         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
1800         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
1801           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1802           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1803         #else
1804           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1805             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1806           #else
1807             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1808           #endif
1809         #endif
1810       #else
1811         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1812         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1813         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1814           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1815         #else
1816           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1817         #endif
1818       #endif
1819       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1820         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1821       #else
1822         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1823       #endif
1824       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1825         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1826       #else
1827         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1828       #endif
1829       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1830         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1831       #else
1832         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1833       #endif
1834       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1835         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1836       #else
1837         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1838       #endif
1839       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1840         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1841       #else
1842         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1843       #endif
1844       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Hy = {
1845         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1846         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1847         TECH_TRAIN_SW_WL_DDR3,
1848         TECH_TRAIN_HW_WL_P1_DDR3,
1849         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1850         TECH_TRAIN_HW_WL_P2_DDR3,
1851         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1852         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1853         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1854         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1855         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1856         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1857         TECH_TRAIN_MAX_RD_LAT_DDR3,
1858         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
1859       };
1860 //      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
1861       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1862 //      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
1863       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy },
1864     #else
1865       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1866       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1867       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1868       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1869       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1870       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1871       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1872       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1873       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1874       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1875       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1876       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1877       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1878       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1879       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1880       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1881     #endif
1882   #else
1883     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1884     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1885   #endif
1886
1887   #if OPTION_MEMCTLR_C32
1888     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32;
1889     #if OPTION_DDR2
1890       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1891       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1892       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1893       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1894       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1895       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1896         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1897         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1898         #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
1899       #else
1900         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1901         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1902         #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1903           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1904         #else
1905           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
1906         #endif
1907       #endif
1908       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1909         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1910       #else
1911         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1912       #endif
1913       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1914         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1915       #else
1916         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1917       #endif
1918       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1919         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1920       #else
1921         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1922       #endif
1923       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1924         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1925       #else
1926         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1927       #endif
1928       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1929         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1930       #else
1931         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1932       #endif
1933       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2C32 = {
1934         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1935         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1936         TECH_TRAIN_SW_WL_DDR2,
1937         TECH_TRAIN_HW_WL_P1_DDR2,
1938         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1939         TECH_TRAIN_HW_WL_P2_DDR2,
1940         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1941         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1942         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1943         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1944         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1945         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1946         TECH_TRAIN_MAX_RD_LAT_DDR2,
1947         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2
1948       };
1949       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1950       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1951       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1952       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 },
1953     #else
1954       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1955       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1956       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1957       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1958       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1959       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1960       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1961       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1962       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1963       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1964       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1965       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1966       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1967       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1968     #endif
1969     #if OPTION_DDR3
1970       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1971       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1972       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1973       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1974       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1975         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1976         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1977       #else
1978         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1979         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1980       #endif
1981       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1982         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1983       #else
1984         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1985       #endif
1986       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1987         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1988           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1989         #endif
1990         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
1991         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1992           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1993         #endif
1994         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
1995         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
1996           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
1997         #else
1998           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1999             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
2000           #else
2001             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
2002           #endif
2003         #endif
2004       #else
2005         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2006         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2007         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2008           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
2009         #else
2010           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
2011         #endif
2012       #endif
2013       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2014         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
2015       #else
2016         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2017       #endif
2018       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2019         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
2020       #else
2021         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2022       #endif
2023       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2024         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2025       #else
2026         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2027       #endif
2028       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2029         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2030       #else
2031         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2032       #endif
2033       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
2034         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
2035       #else
2036         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2037       #endif
2038       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3C32 = {
2039         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
2040         TECH_TRAIN_ENTER_HW_TRN_DDR3,
2041         TECH_TRAIN_SW_WL_DDR3,
2042         TECH_TRAIN_HW_WL_P1_DDR3,
2043         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
2044         TECH_TRAIN_HW_WL_P2_DDR3,
2045         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
2046         TECH_TRAIN_EXIT_HW_TRN_DDR3,
2047         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
2048         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
2049         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
2050         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
2051         TECH_TRAIN_MAX_RD_LAT_DDR3,
2052         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
2053       };
2054 //      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
2055       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
2056 //      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
2057       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 },
2058     #else
2059       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2060       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
2061       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2062       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
2063       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2064       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2065       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2066       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2067       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2068       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2069       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2070       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2071       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2072       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2073       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2074       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2075     #endif
2076   #else
2077     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2078     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2079   #endif
2080
2081
2082   #if OPTION_MEMCTLR_LN
2083     #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
2084     #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
2085     #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
2086     #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
2087     #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
2088     #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2089     #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
2090     #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2091     #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2092     #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2093     #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2094     #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
2095     #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2096     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2097     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN;
2098     #if OPTION_DDR3
2099       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2100       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTFeatDef
2101       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2102       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTrainingClient3
2103       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
2104         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
2105         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
2106       #else
2107         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2108         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2109       #endif
2110       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2111       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
2112         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
2113           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
2114         #endif
2115         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
2116         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
2117           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
2118         #endif
2119         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
2120         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
2121           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
2122           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
2123         #else
2124           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2125             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
2126           #else
2127             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
2128           #endif
2129         #endif
2130       #else
2131         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2132         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2133         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2134           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
2135         #else
2136           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
2137         #endif
2138       #endif
2139       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2140         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
2141       #else
2142         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2143       #endif
2144       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2145         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
2146       #else
2147         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2148       #endif
2149       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2150         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2151       #else
2152         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2153       #endif
2154       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2155         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2156       #else
2157         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2158       #endif
2159       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
2160         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
2161       #else
2162         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2163       #endif
2164       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3LN = {
2165         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
2166         TECH_TRAIN_ENTER_HW_TRN_DDR3,
2167         TECH_TRAIN_SW_WL_DDR3,
2168         TECH_TRAIN_HW_WL_P1_DDR3,
2169         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
2170         TECH_TRAIN_HW_WL_P2_DDR3,
2171         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
2172         TECH_TRAIN_EXIT_HW_TRN_DDR3,
2173         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
2174         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
2175         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
2176         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
2177         TECH_TRAIN_MAX_RD_LAT_DDR3,
2178         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
2179       };
2180 //      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
2181       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
2182 //      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
2183       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN },
2184     #else
2185       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2186       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
2187       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2188       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
2189       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2190       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2191       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2192       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2193       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2194       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2195       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2196       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2197       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2198       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2199       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2200       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2201     #endif
2202   #else
2203     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2204     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2205   #endif
2206
2207
2208   #if OPTION_MEMCTLR_OR
2209     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr;
2210     #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
2211     #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
2212     #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
2213     #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
2214     #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
2215     #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2216     #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
2217     #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2218     #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2219     #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2220     #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2221     #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
2222     #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2223     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2224     #if OPTION_DDR3
2225       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2226       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
2227       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2228       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
2229       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
2230         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
2231         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
2232       #else
2233         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2234         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2235       #endif
2236       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
2237         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
2238       #else
2239         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2240       #endif
2241       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
2242         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
2243           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
2244         #endif
2245         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
2246         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
2247           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
2248         #endif
2249         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
2250         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
2251           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
2252           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
2253         #else
2254           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2255             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
2256           #else
2257             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
2258           #endif
2259         #endif
2260       #else
2261         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2262         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2263         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2264           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
2265         #else
2266           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
2267         #endif
2268       #endif
2269       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2270         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
2271       #else
2272         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2273       #endif
2274       #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
2275       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2276         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
2277       #else
2278         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2279       #endif
2280       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2281         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2282       #else
2283         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2284       #endif
2285       #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
2286       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2287         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2288       #else
2289         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2290       #endif
2291       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
2292         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
2293       #else
2294         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2295       #endif
2296       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3OR = {
2297         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
2298         TECH_TRAIN_ENTER_HW_TRN_DDR3,
2299         TECH_TRAIN_SW_WL_DDR3,
2300         TECH_TRAIN_HW_WL_P1_DDR3,
2301         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
2302         TECH_TRAIN_HW_WL_P2_DDR3,
2303         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
2304         TECH_TRAIN_EXIT_HW_TRN_DDR3,
2305         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
2306         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
2307         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
2308         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
2309         TECH_TRAIN_MAX_RD_LAT_DDR3,
2310         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
2311       };
2312 //      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
2313       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
2314 //      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
2315       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR },
2316     #else
2317       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2318       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
2319       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2320       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
2321       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2322       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2323       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2324       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2325       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2326       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2327       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2328       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2329       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2330       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2331       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2332       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2333     #endif
2334   #else
2335     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2336     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2337   #endif
2338
2339
2340   #if OPTION_MEMCTLR_ON
2341     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON;
2342     #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
2343     #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
2344     #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
2345     #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
2346     #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
2347     #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2348     #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
2349     #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2350     #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2351     #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2352     #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2353     #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
2354     #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2355     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2356     #if OPTION_DDR3
2357       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2358       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTFeatDef
2359       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2360       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTrainingClient3
2361       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
2362         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
2363         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
2364       #else
2365         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2366         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2367       #endif
2368       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2369       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
2370         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
2371         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
2372         #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
2373           #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
2374           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
2375         #else
2376           #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2377             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
2378           #else
2379             #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
2380           #endif
2381         #endif
2382       #else
2383         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2384         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2385         #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2386           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
2387         #else
2388           #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
2389         #endif
2390       #endif
2391       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2392         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
2393       #else
2394         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2395       #endif
2396       #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
2397       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2398         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
2399       #else
2400         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2401       #endif
2402       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2403         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2404       #else
2405         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2406       #endif
2407       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2408         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2409       #else
2410         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2411       #endif
2412       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
2413         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
2414       #else
2415         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2416       #endif
2417       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3ON = {
2418         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
2419         TECH_TRAIN_ENTER_HW_TRN_DDR3,
2420         TECH_TRAIN_SW_WL_DDR3,
2421         TECH_TRAIN_HW_WL_P1_DDR3,
2422         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
2423         TECH_TRAIN_HW_WL_P2_DDR3,
2424         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
2425         TECH_TRAIN_EXIT_HW_TRN_DDR3,
2426         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
2427         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
2428         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
2429         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
2430         TECH_TRAIN_MAX_RD_LAT_DDR3,
2431         TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
2432       };
2433 //      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
2434       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
2435 //      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
2436       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON },
2437     #else
2438       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2439       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
2440       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2441       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
2442       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2443       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2444       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2445       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2446       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2447       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2448       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2449       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2450       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2451       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2452       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2453       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2454     #endif
2455   #else
2456     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2457     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2458   #endif
2459
2460   #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
2461   MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
2462     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR
2463     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA
2464     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY
2465     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN
2466     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32
2467     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON
2468     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni
2469     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR
2470     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH
2471     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB
2472     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
2473   };
2474
2475   MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
2476     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR
2477     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA
2478     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY
2479     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN
2480     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32
2481     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON
2482     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni
2483     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR
2484     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH
2485     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB
2486     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
2487   };
2488   /*---------------------------------------------------------------------------------------------------
2489    * NB TRAINING FLOW CONTROL
2490    *
2491    *
2492    *---------------------------------------------------------------------------------------------------
2493    */
2494   OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
2495     NB_TRAIN_FLOW_DDR2,
2496     NB_TRAIN_FLOW_DDR3,
2497   };
2498   /*---------------------------------------------------------------------------------------------------
2499    * TECHNOLOGY BLOCK
2500    *
2501    *
2502    *---------------------------------------------------------------------------------------------------
2503    */
2504   MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
2505     MEM_TECH_CONSTRUCTOR_DDR2
2506     MEM_TECH_CONSTRUCTOR_DDR3
2507     NULL
2508   };
2509    /*---------------------------------------------------------------------------------------------------
2510    * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
2511    *
2512    *
2513    *---------------------------------------------------------------------------------------------------
2514    */
2515   #if  OPTION_MEMCTLR_HY
2516     #if OPTION_UDIMMS
2517       #if OPTION_DDR2
2518         #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2519       #else
2520         #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2521       #endif
2522       #if OPTION_DDR3
2523         #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUHy3,
2524       #else
2525         #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
2526       #endif
2527     #else
2528       #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2529       #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
2530     #endif
2531     #if OPTION_RDIMMS
2532       #if OPTION_DDR2
2533         #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2534       #else
2535         #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2536       #endif
2537       #if OPTION_DDR3
2538         #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsRHy3,
2539       #else
2540         #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
2541       #endif
2542     #else
2543       #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2544       #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
2545     #endif
2546     #if OPTION_SODIMMS
2547       #if OPTION_DDR2
2548         #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2549       #else
2550         #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2551       #endif
2552       #if OPTION_DDR3
2553         #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsSHy3,
2554       #else
2555         #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
2556       #endif
2557     #else
2558       #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2559       #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
2560     #endif
2561   #else
2562     #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2563     #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2564     #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2565     #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
2566     #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
2567     #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
2568   #endif
2569   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
2570     PLAT_SP_HY_FF_UDIMM2
2571     PLAT_SP_HY_FF_RDIMM2
2572     PLAT_SP_HY_FF_SDIMM2
2573     PLAT_SP_HY_FF_UDIMM3
2574     PLAT_SP_HY_FF_RDIMM3
2575     PLAT_SP_HY_FF_SDIMM3
2576   };
2577
2578   #if OPTION_MEMCTLR_DR
2579     #if OPTION_UDIMMS
2580       #if OPTION_DDR2
2581         extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2;
2582         #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDr2,
2583       #else
2584         #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
2585       #endif
2586       #if OPTION_DDR3
2587         #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDr3,
2588       #else
2589         #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
2590       #endif
2591     #else
2592       #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
2593       #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
2594     #endif
2595     #if OPTION_RDIMMS
2596       #if OPTION_DDR2
2597         extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2;
2598         #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsRDr2,
2599       #else
2600         #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
2601       #endif
2602       #if OPTION_DDR3
2603         #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsRDr3,
2604       #else
2605         #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
2606       #endif
2607     #else
2608       #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
2609       #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
2610     #endif
2611     #if OPTION_SODIMMS
2612       #if OPTION_DDR2
2613         #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2614       #else
2615         #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2616       #endif
2617       #if OPTION_DDR3
2618         #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsSDr3,
2619       #else
2620         #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
2621       #endif
2622     #else
2623       #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2624       #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
2625     #endif
2626   #else
2627     #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2628     #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
2629     #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
2630     #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
2631     #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
2632     #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
2633   #endif
2634   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = {
2635     PLAT_SP_DR_FF_UDIMM2
2636     PLAT_SP_DR_FF_RDIMM2
2637     PLAT_SP_DR_FF_SDIMM2
2638     PLAT_SP_DR_FF_UDIMM3
2639     PLAT_SP_DR_FF_RDIMM3
2640     PLAT_SP_DR_FF_SDIMM3
2641   };
2642
2643   #if (OPTION_MEMCTLR_DA == TRUE)
2644     #if OPTION_UDIMMS
2645       #if OPTION_DDR2
2646         #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2647       #else
2648         #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2649       #endif
2650       #if OPTION_DDR3
2651         #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDA3,
2652       #else
2653         #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
2654       #endif
2655     #else
2656       #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2657       #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
2658     #endif
2659     #if OPTION_RDIMMS
2660       #if OPTION_DDR2
2661         #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2662       #else
2663         #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2664       #endif
2665       #if OPTION_DDR3
2666         #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2667       #else
2668         #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2669       #endif
2670     #else
2671       #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2672       #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2673     #endif
2674     #if OPTION_SODIMMS
2675       #if OPTION_DDR2
2676         #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsSDA2,
2677       #else
2678         #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
2679       #endif
2680       #if OPTION_DDR3
2681         #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsSDA3,
2682       #else
2683         #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
2684       #endif
2685     #else
2686       #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
2687       #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
2688     #endif
2689   #else
2690     #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
2691     #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2692     #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2693     #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
2694     #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2695     #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
2696   #endif
2697   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
2698     PLAT_SP_DA_FF_UDIMM2
2699     PLAT_SP_DA_FF_RDIMM2
2700     PLAT_SP_DA_FF_SDIMM2
2701     PLAT_SP_DA_FF_UDIMM3
2702     PLAT_SP_DA_FF_RDIMM3
2703     PLAT_SP_DA_FF_SDIMM3
2704   };
2705
2706   #if (OPTION_MEMCTLR_Ni == TRUE)
2707     #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
2708     #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
2709     #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
2710     #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsSNi3,
2711     #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
2712     #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUNi3,
2713   #else
2714     #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
2715     #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
2716     #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
2717     #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsUDef,
2718     #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
2719     #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUDef,
2720   #endif
2721   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
2722     PLAT_SP_NI_FF_UDIMM2
2723     PLAT_SP_NI_FF_RDIMM2
2724     PLAT_SP_NI_FF_SDIMM2
2725     PLAT_SP_NI_FF_UDIMM3
2726     PLAT_SP_NI_FF_RDIMM3
2727     PLAT_SP_NI_FF_SDIMM3
2728   };
2729
2730   #if (OPTION_MEMCTLR_PH == TRUE)
2731     #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
2732     #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
2733     #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
2734     #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsSPh3,
2735     #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
2736     #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUPh3,
2737   #else
2738     #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
2739     #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
2740     #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
2741     #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsUDef,
2742     #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
2743     #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUDef,
2744   #endif
2745   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
2746     PLAT_SP_PH_FF_UDIMM2
2747     PLAT_SP_PH_FF_RDIMM2
2748     PLAT_SP_PH_FF_SDIMM2
2749     PLAT_SP_PH_FF_UDIMM3
2750     PLAT_SP_PH_FF_RDIMM3
2751     PLAT_SP_PH_FF_SDIMM3
2752   };
2753
2754   #if (OPTION_MEMCTLR_RB == TRUE)
2755     #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
2756     #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
2757     #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
2758     #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsSRb3,
2759     #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
2760     #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsURb3,
2761   #else
2762     #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
2763     #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
2764     #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
2765     #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsUDef,
2766     #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
2767     #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsUDef,
2768   #endif
2769   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
2770     PLAT_SP_RB_FF_UDIMM2
2771     PLAT_SP_RB_FF_RDIMM2
2772     PLAT_SP_RB_FF_SDIMM2
2773     PLAT_SP_RB_FF_UDIMM3
2774     PLAT_SP_RB_FF_RDIMM3
2775     PLAT_SP_RB_FF_SDIMM3
2776   };
2777
2778   #if OPTION_MEMCTLR_LN
2779     #if OPTION_UDIMMS
2780       #if OPTION_DDR3
2781         #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsULN3,
2782       #else
2783         #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
2784       #endif
2785     #else
2786       #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
2787     #endif
2788     #if OPTION_SODIMMS
2789       #if OPTION_DDR3
2790         #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsSLN3,
2791       #else
2792         #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
2793       #endif
2794     #else
2795       #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
2796     #endif
2797   #else
2798     #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
2799     #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
2800   #endif
2801   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = {
2802     PLAT_SP_LN_FF_SDIMM3
2803     PLAT_SP_LN_FF_UDIMM3
2804     NULL
2805   };
2806
2807   #if  OPTION_MEMCTLR_C32
2808     #if OPTION_UDIMMS
2809       #if OPTION_DDR2
2810         #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2811       #else
2812         #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2813       #endif
2814       #if OPTION_DDR3
2815         #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUC32_3,
2816       #else
2817         #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
2818       #endif
2819     #else
2820       #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2821       #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
2822     #endif
2823     #if OPTION_RDIMMS
2824       #if OPTION_DDR2
2825         #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2826       #else
2827         #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2828       #endif
2829       #if OPTION_DDR3
2830         #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsRC32_3,
2831       #else
2832         #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
2833       #endif
2834     #else
2835       #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2836       #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
2837     #endif
2838     #if OPTION_SODIMMS
2839       #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
2840       #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
2841     #endif
2842   #else
2843     #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
2844     #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2845     #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2846     #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
2847     #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
2848     #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
2849   #endif
2850   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
2851     PLAT_SP_C32_FF_UDIMM2
2852     PLAT_SP_C32_FF_RDIMM2
2853     PLAT_SP_C32_FF_SDIMM2
2854     PLAT_SP_C32_FF_UDIMM3
2855     PLAT_SP_C32_FF_RDIMM3
2856     PLAT_SP_C32_FF_SDIMM3
2857   };
2858
2859   #if OPTION_MEMCTLR_ON
2860     #if OPTION_UDIMMS
2861       #if OPTION_DDR3
2862         #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUON3,
2863       #else
2864         #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
2865       #endif
2866     #else
2867       #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
2868     #endif
2869     #if OPTION_SODIMMS
2870       #if OPTION_DDR3
2871         #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsSON3,
2872       #else
2873         #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
2874       #endif
2875     #else
2876       #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
2877     #endif
2878   #else
2879     #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
2880     #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
2881   #endif
2882   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = {
2883     PLAT_SP_ON_FF_SDIMM3
2884     PLAT_SP_ON_FF_UDIMM3
2885     NULL
2886   };
2887
2888   /*---------------------------------------------------------------------------------------------------
2889    * PLATFORM-SPECIFIC CONFIGURATION
2890    *
2891    *
2892    *---------------------------------------------------------------------------------------------------
2893    */
2894
2895   #if OPTION_MEMCTLR_DR
2896     #if OPTION_UDIMMS
2897       #if OPTION_DDR2
2898         #define PSC_DR_UDIMM_DDR2     //MemAGetPsCfgUDr2
2899       #else
2900         #define PSC_DR_UDIMM_DDR2
2901       #endif
2902       #if OPTION_DDR3
2903         #define PSC_DR_UDIMM_DDR3    MemAGetPsCfgUDr3,
2904       #else
2905         #define PSC_DR_UDIMM_DDR3
2906       #endif
2907     #endif
2908     #if OPTION_RDIMMS
2909       #if OPTION_DDR2
2910         #define PSC_DR_RDIMM_DDR2    MemAGetPsCfgRDr2,
2911       #else
2912         #define PSC_DR_RDIMM_DDR2
2913       #endif
2914       #if OPTION_DDR3
2915         #define PSC_DR_RDIMM_DDR3    MemAGetPsCfgRDr3,
2916       #else
2917         #define PSC_DR_RDIMM_DDR3
2918       #endif
2919     #endif
2920     #if OPTION_SODIMMS
2921       #if OPTION_DDR2
2922         #define PSC_DR_SODIMM_DDR2    //MemAGetPsCfgSDr2
2923       #else
2924         #define PSC_DR_SODIMM_DDR2
2925       #endif
2926       #if OPTION_DDR3
2927         #define PSC_DR_SODIMM_DDR3    //MemAGetPsCfgSDr3
2928       #else
2929         #define PSC_DR_SODIMM_DDR3
2930       #endif
2931     #endif
2932   #endif
2933
2934   #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
2935     #if OPTION_MEMCTLR_Ni
2936       #define PSC_NI_UDIMM_DDR2
2937       #define PSC_NI_UDIMM_DDR3     MemAGetPsCfgUNi3,
2938       #define PSC_NI_RDIMM_DDR2
2939       #define PSC_NI_RDIMM_DDR3
2940       #define PSC_NI_SODIMM_DDR2
2941       #define PSC_NI_SODIMM_DDR3    MemAGetPsCfgSNi3,
2942     #endif
2943     #if OPTION_MEMCTLR_PH
2944       #define PSC_PH_UDIMM_DDR2
2945       #define PSC_PH_UDIMM_DDR3     MemAGetPsCfgUPh3,
2946       #define PSC_PH_RDIMM_DDR2
2947       #define PSC_PH_RDIMM_DDR3
2948       #define PSC_PH_SODIMM_DDR2
2949       #define PSC_PH_SODIMM_DDR3    MemAGetPsCfgSPh3,
2950     #endif
2951     #if OPTION_MEMCTLR_RB
2952       #define PSC_RB_UDIMM_DDR2
2953       #define PSC_RB_UDIMM_DDR3     MemAGetPsCfgURb3,
2954       #define PSC_RB_RDIMM_DDR2
2955       #define PSC_RB_RDIMM_DDR3
2956       #define PSC_RB_SODIMM_DDR2
2957       #define PSC_RB_SODIMM_DDR3    MemAGetPsCfgSRb3,
2958     #endif
2959     #if OPTION_MEMCTLR_DA
2960       #if OPTION_UDIMMS
2961         #if OPTION_DDR2
2962           #define PSC_DA_UDIMM_DDR2     //MemAGetPsCfgUDr2
2963         #else
2964           #define PSC_DA_UDIMM_DDR2
2965         #endif
2966         #if OPTION_DDR3
2967           #define PSC_DA_UDIMM_DDR3    MemAGetPsCfgUDA3,
2968         #else
2969           #define PSC_DA_UDIMM_DDR3
2970         #endif
2971       #endif
2972       #if OPTION_RDIMMS
2973         #if OPTION_DDR2
2974           #define PSC_DA_RDIMM_DDR2
2975         #else
2976           #define PSC_DA_RDIMM_DDR2
2977         #endif
2978         #if OPTION_DDR3
2979           #define PSC_DA_RDIMM_DDR3
2980         #else
2981           #define PSC_DA_RDIMM_DDR3
2982         #endif
2983       #endif
2984       #if OPTION_SODIMMS
2985         #if OPTION_DDR2
2986           #define PSC_DA_SODIMM_DDR2    MemAGetPsCfgSDA2,
2987         #else
2988           #define PSC_DA_SODIMM_DDR2
2989         #endif
2990         #if OPTION_DDR3
2991           #define PSC_DA_SODIMM_DDR3    MemAGetPsCfgSDA3,
2992         #else
2993           #define PSC_DA_SODIMM_DDR3
2994         #endif
2995       #endif
2996     #endif
2997   #endif
2998
2999   #if OPTION_MEMCTLR_HY
3000     #if OPTION_UDIMMS
3001       #if OPTION_DDR2
3002         #define PSC_HY_UDIMM_DDR2     //MemAGetPsCfgUDr2,
3003       #else
3004         #define PSC_HY_UDIMM_DDR2
3005       #endif
3006       #if OPTION_DDR3
3007         #define PSC_HY_UDIMM_DDR3    MemAGetPsCfgUHy3,
3008       #else
3009         #define PSC_HY_UDIMM_DDR3
3010       #endif
3011     #endif
3012     #if OPTION_RDIMMS
3013       #if OPTION_DDR2
3014         #define PSC_HY_RDIMM_DDR2
3015       #else
3016         #define PSC_HY_RDIMM_DDR2
3017       #endif
3018       #if OPTION_DDR3
3019         #define PSC_HY_RDIMM_DDR3    MemAGetPsCfgRHy3,
3020       #else
3021         #define PSC_HY_RDIMM_DDR3
3022       #endif
3023     #endif
3024     #if OPTION_SODIMMS
3025       #if OPTION_DDR2
3026         #define PSC_HY_SODIMM_DDR2    //MemAGetPsCfgSHy2,
3027       #else
3028         #define PSC_HY_SODIMM_DDR2
3029       #endif
3030       #if OPTION_DDR3
3031         #define PSC_HY_SODIMM_DDR3    //MemAGetPsCfgSHy3,
3032       #else
3033         #define PSC_HY_SODIMM_DDR3
3034       #endif
3035     #endif
3036   #endif
3037
3038   #if OPTION_MEMCTLR_C32
3039     #if OPTION_UDIMMS
3040       #if OPTION_DDR2
3041         #define PSC_C32_UDIMM_DDR2     //MemAGetPsCfgUDr2,
3042       #else
3043         #define PSC_C32_UDIMM_DDR2
3044       #endif
3045       #if OPTION_DDR3
3046         #define PSC_C32_UDIMM_DDR3    MemAGetPsCfgUC32_3,
3047       #else
3048         #define PSC_C32_UDIMM_DDR3
3049       #endif
3050     #endif
3051     #if OPTION_RDIMMS
3052       #if OPTION_DDR2
3053         #define PSC_C32_RDIMM_DDR2
3054       #else
3055         #define PSC_C32_RDIMM_DDR2
3056       #endif
3057       #if OPTION_DDR3
3058         #define PSC_C32_RDIMM_DDR3    MemAGetPsCfgRC32_3,
3059       #else
3060         #define PSC_C32_RDIMM_DDR3
3061       #endif
3062     #endif
3063     #if OPTION_SODIMMS
3064       #if OPTION_DDR2
3065         #define PSC_C32_SODIMM_DDR2    //MemAGetPsCfgSC32_2,
3066       #else
3067         #define PSC_C32_SODIMM_DDR2
3068       #endif
3069       #if OPTION_DDR3
3070         #define PSC_C32_SODIMM_DDR3    //MemAGetPsCfgSC32_3,
3071       #else
3072         #define PSC_C32_SODIMM_DDR3
3073       #endif
3074     #endif
3075   #endif
3076
3077   #if OPTION_MEMCTLR_LN
3078     #if OPTION_UDIMMS
3079       #if OPTION_DDR2
3080         #define PSC_LN_UDIMM_DDR2     //MemAGetPsCfgULN2,
3081       #else
3082         #define PSC_LN_UDIMM_DDR2
3083       #endif
3084       #if OPTION_DDR3
3085         #define PSC_LN_UDIMM_DDR3    MemAGetPsCfgULN3,
3086       #else
3087         #define PSC_LN_UDIMM_DDR3
3088       #endif
3089     #endif
3090     #if OPTION_RDIMMS
3091       #if OPTION_DDR2
3092         #define PSC_LN_RDIMM_DDR2
3093       #else
3094         #define PSC_LN_RDIMM_DDR2
3095       #endif
3096       #if OPTION_DDR3
3097         #define PSC_LN_RDIMM_DDR3    //MemAGetPsCfgRLN3,
3098       #else
3099         #define PSC_LN_RDIMM_DDR3
3100       #endif
3101     #endif
3102     #if OPTION_SODIMMS
3103       #if OPTION_DDR2
3104         #define PSC_LN_SODIMM_DDR2    //MemAGetPsCfgSLN2,
3105       #else
3106         #define PSC_LN_SODIMM_DDR2
3107       #endif
3108       #if OPTION_DDR3
3109         #define PSC_LN_SODIMM_DDR3   MemAGetPsCfgSLN3,
3110       #else
3111         #define PSC_LN_SODIMM_DDR3
3112       #endif
3113     #endif
3114   #endif
3115
3116   #if OPTION_MEMCTLR_OR
3117     #if OPTION_UDIMMS
3118       #if OPTION_DDR2
3119         #define PSC_OR_UDIMM_DDR2     //MemAGetPsCfgUOr2,
3120       #else
3121         #define PSC_OR_UDIMM_DDR2
3122       #endif
3123       #if OPTION_DDR3
3124         #define PSC_OR_UDIMM_DDR3     //MemAGetPsCfgUOr3,
3125       #else
3126         #define PSC_OR_UDIMM_DDR3
3127       #endif
3128     #endif
3129     #if OPTION_RDIMMS
3130       #if OPTION_DDR2
3131         #define PSC_OR_RDIMM_DDR2
3132       #else
3133         #define PSC_OR_RDIMM_DDR2
3134       #endif
3135       #if OPTION_DDR3
3136         #define PSC_OR_RDIMM_DDR3     //MemAGetPsCfgROr3,
3137       #else
3138         #define PSC_OR_RDIMM_DDR3
3139       #endif
3140     #endif
3141     #if OPTION_SODIMMS
3142       #if OPTION_DDR2
3143         #define PSC_OR_SODIMM_DDR2    //MemAGetPsCfgSOr2,
3144       #else
3145         #define PSC_OR_SODIMM_DDR2
3146       #endif
3147       #if OPTION_DDR3
3148         #define PSC_OR_SODIMM_DDR3    //MemAGetPsCfgSOr3,
3149       #else
3150         #define PSC_OR_SODIMM_DDR3
3151       #endif
3152     #endif
3153   #endif
3154
3155   #if OPTION_MEMCTLR_ON
3156     #if OPTION_UDIMMS
3157       #if OPTION_DDR2
3158         #define PSC_ON_UDIMM_DDR2     //MemAGetPsCfgUON2,
3159       #else
3160         #define PSC_ON_UDIMM_DDR2
3161       #endif
3162       #if OPTION_DDR3
3163         #define PSC_ON_UDIMM_DDR3    MemAGetPsCfgUON3,
3164       #else
3165         #define PSC_ON_UDIMM_DDR3
3166       #endif
3167     #endif
3168     #if OPTION_RDIMMS
3169       #if OPTION_DDR2
3170         #define PSC_ON_RDIMM_DDR2
3171       #else
3172         #define PSC_ON_RDIMM_DDR2
3173       #endif
3174       #if OPTION_DDR3
3175         #define PSC_ON_RDIMM_DDR3    //MemAGetPsCfgRON3,
3176       #else
3177         #define PSC_ON_RDIMM_DDR3
3178       #endif
3179     #endif
3180     #if OPTION_SODIMMS
3181       #if OPTION_DDR2
3182         #define PSC_ON_SODIMM_DDR2    //MemAGetPsCfgSON2,
3183       #else
3184         #define PSC_ON_SODIMM_DDR2
3185       #endif
3186       #if OPTION_DDR3
3187         #define PSC_ON_SODIMM_DDR3   MemAGetPsCfgSON3,
3188       #else
3189         #define PSC_ON_SODIMM_DDR3
3190       #endif
3191     #endif
3192   #endif
3193
3194   /*----------------------------------------------------------------------
3195    * DEFAULT PSCFG DEFINITIONS
3196    *
3197    *----------------------------------------------------------------------
3198    */
3199
3200   #ifndef PSC_DR_UDIMM_DDR2
3201     #define PSC_DR_UDIMM_DDR2
3202   #endif
3203   #ifndef PSC_DR_RDIMM_DDR2
3204     #define PSC_DR_RDIMM_DDR2
3205   #endif
3206   #ifndef PSC_DR_SODIMM_DDR2
3207     #define PSC_DR_SODIMM_DDR2
3208   #endif
3209   #ifndef PSC_DR_UDIMM_DDR3
3210     #define PSC_DR_UDIMM_DDR3
3211   #endif
3212   #ifndef PSC_DR_RDIMM_DDR3
3213     #define PSC_DR_RDIMM_DDR3
3214   #endif
3215   #ifndef PSC_DR_SODIMM_DDR3
3216     #define PSC_DR_SODIMM_DDR3
3217   #endif
3218   #ifndef PSC_RB_UDIMM_DDR2
3219     #define PSC_RB_UDIMM_DDR2
3220   #endif
3221   #ifndef PSC_RB_RDIMM_DDR2
3222     #define PSC_RB_RDIMM_DDR2
3223   #endif
3224   #ifndef PSC_RB_SODIMM_DDR2
3225     #define PSC_RB_SODIMM_DDR2
3226   #endif
3227   #ifndef PSC_RB_UDIMM_DDR3
3228     #define PSC_RB_UDIMM_DDR3
3229   #endif
3230   #ifndef PSC_RB_RDIMM_DDR3
3231     #define PSC_RB_RDIMM_DDR3
3232   #endif
3233   #ifndef PSC_RB_SODIMM_DDR3
3234     #define PSC_RB_SODIMM_DDR3
3235   #endif
3236   #ifndef PSC_DA_UDIMM_DDR2
3237     #define PSC_DA_UDIMM_DDR2
3238   #endif
3239   #ifndef PSC_DA_RDIMM_DDR2
3240     #define PSC_DA_RDIMM_DDR2
3241   #endif
3242   #ifndef PSC_DA_SODIMM_DDR2
3243     #define PSC_DA_SODIMM_DDR2
3244   #endif
3245   #ifndef PSC_DA_UDIMM_DDR3
3246     #define PSC_DA_UDIMM_DDR3
3247   #endif
3248   #ifndef PSC_DA_RDIMM_DDR3
3249     #define PSC_DA_RDIMM_DDR3
3250   #endif
3251   #ifndef PSC_DA_SODIMM_DDR3
3252     #define PSC_DA_SODIMM_DDR3
3253   #endif
3254   #ifndef PSC_NI_UDIMM_DDR2
3255     #define PSC_NI_UDIMM_DDR2
3256   #endif
3257   #ifndef PSC_NI_RDIMM_DDR2
3258     #define PSC_NI_RDIMM_DDR2
3259   #endif
3260   #ifndef PSC_NI_SODIMM_DDR2
3261     #define PSC_NI_SODIMM_DDR2
3262   #endif
3263   #ifndef PSC_NI_UDIMM_DDR3
3264     #define PSC_NI_UDIMM_DDR3
3265   #endif
3266   #ifndef PSC_NI_RDIMM_DDR3
3267     #define PSC_NI_RDIMM_DDR3
3268   #endif
3269   #ifndef PSC_NI_SODIMM_DDR3
3270     #define PSC_NI_SODIMM_DDR3
3271   #endif
3272   #ifndef PSC_PH_UDIMM_DDR2
3273     #define PSC_PH_UDIMM_DDR2
3274   #endif
3275   #ifndef PSC_PH_RDIMM_DDR2
3276     #define PSC_PH_RDIMM_DDR2
3277   #endif
3278   #ifndef PSC_PH_SODIMM_DDR2
3279     #define PSC_PH_SODIMM_DDR2
3280   #endif
3281   #ifndef PSC_PH_UDIMM_DDR3
3282     #define PSC_PH_UDIMM_DDR3
3283   #endif
3284   #ifndef PSC_PH_RDIMM_DDR3
3285     #define PSC_PH_RDIMM_DDR3
3286   #endif
3287   #ifndef PSC_PH_SODIMM_DDR3
3288     #define PSC_PH_SODIMM_DDR3
3289   #endif
3290   #ifndef PSC_HY_UDIMM_DDR2
3291     #define PSC_HY_UDIMM_DDR2
3292   #endif
3293   #ifndef PSC_HY_RDIMM_DDR2
3294     #define PSC_HY_RDIMM_DDR2
3295   #endif
3296   #ifndef PSC_HY_SODIMM_DDR2
3297     #define PSC_HY_SODIMM_DDR2
3298   #endif
3299   #ifndef PSC_HY_UDIMM_DDR3
3300     #define PSC_HY_UDIMM_DDR3
3301   #endif
3302   #ifndef PSC_HY_RDIMM_DDR3
3303     #define PSC_HY_RDIMM_DDR3
3304   #endif
3305   #ifndef PSC_HY_SODIMM_DDR3
3306     #define PSC_HY_SODIMM_DDR3
3307   #endif
3308   #ifndef PSC_LN_UDIMM_DDR2
3309     #define PSC_LN_UDIMM_DDR2
3310   #endif
3311   #ifndef PSC_LN_RDIMM_DDR2
3312     #define PSC_LN_RDIMM_DDR2
3313   #endif
3314   #ifndef PSC_LN_SODIMM_DDR2
3315     #define PSC_LN_SODIMM_DDR2
3316   #endif
3317   #ifndef PSC_LN_UDIMM_DDR3
3318     #define PSC_LN_UDIMM_DDR3
3319   #endif
3320   #ifndef PSC_LN_RDIMM_DDR3
3321     #define PSC_LN_RDIMM_DDR3
3322   #endif
3323   #ifndef PSC_LN_SODIMM_DDR3
3324     #define PSC_LN_SODIMM_DDR3
3325   #endif
3326   #ifndef PSC_OR_UDIMM_DDR2
3327     #define PSC_OR_UDIMM_DDR2
3328   #endif
3329   #ifndef PSC_OR_RDIMM_DDR2
3330     #define PSC_OR_RDIMM_DDR2
3331   #endif
3332   #ifndef PSC_OR_SODIMM_DDR2
3333     #define PSC_OR_SODIMM_DDR2
3334   #endif
3335   #ifndef PSC_OR_UDIMM_DDR3
3336     #define PSC_OR_UDIMM_DDR3
3337   #endif
3338   #ifndef PSC_OR_RDIMM_DDR3
3339     #define PSC_OR_RDIMM_DDR3
3340   #endif
3341   #ifndef PSC_OR_SODIMM_DDR3
3342     #define PSC_OR_SODIMM_DDR3
3343   #endif
3344   #ifndef PSC_C32_UDIMM_DDR3
3345     #define PSC_C32_UDIMM_DDR3
3346   #endif
3347   #ifndef PSC_C32_RDIMM_DDR3
3348     #define PSC_C32_RDIMM_DDR3
3349   #endif
3350   #ifndef PSC_ON_UDIMM_DDR2
3351     #define PSC_ON_UDIMM_DDR2
3352   #endif
3353   #ifndef PSC_ON_RDIMM_DDR2
3354     #define PSC_ON_RDIMM_DDR2
3355   #endif
3356   #ifndef PSC_ON_SODIMM_DDR2
3357     #define PSC_ON_SODIMM_DDR2
3358   #endif
3359   #ifndef PSC_ON_UDIMM_DDR3
3360     #define PSC_ON_UDIMM_DDR3
3361   #endif
3362   #ifndef PSC_ON_RDIMM_DDR3
3363     #define PSC_ON_RDIMM_DDR3
3364   #endif
3365   #ifndef PSC_ON_SODIMM_DDR3
3366     #define PSC_ON_SODIMM_DDR3
3367   #endif
3368
3369   MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
3370     PSC_DR_UDIMM_DDR2
3371     PSC_DR_RDIMM_DDR2
3372     PSC_DR_SODIMM_DDR2
3373     PSC_DR_UDIMM_DDR3
3374     PSC_DR_RDIMM_DDR3
3375     PSC_DR_SODIMM_DDR3
3376     PSC_RB_UDIMM_DDR3
3377     PSC_RB_SODIMM_DDR3
3378     PSC_DA_SODIMM_DDR2
3379     PSC_DA_UDIMM_DDR3
3380     PSC_DA_SODIMM_DDR3
3381     PSC_NI_UDIMM_DDR3
3382     PSC_NI_SODIMM_DDR3
3383     PSC_PH_UDIMM_DDR3
3384     PSC_PH_SODIMM_DDR3
3385     PSC_HY_UDIMM_DDR3
3386     PSC_HY_RDIMM_DDR3
3387     PSC_HY_SODIMM_DDR3
3388     PSC_LN_UDIMM_DDR3
3389     PSC_LN_RDIMM_DDR3
3390     PSC_LN_SODIMM_DDR3
3391     PSC_OR_UDIMM_DDR3
3392     PSC_OR_RDIMM_DDR3
3393     PSC_OR_SODIMM_DDR3
3394     PSC_C32_UDIMM_DDR3
3395     PSC_C32_RDIMM_DDR3
3396     PSC_ON_UDIMM_DDR3
3397     PSC_ON_RDIMM_DDR3
3398     PSC_ON_SODIMM_DDR3
3399     NULL
3400   };
3401   CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
3402 /* SIZE_OF_PLATFORM is not defined when the preprocessor runs
3403  * Removing this test for coreboot.
3404  */
3405 #if RUN_BROKEN_AGESA_TESTS
3406   #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
3407     #error   Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
3408   #endif
3409 #endif
3410
3411   /*---------------------------------------------------------------------------------------------------
3412    * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
3413    *
3414    *
3415    *---------------------------------------------------------------------------------------------------
3416    */
3417   #define MEM_PSC_FLOW_BLOCK_END NULL
3418   #define PSC_TBL_END NULL
3419   #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
3420
3421   #if OPTION_MEMCTLR_OR
3422     #if OPTION_UDIMMS
3423       #if OPTION_AM3_SOCKET_SUPPORT
3424         extern PSC_TBL_ENTRY MaxFreqTblEntUAM3;
3425         #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3  &MaxFreqTblEntUAM3,
3426         extern PSC_TBL_ENTRY DramTermTblEntUAM3;
3427         #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3  &DramTermTblEntUAM3,
3428         extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3;
3429         #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3  &OdtPat1DTblEntUAM3,
3430         extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3;
3431         #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3  &OdtPat2DTblEntUAM3,
3432         extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3;
3433         #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3  &OdtPat3DTblEntUAM3,
3434         extern PSC_TBL_ENTRY SAOTblEntUAM3;
3435         #define PSC_TBL_OR_UDIMM3_SAO_AM3  &SAOTblEntUAM3,
3436         extern PSC_TBL_ENTRY ClkDisMapEntUAM3;
3437         #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3,
3438       #endif
3439       #if OPTION_C32_SOCKET_SUPPORT
3440         extern PSC_TBL_ENTRY MaxFreqTblEntUC32;
3441         #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32  &MaxFreqTblEntUC32,
3442         extern PSC_TBL_ENTRY DramTermTblEntUC32;
3443         #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32  &DramTermTblEntUC32,
3444         extern PSC_TBL_ENTRY OdtPat1DTblEntUC32;
3445         #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntUC32,
3446         extern PSC_TBL_ENTRY OdtPat2DTblEntUC32;
3447         #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32  &OdtPat2DTblEntUC32,
3448         extern PSC_TBL_ENTRY OdtPat3DTblEntUC32;
3449         #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntUC32,
3450         extern PSC_TBL_ENTRY SAOTblEntUC32;
3451         #define PSC_TBL_OR_UDIMM3_SAO_C32  &SAOTblEntUC32,
3452         extern PSC_TBL_ENTRY ClkDisMapEntUC32;
3453         #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32,
3454         extern PSC_TBL_ENTRY ClkDisMap3DEntUC32;
3455         #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32,
3456       #endif
3457       #if OPTION_G34_SOCKET_SUPPORT
3458         extern PSC_TBL_ENTRY MaxFreqTblEntUG34;
3459         #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34  &MaxFreqTblEntUG34,
3460         extern PSC_TBL_ENTRY DramTermTblEntUG34;
3461         #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34  &DramTermTblEntUG34,
3462         extern PSC_TBL_ENTRY OdtPat1DTblEntUG34;
3463         #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntUG34,
3464         extern PSC_TBL_ENTRY OdtPat2DTblEntUG34;
3465         #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34  &OdtPat2DTblEntUG34,
3466         extern PSC_TBL_ENTRY OdtPat3DTblEntUG34;
3467         #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntUG34,
3468         extern PSC_TBL_ENTRY SAOTblEntUG34;
3469         #define PSC_TBL_OR_UDIMM3_SAO_G34  &SAOTblEntUG34,
3470         extern PSC_TBL_ENTRY ClkDisMapEntUG34;
3471         #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34,
3472       #endif
3473     #endif
3474     #if OPTION_RDIMMS
3475       #if OPTION_C32_SOCKET_SUPPORT
3476         extern PSC_TBL_ENTRY MaxFreqTblEntRC32;
3477         #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32  &MaxFreqTblEntRC32,
3478         extern PSC_TBL_ENTRY DramTermTblEntRC32;
3479         #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32  &DramTermTblEntRC32,
3480         extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
3481         #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntRC32,
3482         extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
3483         #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32  &OdtPat2DTblEntRC32,
3484         extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
3485         #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntRC32,
3486         extern PSC_TBL_ENTRY SAOTblEntRC32;
3487         #define PSC_TBL_OR_RDIMM3_SAO_C32  &SAOTblEntRC32,
3488         extern PSC_TBL_ENTRY RC2IBTTblEntRC32;
3489         #define PSC_TBL_OR_RDIMM3_RC2IBT_C32  &RC2IBTTblEntRC32,
3490         extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32;
3491         #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32  &RC10OpSpdTblEntRC32,
3492         extern PSC_TBL_ENTRY ClkDisMapEntRC32;
3493         #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32,
3494       #endif
3495       #if OPTION_G34_SOCKET_SUPPORT
3496         extern PSC_TBL_ENTRY MaxFreqTblEntRG34;
3497         #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34  &MaxFreqTblEntRG34,
3498         extern PSC_TBL_ENTRY DramTermTblEntRG34;
3499         #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34  &DramTermTblEntRG34,
3500         extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
3501         #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntRG34,
3502         extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
3503         #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34  &OdtPat2DTblEntRG34,
3504         extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
3505         #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntRG34,
3506         extern PSC_TBL_ENTRY SAOTblEntRG34;
3507         #define PSC_TBL_OR_RDIMM3_SAO_G34  &SAOTblEntRG34,
3508         extern PSC_TBL_ENTRY RC2IBTTblEntRG34;
3509         #define PSC_TBL_OR_RDIMM3_RC2IBT_G34  &RC2IBTTblEntRG34,
3510         extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34;
3511         #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34  &RC10OpSpdTblEntRG34,
3512         extern PSC_TBL_ENTRY ClkDisMapEntRG34;
3513         #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34,
3514       #endif
3515     #endif
3516     //#if OPTION_SODIMMS
3517     //#endif
3518     //#if OPTION_LRDIMMS
3519     //  #if OPTION_C32_SOCKET_SUPPORT
3520     //    extern PSC_TBL_ENTRY MaxFreqTblEntLRC32;
3521     //    #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32  &MaxFreqTblEntLRC32,
3522     //    extern PSC_TBL_ENTRY DramTermTblEntLRC32;
3523     //    #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32  &DramTermTblEntLRC32,
3524     //    extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
3525     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntLRC32,
3526     //    extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
3527     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32  &OdtPat2DTblEntLRC32,
3528     //    extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
3529     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntLRC32,
3530     //    extern PSC_TBL_ENTRY SAOTblEntRC32;
3531     //    #define PSC_TBL_OR_LRDIMM3_SAO_C32  &SAOTblEntLRC32,
3532     //    extern PSC_TBL_ENTRY IBTTblEntLRC32;
3533     //    #define PSC_TBL_OR_LRDIMM3_IBT_C32  &IBTTblEntLRC32,
3534     //    extern PSC_TBL_ENTRY ClkDisMapEntLRC32;
3535     //    #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32,
3536     //  #endif
3537     //  #if OPTION_G34_SOCKET_SUPPORT
3538     //    extern PSC_TBL_ENTRY MaxFreqTblEntLRG34;
3539     //    #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34  &MaxFreqTblEntLRG34,
3540     //    extern PSC_TBL_ENTRY DramTermTblEntLRG34;
3541     //    #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34  &DramTermTblEntLRG34,
3542     //    extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
3543     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntLRG34,
3544     //    extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
3545     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34  &OdtPat2DTblEntLRG34,
3546     //    extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
3547     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntLRG34,
3548     //    extern PSC_TBL_ENTRY SAOTblEntRG34;
3549     //    #define PSC_TBL_OR_LRDIMM3_SAO_G34  &SAOTblEntLRG34,
3550     //    extern PSC_TBL_ENTRY IBTTblEntLRG34;
3551     //    #define PSC_TBL_OR_LRDIMM3_IBT_G34  &IBTTblEntLRG34,
3552     //    extern PSC_TBL_ENTRY ClkDisMapEntLRG34;
3553     //    #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34,
3554     //  #endif
3555     //#endif
3556     extern PSC_TBL_ENTRY MR0WrTblEntry;
3557     #define PSC_TBL_OR_MR0_WR  &MR0WrTblEntry,
3558     extern PSC_TBL_ENTRY MR0CLTblEntry;
3559     #define PSC_TBL_OR_MR0_CL  &MR0CLTblEntry,
3560     extern PSC_TBL_ENTRY OrDdr3CKETriEnt;
3561     #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt,
3562     extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt;
3563     #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt,
3564     extern PSC_TBL_ENTRY OrDdr3ODTTriEnt;
3565     #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt,
3566     extern PSC_TBL_ENTRY OrUDdr3CSTriEnt;
3567     #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt,
3568     extern PSC_TBL_ENTRY OrDdr3CSTriEnt;
3569     #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt,
3570     extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt;
3571     #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt,
3572     extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt;
3573     #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt,
3574
3575     #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
3576       #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
3577     #endif
3578     #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
3579       #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
3580     #endif
3581     #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
3582       #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
3583     #endif
3584     #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
3585       #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
3586     #endif
3587     #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
3588       #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
3589     #endif
3590     #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
3591       #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
3592     #endif
3593     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
3594       #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
3595     #endif
3596     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
3597       #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
3598     #endif
3599     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
3600       #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
3601     #endif
3602     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
3603       #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
3604     #endif
3605     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
3606       #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
3607     #endif
3608     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
3609       #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
3610     #endif
3611     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
3612       #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
3613     #endif
3614     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
3615       #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
3616     #endif
3617     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
3618       #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
3619     #endif
3620     #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3
3621       #define PSC_TBL_OR_UDIMM3_SAO_AM3
3622     #endif
3623     #ifndef PSC_TBL_OR_UDIMM3_SAO_C32
3624       #define PSC_TBL_OR_UDIMM3_SAO_C32
3625     #endif
3626     #ifndef PSC_TBL_OR_UDIMM3_SAO_G34
3627       #define PSC_TBL_OR_UDIMM3_SAO_G34
3628     #endif
3629     #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
3630       #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
3631     #endif
3632     #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
3633       #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
3634     #endif
3635     #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
3636       #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
3637     #endif
3638     #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
3639       #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
3640     #endif
3641     #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
3642       #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
3643     #endif
3644     #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
3645       #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
3646     #endif
3647     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
3648       #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
3649     #endif
3650     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
3651       #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
3652     #endif
3653     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
3654       #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
3655     #endif
3656     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
3657       #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
3658     #endif
3659     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
3660       #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
3661     #endif
3662     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
3663       #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
3664     #endif
3665     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
3666       #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
3667     #endif
3668     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
3669       #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
3670     #endif
3671     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
3672       #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
3673     #endif
3674     #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3
3675       #define PSC_TBL_OR_RDIMM3_SAO_AM3
3676     #endif
3677     #ifndef PSC_TBL_OR_RDIMM3_SAO_C32
3678       #define PSC_TBL_OR_RDIMM3_SAO_C32
3679     #endif
3680     #ifndef PSC_TBL_OR_RDIMM3_SAO_G34
3681       #define PSC_TBL_OR_RDIMM3_SAO_G34
3682     #endif
3683     #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3
3684       #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3
3685     #endif
3686     #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32
3687       #define PSC_TBL_OR_RDIMM3_RC2IBT_C32
3688     #endif
3689     #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34
3690       #define PSC_TBL_OR_RDIMM3_RC2IBT_G34
3691     #endif
3692     #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
3693       #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
3694     #endif
3695     #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
3696       #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
3697     #endif
3698     #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
3699       #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
3700     #endif
3701     #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
3702       #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
3703     #endif
3704     #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
3705       #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
3706     #endif
3707     #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
3708       #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
3709     #endif
3710     #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
3711       #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
3712     #endif
3713     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
3714       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
3715     #endif
3716     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
3717       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
3718     #endif
3719     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
3720       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
3721     #endif
3722     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
3723       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
3724     #endif
3725     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
3726       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
3727     #endif
3728     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
3729       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
3730     #endif
3731     #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32
3732       #define PSC_TBL_OR_LRDIMM3_SAO_C32
3733     #endif
3734     #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34
3735       #define PSC_TBL_OR_LRDIMM3_SAO_G34
3736     #endif
3737     #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32
3738       #define PSC_TBL_OR_LRDIMM3_IBT_C32
3739     #endif
3740     #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34
3741       #define PSC_TBL_OR_LRDIMM3_IBT_G34
3742     #endif
3743     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
3744       #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
3745     #endif
3746     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32
3747       #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32
3748     #endif
3749     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
3750       #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
3751     #endif
3752     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34
3753       #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34
3754     #endif
3755     #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32
3756       #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32
3757     #endif
3758     #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34
3759       #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34
3760     #endif
3761     #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
3762       #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
3763     #endif
3764     #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
3765       #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
3766     #endif
3767
3768     PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = {
3769       PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
3770       PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
3771       PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
3772       PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
3773       PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
3774       PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
3775       PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
3776       PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
3777       PSC_TBL_END
3778     };
3779
3780     PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = {
3781       PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
3782       PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
3783       PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
3784       PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
3785       PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
3786       PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
3787       PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
3788       PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
3789       PSC_TBL_END
3790     };
3791
3792     PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = {
3793       PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
3794       PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
3795       PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
3796       PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
3797       PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
3798       PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
3799       PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
3800       PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
3801       PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
3802       PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
3803       PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
3804       PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
3805       PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
3806       PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
3807       PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
3808       PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
3809       PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
3810       PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
3811       PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
3812       PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
3813       PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
3814       PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
3815       PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
3816       PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
3817       PSC_TBL_END
3818     };
3819
3820     PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = {
3821       PSC_TBL_OR_UDIMM3_SAO_AM3
3822       PSC_TBL_OR_UDIMM3_SAO_C32
3823       PSC_TBL_OR_UDIMM3_SAO_G34
3824       PSC_TBL_OR_RDIMM3_SAO_AM3
3825       PSC_TBL_OR_RDIMM3_SAO_C32
3826       PSC_TBL_OR_RDIMM3_SAO_G34
3827       PSC_TBL_OR_LRDIMM3_SAO_C32
3828       PSC_TBL_OR_LRDIMM3_SAO_G34
3829       PSC_TBL_END
3830     };
3831
3832     PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = {
3833       PSC_TBL_OR_MR0_WR
3834       PSC_TBL_END
3835     };
3836
3837     PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = {
3838       PSC_TBL_OR_MR0_CL
3839       PSC_TBL_END
3840     };
3841
3842     PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = {
3843       PSC_TBL_OR_RDIMM3_RC2IBT_AM3
3844       PSC_TBL_OR_RDIMM3_RC2IBT_C32
3845       PSC_TBL_OR_RDIMM3_RC2IBT_G34
3846       PSC_TBL_END
3847     };
3848
3849     PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = {
3850       PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
3851       PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
3852       PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
3853       PSC_TBL_END
3854     };
3855
3856     PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = {
3857       PSC_TBL_OR_LRDIMM3_IBT_C32
3858       PSC_TBL_OR_LRDIMM3_IBT_G34
3859       PSC_TBL_END
3860     };
3861
3862     PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = {
3863       PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
3864       PSC_TBL_OR_UDIMM3_CLK_DIS_C32
3865       PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
3866       PSC_TBL_OR_UDIMM3_CLK_DIS_G34
3867       PSC_TBL_OR_RDIMM3_CLK_DIS_C32
3868       PSC_TBL_OR_RDIMM3_CLK_DIS_G34
3869       PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
3870       PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
3871       PSC_TBL_OR_CKE_TRI
3872       PSC_TBL_OR_ODT_TRI_3D
3873       PSC_TBL_OR_ODT_TRI
3874       PSC_TBL_OR_LRDIMM3_ODT_TRI_3D
3875       PSC_TBL_OR_LRDIMM3_ODT_TRI
3876       PSC_TBL_OR_UDIMM3_CS_TRI
3877       PSC_TBL_OR_CS_TRI
3878       PSC_TBL_END
3879     };
3880
3881     MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = {
3882       (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR,
3883       (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR,
3884       (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR,
3885       (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR,
3886       (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR,
3887       (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR,
3888       (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR,
3889       (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR,
3890       (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR,
3891       NULL,
3892       NULL,
3893       (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR
3894     };
3895
3896     extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
3897     #define PSC_FLOW_OR_MAX_FREQ   MemPGetMaxFreqSupported
3898     extern MEM_PSC_FLOW MemPGetRttNomWr;
3899     #define PSC_FLOW_OR_DRAM_TERM   MemPGetRttNomWr
3900     extern MEM_PSC_FLOW MemPGetODTPattern;
3901     #define PSC_FLOW_OR_ODT_PATTERN   MemPGetODTPattern
3902     extern MEM_PSC_FLOW MemPGetSAO;
3903     #define PSC_FLOW_OR_SAO   MemPGetSAO
3904     extern MEM_PSC_FLOW MemPGetMR0WrCL;
3905     #define PSC_FLOW_OR_MR0_WRCL   MemPGetMR0WrCL
3906     #if OPTION_RDIMMS
3907       extern MEM_PSC_FLOW MemPGetRC2IBT;
3908       #define PSC_FLOW_OR_RC2_IBT    MemPGetRC2IBT
3909       extern MEM_PSC_FLOW MemPGetRC10OpSpd;
3910       #define PSC_FLOW_OR_RC10_OPSPD   MemPGetRC10OpSpd
3911     #endif
3912     //#if OPTION_LRDIMMS
3913     //extern MEM_PSC_FLOW MemPGetLRIBT;
3914     //#define PSC_FLOW_OR_LR_IBT   MemPGetLRIBT
3915     //extern MEM_PSC_FLOW MemPGetLRNPR;
3916     //#define PSC_FLOW_OR_LR_NPR   MemPGetLRNPR
3917     //extern MEM_PSC_FLOW MemPGetLRNLR;
3918     //#define PSC_FLOW_OR_LR_NLR  MemPGetLRNLR
3919     //#endif
3920     #ifndef PSC_FLOW_OR_MAX_FREQ
3921       #define PSC_FLOW_OR_MAX_FREQ   MEM_PSC_FLOW_DEFTRUE
3922     #endif
3923     #ifndef PSC_FLOW_OR_DRAM_TERM
3924       #define PSC_FLOW_OR_DRAM_TERM   MEM_PSC_FLOW_DEFTRUE
3925     #endif
3926     #ifndef PSC_FLOW_OR_ODT_PATTERN
3927       #define PSC_FLOW_OR_ODT_PATTERN   MEM_PSC_FLOW_DEFTRUE
3928     #endif
3929     #ifndef PSC_FLOW_OR_SAO
3930       #define PSC_FLOW_OR_SAO   MEM_PSC_FLOW_DEFTRUE
3931     #endif
3932     #ifndef PSC_FLOW_OR_MR0_WRCL
3933       #define PSC_FLOW_OR_MR0_WRCL   MEM_PSC_FLOW_DEFTRUE
3934     #endif
3935     #ifndef PSC_FLOW_OR_RC2_IBT
3936       #define PSC_FLOW_OR_RC2_IBT   MEM_PSC_FLOW_DEFTRUE
3937     #endif
3938     #ifndef PSC_FLOW_OR_RC10_OPSPD
3939       #define PSC_FLOW_OR_RC10_OPSPD   MEM_PSC_FLOW_DEFTRUE
3940     #endif
3941     #ifndef PSC_FLOW_OR_LR_IBT
3942       #define PSC_FLOW_OR_LR_IBT   MEM_PSC_FLOW_DEFTRUE
3943     #endif
3944     #ifndef PSC_FLOW_OR_LR_NPR
3945       #define PSC_FLOW_OR_LR_NPR   MEM_PSC_FLOW_DEFTRUE
3946     #endif
3947     #ifndef PSC_FLOW_OR_LR_NLR
3948       #define PSC_FLOW_OR_LR_NLR   MEM_PSC_FLOW_DEFTRUE
3949     #endif
3950     MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = {
3951       &memPSCTblBlockOr,
3952       PSC_FLOW_OR_MAX_FREQ,
3953       PSC_FLOW_OR_DRAM_TERM,
3954       PSC_FLOW_OR_ODT_PATTERN,
3955       PSC_FLOW_OR_SAO,
3956       PSC_FLOW_OR_MR0_WRCL,
3957       PSC_FLOW_OR_RC2_IBT,
3958       PSC_FLOW_OR_RC10_OPSPD,
3959       PSC_FLOW_OR_LR_IBT,
3960       PSC_FLOW_OR_LR_NPR,
3961       PSC_FLOW_OR_LR_NLR
3962     };
3963     #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR,
3964   #else
3965     #define MEM_PSC_FLOW_BLOCK_OR
3966   #endif
3967
3968
3969   MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
3970     MEM_PSC_FLOW_BLOCK_OR
3971     MEM_PSC_FLOW_BLOCK_END
3972   };
3973
3974   /*---------------------------------------------------------------------------------------------------
3975   *
3976   *  LRDIMM CONTROL
3977   *
3978   *---------------------------------------------------------------------------------------------------
3979   */
3980   #if (OPTION_LRDIMMS == TRUE)
3981     #if (OPTION_MEMCTLR_OR == TRUE)
3982       extern MEM_TECH_FEAT MemTLrdimmConstructor3;
3983       #define MEM_TECH_FEATURE_LRDIMM_INIT  &MemTLrdimmConstructor3
3984     #else //#if (OPTION_MEMCTLR_OR == FALSE)
3985       #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
3986     #endif
3987   #else //#if (OPTION_LRDIMMS == FALSE)
3988     #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
3989   #endif
3990   MEM_TECH_LRDIMM memLrdimmSupported = {
3991     MEM_TECH_LRDIMM_STRUCT_VERSION,
3992     MEM_TECH_FEATURE_LRDIMM_INIT
3993   };
3994 #else
3995   /*---------------------------------------------------------------------------------------------------
3996    * MAIN FLOW CONTROL
3997    *
3998    *
3999    *---------------------------------------------------------------------------------------------------
4000    */
4001   MEM_FLOW_CFG* memFlowControlInstalled[] = {
4002     NULL
4003   };
4004   /*---------------------------------------------------------------------------------------------------
4005    * NB TRAINING FLOW CONTROL
4006    *
4007    *
4008    *---------------------------------------------------------------------------------------------------
4009    */
4010   OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
4011     NULL
4012   };
4013   /*---------------------------------------------------------------------------------------------------
4014    * DEFAULT TECHNOLOGY BLOCK
4015    *
4016    *
4017    *---------------------------------------------------------------------------------------------------
4018    */
4019   MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
4020     NULL
4021   };
4022
4023   /*---------------------------------------------------------------------------------------------------
4024    * DEFAULT TECHNOLOGY MAP
4025    *
4026    *
4027    *---------------------------------------------------------------------------------------------------
4028    */
4029   UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
4030
4031   /*---------------------------------------------------------------------------------------------------
4032    * DEFAULT MAIN FEATURE BLOCK
4033    *---------------------------------------------------------------------------------------------------
4034    */
4035   MEM_FEAT_BLOCK_MAIN MemFeatMain = {
4036     NULL
4037   };
4038
4039   /*---------------------------------------------------------------------------------------------------
4040    * DEFAULT NORTHBRIDGE SUPPORT LIST
4041    *
4042    *
4043    *---------------------------------------------------------------------------------------------------
4044    */
4045   #if (OPTION_MEMCTLR_DR == TRUE)
4046     #undef MEM_NB_SUPPORT_DR
4047     #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
4048   #endif
4049   #if (OPTION_MEMCTLR_RB == TRUE)
4050     #undef MEM_NB_SUPPORT_RB
4051     #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
4052   #endif
4053   #if (OPTION_MEMCTLR_DA == TRUE)
4054     #undef MEM_NB_SUPPORT_DA
4055     #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
4056   #endif
4057   #if (OPTION_MEMCTLR_PH == TRUE)
4058     #undef MEM_NB_SUPPORT_PH
4059     #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
4060   #endif
4061   #if (OPTION_MEMCTLR_HY == TRUE)
4062     #undef MEM_NB_SUPPORT_HY
4063     #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
4064   #endif
4065   #if (OPTION_MEMCTLR_C32 == TRUE)
4066     #undef MEM_NB_SUPPORT_C32
4067     #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
4068   #endif
4069   #if (OPTION_MEMCTLR_LN == TRUE)
4070     #undef MEM_NB_SUPPORT_LN
4071     #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
4072   #endif
4073   #if (OPTION_MEMCTLR_ON == TRUE)
4074     #undef MEM_NB_SUPPORT_ON
4075     #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
4076   #endif
4077   #if (OPTION_MEMCTLR_OR == TRUE)
4078     #undef MEM_NB_SUPPORT_OR
4079     #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
4080   #endif
4081   /*---------------------------------------------------------------------------------------------------
4082    * DEFAULT Technology Training
4083    *
4084    *
4085    *---------------------------------------------------------------------------------------------------
4086    */
4087   #if OPTION_DDR2
4088     MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
4089       NULL
4090     };
4091     MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
4092       NULL
4093     };
4094   #endif
4095   #if OPTION_DDR3
4096     MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
4097       NULL
4098     };
4099     MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
4100       NULL
4101     };
4102   #endif
4103     /*---------------------------------------------------------------------------------------------------
4104      * DEFAULT Platform Specific list
4105      *
4106      *
4107      *---------------------------------------------------------------------------------------------------
4108      */
4109   #if (OPTION_MEMCTLR_DR == TRUE)
4110     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = {
4111       NULL
4112     };
4113   #endif
4114   #if (OPTION_MEMCTLR_RB == TRUE)
4115     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
4116       NULL
4117     };
4118   #endif
4119   #if (OPTION_MEMCTLR_DA == TRUE)
4120     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
4121       NULL
4122     };
4123   #endif
4124   #if (OPTION_MEMCTLR_Ni == TRUE)
4125     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
4126       NULL
4127     };
4128   #endif
4129   #if (OPTION_MEMCTLR_PH == TRUE)
4130     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
4131       NULL
4132     };
4133   #endif
4134   #if (OPTION_MEMCTLR_LN == TRUE)
4135     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = {
4136       NULL
4137     };
4138   #endif
4139   #if (OPTION_MEMCTLR_HY == TRUE)
4140     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
4141       NULL
4142     };
4143   #endif
4144   #if (OPTION_MEMCTLR_OR == TRUE)
4145     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = {
4146       NULL
4147     };
4148   #endif
4149   #if (OPTION_MEMCTLR_C32 == TRUE)
4150     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
4151       NULL
4152     };
4153   #endif
4154   #if (OPTION_MEMCTLR_ON == TRUE)
4155     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
4156       NULL
4157     };
4158   #endif
4159   /*----------------------------------------------------------------------
4160    * DEFAULT PSCFG DEFINITIONS
4161    *
4162    *----------------------------------------------------------------------
4163    */
4164   MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
4165     NULL
4166   };
4167
4168   /*----------------------------------------------------------------------
4169    * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
4170    *
4171    *----------------------------------------------------------------------
4172    */
4173   MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
4174     NULL
4175   };
4176
4177   MEM_TECH_LRDIMM memLrdimmSupported = {
4178     MEM_TECH_LRDIMM_STRUCT_VERSION,
4179     NULL
4180   };
4181 #endif
4182
4183 /*---------------------------------------------------------------------------------------------------
4184  * NORTHBRIDGE SUPPORT LIST
4185  *
4186  *
4187  *---------------------------------------------------------------------------------------------------
4188  */
4189 MEM_NB_SUPPORT memNBInstalled[] = {
4190   MEM_NB_SUPPORT_RB
4191   MEM_NB_SUPPORT_DA
4192   MEM_NB_SUPPORT_Ni
4193   MEM_NB_SUPPORT_PH
4194   MEM_NB_SUPPORT_HY
4195   MEM_NB_SUPPORT_LN
4196   MEM_NB_SUPPORT_OR
4197   MEM_NB_SUPPORT_C32
4198   MEM_NB_SUPPORT_ON
4199   MEM_NB_SUPPORT_END
4200 };
4201
4202 #endif  // _OPTION_MEMORY_INSTALL_H_