7 * Platform specific settings for RB DDR3 U-DIMM system
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ps)
12 * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
16 *****************************************************************************
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
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22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
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43 * ***************************************************************************
47 /* This file contains routine that add platform specific support L1 */
51 #include "AdvancedApi.h"
55 #include "cpuFamRegisters.h"
60 #include "OptionMemory.h"
61 #include "PlatformMemoryConfiguration.h"
62 #include "GeneralServices.h"
67 #define FILECODE PROC_MEM_PS_RB_MPURB3_FILECODE
68 /*----------------------------------------------------------------------------
69 * DEFINITIONS AND MACROS
71 *----------------------------------------------------------------------------
74 /*----------------------------------------------------------------------------
75 * TYPEDEFS AND STRUCTURES
77 *----------------------------------------------------------------------------
80 /*----------------------------------------------------------------------------
81 * PROTOTYPES OF LOCAL FUNCTIONS
83 *----------------------------------------------------------------------------
88 IN OUT MEM_NB_BLOCK *NBPtr
93 MemPGetPORFreqLimitURb3 (
94 IN OUT MEM_NB_BLOCK *NBPtr
98 *-----------------------------------------------------------------------------
101 *-----------------------------------------------------------------------------
103 STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
104 {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
105 {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
106 {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
107 {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
109 /* -----------------------------------------------------------------------------*/
112 * This function is the constructor for the platform specific settings for U-DDR3 RB DDR3
114 * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
115 * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
116 * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
118 * @return AGESA_SUCCESS
123 MemPConstructPsURb3 (
124 IN OUT MEM_DATA_STRUCT *MemPtr,
125 IN OUT CH_DEF_STRUCT *ChannelPtr,
126 IN OUT MEM_PS_BLOCK *PsPtr
129 ASSERT (MemPtr != 0);
130 ASSERT (ChannelPtr != 0);
132 if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
133 return AGESA_UNSUPPORTED;
135 if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
136 return AGESA_UNSUPPORTED;
138 if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
139 return AGESA_UNSUPPORTED;
142 PsPtr->MemPDoPs = MemPDoPsURb3;
143 PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitURb3;
144 return AGESA_SUCCESS;
147 /* -----------------------------------------------------------------------------*/
150 * This is function sets the platform specific settings for U-DDR3 RB DDR3
152 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
154 * @return TRUE - Find settings for corresponding platform and dimm population.
155 * @return FALSE - Fail to find settings for corresponding platform and dimm population.
162 IN OUT MEM_NB_BLOCK *NBPtr
165 if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
172 /* -----------------------------------------------------------------------------*/
175 * This is function gets the POR speed limit for U-DDR3 RB
177 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
183 MemPGetPORFreqLimitURb3 (
184 IN OUT MEM_NB_BLOCK *NBPtr
189 if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
191 // Highest POR supported speed for Unbuffered dimm is 1333
193 SpeedLimit = DDR1333_FREQUENCY;
196 // Max LV DDR3 Speed is 1066 for this silicon
198 SpeedLimit = DDR1066_FREQUENCY;
201 if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
202 NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
203 } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
204 // Unbuffered DDR3 at 333MHz is not supported
205 NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
206 PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
207 SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
208 // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
209 NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;