src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * Install of family 15h support
   6  *
   7  * This file generates the defaults tables for family 15h processors.
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      AGESA
  11  * @e sub-project:  Core
  12  * @e \$Revision: 37150 $   @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
  13  */
  14 /*
  15  *****************************************************************************
  16  *
  17  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  18  * All rights reserved.
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions are met:
  22  *     * Redistributions of source code must retain the above copyright
  23  *       notice, this list of conditions and the following disclaimer.
  24  *     * Redistributions in binary form must reproduce the above copyright
  25  *       notice, this list of conditions and the following disclaimer in the
  26  *       documentation and/or other materials provided with the distribution.
  27  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  28  *       its contributors may be used to endorse or promote products derived
  29  *       from this software without specific prior written permission.
  30  *
  31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  32  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  33  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  34  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  35  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  37  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  38  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  40  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  * ***************************************************************************
  43  *
  44  */
  45
  46 #ifndef _OPTION_FAMILY_15H_INSTALL_H_
  47 #define _OPTION_FAMILY_15H_INSTALL_H_
  48
  49 /*
  50  * Pull in family specific services based on entry point
  51  */
  52
  53 /*
  54  * Common Family 15h routines
  55  */
  56 extern F_GET_EARLY_INIT_TABLE GetF15EarlyInitOnCoreTable;
  57 extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
  58
  59 /*
  60  * Install family 15h model 0 support
  61  */
  62 #ifdef OPTION_FAMILY15H_OR
  63   #if OPTION_FAMILY15H_OR == TRUE
  64     extern F_CPU_GET_IDD_MAX F15GetProcIddMax;
  65     extern F_CPU_GET_NB_PSTATE_INFO F15GetNbPstateInfo;
  66     extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
  67     extern F_CPU_DISABLE_PSTATE F15DisablePstate;
  68     extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
  69     extern F_CPU_GET_TSC_RATE F15GetTscRate;
  70     extern F_CPU_GET_NB_FREQ F15GetCurrentNbFrequency;
  71     extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
  72     extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F15CommonGetNumberOfCoresForBrandstring;
  73     extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15GetApMailboxFromHardware;
  74     extern F_CPU_SET_AP_CORE_NUMBER F15SetApCoreNumber;
  75     extern F_CPU_GET_AP_CORE_NUMBER F15GetApCoreNumber;
  76     extern F_CPU_TRANSFER_AP_CORE_NUMBER F15TransferApCoreNumber;
  77     extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
  78     extern F_CPU_SAVE_FEATURES F15SaveFeatures;
  79     extern F_CPU_WRITE_FEATURES F15WriteFeatures;
  80     extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
  81     extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
  82     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
  83     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15SysPmTable;
  84     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
  85     extern F_CPU_SET_CFOH_REG SetF15CacheFlushOnHaltRegister;
  86     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
  87     extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F15GetPlatformTypeSpecificInfo;
  88     extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
  89     extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
  90     extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
  91     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
  92     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
  93     extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
  94     extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
  95     extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
  96     extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
  97     extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
  98     extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
  99     extern CONST REGISTER_TABLE ROMDATA F15HtPhyRegisterTable;
 100     extern CONST REGISTER_TABLE ROMDATA F15MultiLinkPciRegisterTable;
 101     extern CONST REGISTER_TABLE ROMDATA F15SingleLinkPciRegisterTable;
 102     extern CONST REGISTER_TABLE ROMDATA F15WorkaroundsTable;
 103     extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
 104
 105     /**
 106      * Core Pair and core pair primary determination table.
 107      *
 108      * The two fields from the core pair hardware register can be used to determine whether
 109      * even number cores are primary or all cores are primary.  It can be extended if it is
 110      * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
 111      * but they are currently not supported by the processor.
 112      */
 113     CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
 114     {
 115       {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
 116       {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
 117       {7, 7, EvenCoresMapping},                                     ///< 3 Compute Units all with 2 Cores
 118       {0xF, 0xF, EvenCoresMapping},                                 ///< 4 Compute Units all with 2 Cores
 119       {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
 120       {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
 121       {7, 0, AllCoresMapping},                                      ///< 3 Compute Units all with 1 Core
 122       {0xF, 0, AllCoresMapping},                                    ///< 4 Compute Units all with 1 Core
 123       {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
 124     };
 125
 126
 127     #if USES_REGISTER_TABLES == TRUE
 128       CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
 129       {
 130         #if BASE_FAMILY_PCI == TRUE
 131           &F15PciRegisterTable,
 132         #endif
 133         #if MODEL_SPECIFIC_PCI == TRUE
 134           &F15MultiLinkPciRegisterTable,
 135         #endif
 136         #if MODEL_SPECIFIC_PCI == TRUE
 137           &F15OrPciRegisterTable,
 138         #endif
 139         #if BASE_FAMILY_MSR == TRUE
 140           &F15MsrRegisterTable,
 141         #endif
 142         #if MODEL_SPECIFIC_MSR == TRUE
 143           &F15OrMsrRegisterTable,
 144         #endif
 145         #if MODEL_SPECIFIC_MSR == TRUE
 146           &F15OrSharedMsrRegisterTable,
 147         #endif
 148         #if MODEL_SPECIFIC_HT_PCI == TRUE
 149           &F15HtPhyRegisterTable,
 150         #endif
 151         #if MODEL_SPECIFIC_HT_PCI == TRUE
 152           &F15OrHtPhyRegisterTable,
 153         #endif
 154         #if BASE_FAMILY_WORKAROUNDS == TRUE
 155           &F15WorkaroundsTable,
 156         #endif
 157         // the end.
 158         NULL
 159       };
 160     #endif
 161
 162     #if USES_REGISTER_TABLES == TRUE
 163       CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
 164       {
 165         {MsrRegister, SetRegisterForMsrEntry},
 166         {PciRegister, SetRegisterForPciEntry},
 167         {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
 168         {HtPhyRegister, SetRegisterForHtPhyEntry},
 169         {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
 170         {DeemphasisRegister, SetRegisterForDeemphasisEntry},
 171         {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
 172         {ProfileFixup, SetRegisterForPerformanceProfileEntry},
 173         {HtHostPciRegister, SetRegisterForHtHostEntry},
 174         {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
 175         {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
 176         {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
 177         {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
 178         {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
 179         {TokenPciRegister, SetRegisterForTokenPciEntry},
 180         {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
 181         {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
 182         // End
 183         {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
 184       };
 185     #endif
 186
 187     CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
 188     {
 189       0,
 190       #if DISABLE_PSTATE == TRUE
 191         F15DisablePstate,
 192       #else
 193         (PF_CPU_DISABLE_PSTATE) CommonAssert,
 194       #endif
 195       #if TRANSITION_PSTATE == TRUE
 196         F15TransitionPstate,
 197       #else
 198         (PF_CPU_TRANSITION_PSTATE) CommonAssert,
 199       #endif
 200       #if PROC_IDD_MAX == TRUE
 201         F15GetProcIddMax,
 202       #else
 203         (PF_CPU_GET_IDD_MAX) CommonAssert,
 204       #endif
 205       #if GET_TSC_RATE == TRUE
 206         F15GetTscRate,
 207       #else
 208         (PF_CPU_GET_TSC_RATE) CommonAssert,
 209       #endif
 210       #if GET_NB_FREQ == TRUE
 211         F15GetCurrentNbFrequency,
 212       #else
 213         (PF_CPU_GET_NB_FREQ) CommonAssert,
 214       #endif
 215       #if GET_NB_FREQ == TRUE
 216         F15GetNbPstateInfo,
 217       #else
 218         (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
 219       #endif
 220       #if IS_NBCOF_INIT_NEEDED == TRUE
 221         F15CommonGetNbCofVidUpdate,
 222       #else
 223         (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
 224       #endif
 225       #if AP_INITIAL_LAUNCH == TRUE
 226         F15LaunchApCore,
 227       #else
 228         (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
 229       #endif
 230       #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
 231         F15CommonGetNumberOfCoresForBrandstring,
 232       #else
 233         (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
 234       #endif
 235       #if GET_AP_MAILBOX_FROM_HW == TRUE
 236         F15GetApMailboxFromHardware,
 237       #else
 238         (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
 239       #endif
 240       #if SET_AP_CORE_NUMBER == TRUE
 241         F15SetApCoreNumber,
 242       #else
 243         (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
 244       #endif
 245       #if GET_AP_CORE_NUMBER == TRUE
 246         F15GetApCoreNumber,
 247       #else
 248         (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
 249       #endif
 250       #if TRANSFER_AP_CORE_NUMBER == TRUE
 251         F15TransferApCoreNumber,
 252       #else
 253         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
 254       #endif
 255       #if ID_POSITION_INITIAL_APICID == TRUE
 256         F15CpuAmdCoreIdPositionInInitialApicId,
 257       #else
 258         (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
 259       #endif
 260       #if SAVE_FEATURES == TRUE
 261         // F15SaveFeatures,
 262         (PF_CPU_SAVE_FEATURES) CommonVoid,
 263       #else
 264         (PF_CPU_SAVE_FEATURES) CommonAssert,
 265       #endif
 266       #if WRITE_FEATURES == TRUE
 267         // F15WriteFeatures,
 268         (PF_CPU_WRITE_FEATURES) CommonVoid,
 269       #else
 270         (PF_CPU_WRITE_FEATURES) CommonAssert,
 271       #endif
 272       #if SET_WARM_RESET_FLAG == TRUE
 273         F15SetAgesaWarmResetFlag,
 274       #else
 275         (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
 276       #endif
 277       #if GET_WARM_RESET_FLAG == TRUE
 278         F15GetAgesaWarmResetFlag,
 279       #else
 280         (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
 281       #endif
 282       #if BRAND_STRING1 == TRUE
 283         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
 284       #else
 285         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 286       #endif
 287       #if BRAND_STRING2 == TRUE
 288         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
 289       #else
 290         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 291       #endif
 292       #if GET_PATCHES == TRUE
 293         GetF15OrMicroCodePatchesStruct,
 294       #else
 295         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 296       #endif
 297       #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
 298         GetF15OrMicrocodeEquivalenceTable,
 299       #else
 300         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 301       #endif
 302       #if GET_CACHE_INFO == TRUE
 303         GetF15CacheInfo,
 304       #else
 305         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 306       #endif
 307       #if GET_SYSTEM_PM_TABLE == TRUE
 308         GetF15SysPmTable,
 309       #else
 310         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 311       #endif
 312       #if GET_WHEA_INIT == TRUE
 313         GetF15WheaInitData,
 314       #else
 315         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 316       #endif
 317       #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
 318         F15GetPlatformTypeSpecificInfo,
 319       #else
 320         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
 321       #endif
 322       #if IS_NB_PSTATE_ENABLED == TRUE
 323         F15IsNbPstateEnabled,
 324       #else
 325         (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
 326       #endif
 327       #if (BASE_FAMILY_HT_PCI == TRUE)
 328         F15NextLinkHasHtPhyFeats,
 329       #else
 330         (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
 331       #endif
 332       #if (BASE_FAMILY_HT_PCI == TRUE)
 333         F15SetHtPhyRegister,
 334       #else
 335         (PF_SET_HT_PHY_REGISTER) CommonAssert,
 336       #endif
 337       #if BASE_FAMILY_PCI == TRUE
 338         F15GetNextHtLinkFeatures,
 339       #else
 340         (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
 341       #endif
 342       #if USES_REGISTER_TABLES == TRUE
 343         (REGISTER_TABLE **) F15OrRegisterTables,
 344       #else
 345         NULL,
 346       #endif
 347       #if USES_REGISTER_TABLES == TRUE
 348         (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
 349       #else
 350         NULL,
 351       #endif
 352       #if MODEL_SPECIFIC_HT_PCI == TRUE
 353         (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
 354       #else
 355         NULL,
 356       #endif
 357       (CORE_PAIR_MAP *) &HtFam15CorePairMapping,
 358       InitCacheEnabled,
 359       #if AGESA_ENTRY_INIT_EARLY == TRUE
 360         GetF15EarlyInitOnCoreTable
 361       #else
 362         (PF_GET_EARLY_INIT_TABLE) CommonVoid
 363       #endif
 364     };
 365
 366     #define OR_SOCKETS 8
 367     #define OR_MODULES 2
 368     #define OR_RECOVERY_SOCKETS 1
 369     #define OR_RECOVERY_MODULES 1
 370     extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
 371     #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
 372     #ifndef ADVCFG_PLATFORM_SOCKETS
 373       #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
 374     #else
 375       #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
 376         #undef ADVCFG_PLATFORM_SOCKETS
 377         #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
 378       #endif
 379     #endif
 380     #ifndef ADVCFG_PLATFORM_MODULES
 381       #define ADVCFG_PLATFORM_MODULES OR_MODULES
 382     #else
 383       #if ADVCFG_PLATFORM_MODULES < OR_MODULES
 384         #undef ADVCFG_PLATFORM_MODULES
 385         #define ADVCFG_PLATFORM_MODULES OR_MODULES
 386       #endif
 387     #endif
 388
 389     #if GET_PATCHES == TRUE
 390       #define F15_OR_UCODE_09
 391
 392       #if AGESA_ENTRY_INIT_EARLY == TRUE
 393         #if OPTION_EARLY_SAMPLES == TRUE
 394           extern  CONST MICROCODE_PATCHES_4K ROMDATA CpuF15OrMicrocodePatch06000009;
 395           #undef F15_OR_UCODE_09
 396           #define F15_OR_UCODE_09 &CpuF15OrMicrocodePatch06000009,
 397         #endif
 398       #endif
 399
 400       CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15OrMicroCodePatchArray[] =
 401       {
 402         F15_OR_UCODE_09
 403         NULL
 404       };
 405
 406       CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
 407     #endif
 408
 409     #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
 410
 411   #else  //  OPTION_FAMILY15H_OR == TRUE
 412     #define OPT_F15_OR_CPU
 413     #define OPT_F15_OR_ID
 414   #endif  //  OPTION_FAMILY15H_OR == TRUE
 415 #else  //  defined (OPTION_FAMILY15H_OR)
 416   #define OPT_F15_OR_CPU
 417   #define OPT_F15_OR_ID
 418 #endif  //  defined (OPTION_FAMILY15H_OR)
 419
 420 /*
 421  * Install unknown family 15h support
 422  */
 423
 424
 425 #if USES_REGISTER_TABLES == TRUE
 426   CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
 427   {
 428     #if BASE_FAMILY_PCI == TRUE
 429       &F15PciRegisterTable,
 430     #endif
 431     #if BASE_FAMILY_MSR == TRUE
 432       &F15MsrRegisterTable,
 433     #endif
 434     #if BASE_FAMILY_HT_PCI == TRUE
 435       &F15HtPhyRegisterTable,
 436     #endif
 437     #if OPTION_MULTISOCKET == TRUE
 438       #if MODEL_SPECIFIC_PCI == TRUE
 439         &F15MultiLinkPciRegisterTable,
 440       #endif
 441     #endif
 442     #if OPTION_MULTISOCKET == FALSE
 443       #if MODEL_SPECIFIC_PCI == TRUE
 444         &F15SingleLinkPciRegisterTable,
 445       #endif
 446     #endif
 447     #if BASE_FAMILY_WORKAROUNDS == TRUE
 448       &F15WorkaroundsTable,
 449     #endif
 450     // the end.
 451     NULL
 452   };
 453 #endif
 454
 455 #if USES_REGISTER_TABLES == TRUE
 456   CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
 457   {
 458     {MsrRegister, SetRegisterForMsrEntry},
 459     {PciRegister, SetRegisterForPciEntry},
 460     {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
 461     {HtPhyRegister, SetRegisterForHtPhyEntry},
 462     {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
 463     {DeemphasisRegister, SetRegisterForDeemphasisEntry},
 464     {ProfileFixup, SetRegisterForPerformanceProfileEntry},
 465     {HtHostPciRegister, SetRegisterForHtHostEntry},
 466     {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
 467     {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
 468     {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
 469     {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
 470     {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
 471     {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
 472     // End
 473     {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
 474   };
 475 #endif
 476
 477
 478 CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
 479 {
 480   0,
 481   #if DISABLE_PSTATE == TRUE
 482     F15DisablePstate,
 483   #else
 484     (PF_CPU_DISABLE_PSTATE) CommonAssert,
 485   #endif
 486   #if TRANSITION_PSTATE == TRUE
 487     F15TransitionPstate,
 488   #else
 489     (PF_CPU_TRANSITION_PSTATE) CommonAssert,
 490   #endif
 491   #if PROC_IDD_MAX == TRUE
 492     (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
 493   #else
 494     (PF_CPU_GET_IDD_MAX) CommonAssert,
 495   #endif
 496   #if GET_TSC_RATE == TRUE
 497     F15GetTscRate,
 498   #else
 499     (PF_CPU_GET_TSC_RATE) CommonAssert,
 500   #endif
 501   #if GET_NB_FREQ == TRUE
 502     F15GetCurrentNbFrequency,
 503   #else
 504     (PF_CPU_GET_NB_FREQ) CommonAssert,
 505   #endif
 506   #if GET_NB_FREQ == TRUE
 507     F15GetNbPstateInfo,
 508   #else
 509     (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
 510   #endif
 511   #if IS_NBCOF_INIT_NEEDED == TRUE
 512     (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
 513   #else
 514     (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
 515   #endif
 516   #if AP_INITIAL_LAUNCH == TRUE
 517     F15LaunchApCore,
 518   #else
 519     (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
 520   #endif
 521   #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
 522     (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonVoid,
 523   #else
 524     (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
 525   #endif
 526   #if GET_AP_MAILBOX_FROM_HW == TRUE
 527     F15GetApMailboxFromHardware,
 528   #else
 529     (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
 530   #endif
 531   #if SET_AP_CORE_NUMBER == TRUE
 532     F15SetApCoreNumber,
 533   #else
 534     (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
 535   #endif
 536   #if GET_AP_CORE_NUMBER == TRUE
 537     F15GetApCoreNumber,
 538   #else
 539     (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
 540   #endif
 541   #if TRANSFER_AP_CORE_NUMBER == TRUE
 542     F15TransferApCoreNumber,
 543   #else
 544     (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
 545   #endif
 546   #if ID_POSITION_INITIAL_APICID == TRUE
 547     F15CpuAmdCoreIdPositionInInitialApicId,
 548   #else
 549     (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
 550   #endif
 551   #if SAVE_FEATURES == TRUE
 552     // F15SaveFeatures,
 553     (PF_CPU_SAVE_FEATURES) CommonVoid,
 554   #else
 555     (PF_CPU_SAVE_FEATURES) CommonAssert,
 556   #endif
 557   #if WRITE_FEATURES == TRUE
 558     // F15WriteFeatures,
 559     (PF_CPU_WRITE_FEATURES) CommonVoid,
 560   #else
 561     (PF_CPU_WRITE_FEATURES) CommonAssert,
 562   #endif
 563   #if SET_WARM_RESET_FLAG == TRUE
 564     F15SetAgesaWarmResetFlag,
 565   #else
 566     (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
 567   #endif
 568   #if GET_WARM_RESET_FLAG == TRUE
 569     F15GetAgesaWarmResetFlag,
 570   #else
 571     (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
 572   #endif
 573   #if BRAND_STRING1 == TRUE
 574     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
 575   #else
 576     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 577   #endif
 578   #if BRAND_STRING2 == TRUE
 579     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
 580   #else
 581     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 582   #endif
 583   #if GET_PATCHES == TRUE
 584     GetEmptyArray,
 585   #else
 586     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 587   #endif
 588   #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
 589     GetEmptyArray,
 590   #else
 591     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 592   #endif
 593   #if GET_CACHE_INFO == TRUE
 594     GetF15CacheInfo,
 595   #else
 596     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 597   #endif
 598   #if GET_SYSTEM_PM_TABLE == TRUE
 599     GetF15SysPmTable,
 600   #else
 601     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 602   #endif
 603   #if GET_WHEA_INIT == TRUE
 604     GetF15WheaInitData,
 605   #else
 606     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 607   #endif
 608   #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
 609     F15GetPlatformTypeSpecificInfo,
 610   #else
 611     (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
 612   #endif
 613   #if IS_NB_PSTATE_ENABLED == TRUE
 614     F15IsNbPstateEnabled,
 615   #else
 616     (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
 617   #endif
 618   #if (BASE_FAMILY_HT_PCI == TRUE)
 619     F15NextLinkHasHtPhyFeats,
 620   #else
 621     (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
 622   #endif
 623   #if (BASE_FAMILY_HT_PCI == TRUE)
 624     F15SetHtPhyRegister,
 625   #else
 626     (PF_SET_HT_PHY_REGISTER) CommonVoid,
 627   #endif
 628   #if BASE_FAMILY_PCI == TRUE
 629     F15GetNextHtLinkFeatures,
 630   #else
 631     (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
 632   #endif
 633   #if USES_REGISTER_TABLES == TRUE
 634     (REGISTER_TABLE **) F15UnknownRegisterTables,
 635   #else
 636     NULL,
 637   #endif
 638   #if USES_REGISTER_TABLES == TRUE
 639     (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
 640   #else
 641     NULL,
 642   #endif
 643   NULL,
 644   NULL,
 645   InitCacheEnabled,
 646   #if AGESA_ENTRY_INIT_EARLY == TRUE
 647     GetF15EarlyInitOnCoreTable
 648   #else
 649     (PF_GET_EARLY_INIT_TABLE) CommonVoid
 650   #endif
 651 };
 652
 653 // Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
 654 #if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
 655   #undef  FAMILY_MMIO_BASE_MASK
 656   #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
 657 #endif
 658
 659
 660 #undef OPT_F15_ID_TABLE
 661 #define OPT_F15_ID_TABLE {0x15, {AMD_FAMILY_15, AMD_F15_UNKNOWN}, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
 662 #define OPT_F15_UNKNOWN_CPU {AMD_FAMILY_15, &cpuF15UnknownServices},
 663
 664 #undef OPT_F15_TABLE
 665 #define OPT_F15_TABLE   OPT_F15_OR_CPU  OPT_F15_UNKNOWN_CPU
 666
 667
 668 #if OPTION_G34_SOCKET_SUPPORT == TRUE
 669   #define F15_G34_BRANDSTRING1 NULL,
 670   #define F15_G34_BRANDSTRING2 NULL,
 671 #else
 672   #define F15_G34_BRANDSTRING1
 673   #define F15_G34_BRANDSTRING2
 674 #endif
 675 #if OPTION_C32_SOCKET_SUPPORT == TRUE
 676   #define F15_C32_BRANDSTRING1 NULL,
 677   #define F15_C32_BRANDSTRING2 NULL,
 678 #else
 679   #define F15_C32_BRANDSTRING1
 680   #define F15_C32_BRANDSTRING2
 681 #endif
 682 #if OPTION_AM3_SOCKET_SUPPORT == TRUE
 683   #define F15_AM3_BRANDSTRING1 NULL,
 684   #define F15_AM3_BRANDSTRING2 NULL,
 685 #else
 686   #define F15_AM3_BRANDSTRING1
 687   #define F15_AM3_BRANDSTRING2
 688 #endif
 689
 690 #if BRAND_STRING1 == TRUE
 691   CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
 692   {
 693     F15_G34_BRANDSTRING1
 694     F15_C32_BRANDSTRING1
 695     F15_AM3_BRANDSTRING1
 696   };
 697
 698   CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
 699 #endif
 700
 701 #if BRAND_STRING2 == TRUE
 702   CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
 703   {
 704     F15_G34_BRANDSTRING2
 705     F15_C32_BRANDSTRING2
 706     F15_AM3_BRANDSTRING2
 707   };
 708
 709   CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
 710 #endif
 711
 712 CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
 713 {
 714   OPT_F15_OR_ID
 715 };
 716
 717 #endif  // _OPTION_FAMILY_15H_INSTALL_H_