src/superio/winbond/w83627uhg/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 Dynon Avionics
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 $
  19  */
  20
  21 #include <arch/io.h>
  22 #include <device/device.h>
  23 #include <device/pnp.h>
  24 #include <console/console.h>
  25 #include <string.h>
  26 #include <stdint.h>
  27 #include <stdlib.h>
  28 #include <bitops.h>
  29 #include <uart8250.h>
  30 #include <pc80/keyboard.h>
  31 #include "chip.h"
  32 #include "w83627uhg.h"
  33
  34 static void w83627uhg_enter_ext_func_mode(device_t dev)
  35 {
  36         outb(0x87, dev->path.pnp.port);
  37         outb(0x87, dev->path.pnp.port);
  38 }
  39
  40 static void w83627uhg_exit_ext_func_mode(device_t dev)
  41 {
  42         outb(0xaa, dev->path.pnp.port);
  43 }
  44
  45 /*
  46  * Set the UART clock source.
  47  *
  48  * Possible UART clock source speeds are:
  49  *
  50  *   0 = 1.8462 MHz (default)
  51  *   1 = 2 MHz
  52  *   2 = 24 MHz
  53  *   3 = 14.769 MHz
  54  *
  55  * The faster clocks allow for BAUD rates up to 2mbits.
  56  *
  57  * Warning: The kernel will need to be adjusted since it assumes
  58  * a 1.8462 MHz clock.
  59  */
  60 static void set_uart_clock_source(device_t dev, u8 uart_clock)
  61 {
  62         u8 value;
  63
  64         w83627uhg_enter_ext_func_mode(dev);
  65         pnp_set_logical_device(dev);
  66         value = pnp_read_config(dev, 0xf0);
  67         value &= ~0x03;
  68         value |= (uart_clock & 0x03);
  69         pnp_write_config(dev, 0xf0, value);
  70         w83627uhg_exit_ext_func_mode(dev);
  71 }
  72
  73 static void w83627uhg_init(device_t dev)
  74 {
  75         struct superio_winbond_w83627uhg_config *conf = dev->chip_info;
  76         struct resource *res0, *res1;
  77
  78         if (!dev->enabled)
  79                 return;
  80
  81         switch(dev->path.pnp.device) {
  82         case W83627UHG_SP1:
  83                 res0 = find_resource(dev, PNP_IDX_IO0);
  84                 /* set_uart_clock_source(dev, 0); */
  85                 init_uart8250(res0->base, &conf->com1);
  86                 break;
  87         case W83627UHG_SP2:
  88                 res0 = find_resource(dev, PNP_IDX_IO0);
  89                 /* set_uart_clock_source(dev, 0); */
  90                 init_uart8250(res0->base, &conf->com2);
  91                 break;
  92         case W83627UHG_SP3:
  93                 res0 = find_resource(dev, PNP_IDX_IO0);
  94                 /* set_uart_clock_source(dev, 0); */
  95                 init_uart8250(res0->base, &conf->com3);
  96                 break;
  97         case W83627UHG_SP4:
  98                 res0 = find_resource(dev, PNP_IDX_IO0);
  99                 /* set_uart_clock_source(dev, 0); */
 100                 init_uart8250(res0->base, &conf->com4);
 101                 break;
 102         case W83627UHG_SP5:
 103                 res0 = find_resource(dev, PNP_IDX_IO0);
 104                 /* set_uart_clock_source(dev, 0); */
 105                 init_uart8250(res0->base, &conf->com5);
 106                 break;
 107         case W83627UHG_SP6:
 108                 res0 = find_resource(dev, PNP_IDX_IO0);
 109                 /* set_uart_clock_source(dev, 0); */
 110                 init_uart8250(res0->base, &conf->com6);
 111                 break;
 112         case W83627UHG_KBC:
 113                 res0 = find_resource(dev, PNP_IDX_IO0);
 114                 res1 = find_resource(dev, PNP_IDX_IO1);
 115                 pc_keyboard_init(&conf->keyboard);
 116                 break;
 117         }
 118 }
 119
 120 static void w83627uhg_set_resources(device_t dev)
 121 {
 122         w83627uhg_enter_ext_func_mode(dev);
 123         pnp_set_resources(dev);
 124         w83627uhg_exit_ext_func_mode(dev);
 125 }
 126
 127 static void w83627uhg_enable_resources(device_t dev)
 128 {
 129         w83627uhg_enter_ext_func_mode(dev);
 130         pnp_enable_resources(dev);
 131         w83627uhg_exit_ext_func_mode(dev);
 132 }
 133
 134 static void w83627uhg_enable(device_t dev)
 135 {
 136         w83627uhg_enter_ext_func_mode(dev);
 137         pnp_enable(dev);
 138         w83627uhg_exit_ext_func_mode(dev);
 139 }
 140
 141 static struct device_operations ops = {
 142         .read_resources   = pnp_read_resources,
 143         .set_resources    = w83627uhg_set_resources,
 144         .enable_resources = w83627uhg_enable_resources,
 145         .enable           = w83627uhg_enable,
 146         .init             = w83627uhg_init,
 147 };
 148
 149 static struct pnp_info pnp_dev_info[] = {
 150         { &ops, W83627UHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 151         { &ops, W83627UHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 152         { &ops, W83627UHG_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 153         { &ops, W83627UHG_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 154         { &ops, W83627UHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
 155         { &ops, W83627UHG_SP3,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 156         { &ops, W83627UHG_GPIO3_4, },
 157         { &ops, W83627UHG_WDTO_PLED_GPIO5_6, },
 158         { &ops, W83627UHG_GPIO1_2,},
 159         { &ops, W83627UHG_ACPI, PNP_IRQ0,  },
 160         { &ops, W83627UHG_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
 161         { &ops, W83627UHG_PECI_SST,},
 162         { &ops, W83627UHG_SP4,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 163         { &ops, W83627UHG_SP5,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 164         { &ops, W83627UHG_SP6,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 165 };
 166
 167 static void enable_dev(device_t dev)
 168 {
 169         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 170 }
 171
 172 struct chip_operations superio_winbond_w83627uhg_ops = {
 173         CHIP_NAME("Winbond W83627UHG Super I/O")
 174         .enable_dev = enable_dev,
 175 };