2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 Dynon Avionics
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 $
22 #include <device/device.h>
23 #include <device/pnp.h>
24 #include <console/console.h>
30 #include <pc80/keyboard.h>
32 #include "w83627uhg.h"
34 static void w83627uhg_enter_ext_func_mode(device_t dev)
36 outb(0x87, dev->path.pnp.port);
37 outb(0x87, dev->path.pnp.port);
40 static void w83627uhg_exit_ext_func_mode(device_t dev)
42 outb(0xaa, dev->path.pnp.port);
46 * Set the UART clock source.
48 * Possible UART clock source speeds are:
50 * 0 = 1.8462 MHz (default)
55 * The faster clocks allow for BAUD rates up to 2mbits.
57 * Warning: The kernel will need to be adjusted since it assumes
60 static void set_uart_clock_source(device_t dev, u8 uart_clock)
64 w83627uhg_enter_ext_func_mode(dev);
65 pnp_set_logical_device(dev);
66 value = pnp_read_config(dev, 0xf0);
68 value |= (uart_clock & 0x03);
69 pnp_write_config(dev, 0xf0, value);
70 w83627uhg_exit_ext_func_mode(dev);
73 static void w83627uhg_init(device_t dev)
75 struct superio_winbond_w83627uhg_config *conf;
76 struct resource *res0, *res1;
81 conf = dev->chip_info;
82 switch(dev->path.pnp.device) {
84 res0 = find_resource(dev, PNP_IDX_IO0);
85 /* set_uart_clock_source(dev, 0); */
86 init_uart8250(res0->base, &conf->com1);
89 res0 = find_resource(dev, PNP_IDX_IO0);
90 /* set_uart_clock_source(dev, 0); */
91 init_uart8250(res0->base, &conf->com2);
94 res0 = find_resource(dev, PNP_IDX_IO0);
95 /* set_uart_clock_source(dev, 0); */
96 init_uart8250(res0->base, &conf->com3);
99 res0 = find_resource(dev, PNP_IDX_IO0);
100 /* set_uart_clock_source(dev, 0); */
101 init_uart8250(res0->base, &conf->com4);
104 res0 = find_resource(dev, PNP_IDX_IO0);
105 /* set_uart_clock_source(dev, 0); */
106 init_uart8250(res0->base, &conf->com5);
109 res0 = find_resource(dev, PNP_IDX_IO0);
110 /* set_uart_clock_source(dev, 0); */
111 init_uart8250(res0->base, &conf->com6);
114 res0 = find_resource(dev, PNP_IDX_IO0);
115 res1 = find_resource(dev, PNP_IDX_IO1);
116 pc_keyboard_init(&conf->keyboard);
121 static void w83627uhg_set_resources(device_t dev)
123 w83627uhg_enter_ext_func_mode(dev);
124 pnp_set_resources(dev);
125 w83627uhg_exit_ext_func_mode(dev);
128 static void w83627uhg_enable_resources(device_t dev)
130 w83627uhg_enter_ext_func_mode(dev);
131 pnp_enable_resources(dev);
132 w83627uhg_exit_ext_func_mode(dev);
135 static void w83627uhg_enable(device_t dev)
137 w83627uhg_enter_ext_func_mode(dev);
139 w83627uhg_exit_ext_func_mode(dev);
142 static struct device_operations ops = {
143 .read_resources = pnp_read_resources,
144 .set_resources = w83627uhg_set_resources,
145 .enable_resources = w83627uhg_enable_resources,
146 .enable = w83627uhg_enable,
147 .init = w83627uhg_init,
150 static struct pnp_info pnp_dev_info[] = {
151 { &ops, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
152 { &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
153 { &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
154 { &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
155 { &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
156 { &ops, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
157 { &ops, W83627UHG_GPIO3_4, },
158 { &ops, W83627UHG_WDTO_PLED_GPIO5_6, },
159 { &ops, W83627UHG_GPIO1_2,},
160 { &ops, W83627UHG_ACPI, PNP_IRQ0, },
161 { &ops, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
162 { &ops, W83627UHG_PECI_SST,},
163 { &ops, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
164 { &ops, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
165 { &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
168 static void enable_dev(device_t dev)
170 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
173 struct chip_operations superio_winbond_w83627uhg_ops = {
174 CHIP_NAME("Winbond W83627UHG Super I/O")
175 .enable_dev = enable_dev,