2 * This file is part of the coreboot project.
4 * Copyright (C) 2000 AG Electronics Ltd.
5 * Copyright (C) 2003-2004 Linux Networx
6 * Copyright (C) 2004 Tyan
7 * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <device/device.h>
26 #include <device/pnp.h>
27 #include <console/console.h>
31 #include <pc80/keyboard.h>
32 #include <pc80/mc146818rtc.h>
37 static void pnp_enter_ext_func_mode(device_t dev)
39 outb(0x87, dev->path.pnp.port);
40 outb(0x87, dev->path.pnp.port);
43 static void pnp_exit_ext_func_mode(device_t dev)
45 outb(0xaa, dev->path.pnp.port);
48 static void pnp_write_index(u16 port, u8 reg, u8 value)
51 outb(value, port + 1);
54 static u8 pnp_read_index(u16 port, u8 reg)
61 static void w83627hf_16_bit_addr_qual(device_t dev)
65 /* Enable 16 bit address qualification. */
66 pnp_enter_ext_func_mode(dev);
67 reg8 = pnp_read_config(dev, 0x24);
69 pnp_write_config(dev, 0x24, reg8);
70 pnp_exit_ext_func_mode(dev);
74 static void enable_hwm_smbus(device_t dev)
78 /* Configure pins 91/92 as SDA/SCL (I2C bus). */
79 reg8 = pnp_read_config(dev, 0x2b);
81 pnp_write_config(dev, 0x2b, reg8);
84 static void init_acpi(device_t dev)
86 u8 value = 0x20; /* FIXME: The 0x20 value here is never used? */
89 get_option(&power_on, "power_on_after_fail");
91 pnp_enter_ext_func_mode(dev);
92 pnp_set_logical_device(dev);
93 value = pnp_read_config(dev, 0xE4);
97 pnp_write_config(dev, 0xE4, value);
98 pnp_exit_ext_func_mode(dev);
101 static void init_hwm(u16 base)
106 u8 hwm_reg_values[] = {
108 0x40, 0xff, 0x81, /* Start HWM. */
109 0x48, 0xaa, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */
110 0x4a, 0x21, 0x21, /* Set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1. */
115 0x4d, 0xff, 0x80, /* Turn off beep */
118 for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
119 reg = hwm_reg_values[i];
120 value = pnp_read_index(base, reg);
121 value &= 0xff & hwm_reg_values[i + 1];
122 value |= 0xff & hwm_reg_values[i + 2];
123 printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, "
124 "value = 0x%02x\n", base, reg, value);
125 pnp_write_index(base, reg, value);
129 static void w83627hf_init(device_t dev)
131 struct superio_winbond_w83627hf_config *conf = dev->chip_info;
132 struct resource *res0;
137 switch(dev->path.pnp.device) {
139 res0 = find_resource(dev, PNP_IDX_IO0);
140 init_uart8250(res0->base, &conf->com1);
143 res0 = find_resource(dev, PNP_IDX_IO0);
144 init_uart8250(res0->base, &conf->com2);
147 pc_keyboard_init(&conf->keyboard);
150 res0 = find_resource(dev, PNP_IDX_IO0);
151 #define HWM_INDEX_PORT 5
152 init_hwm(res0->base + HWM_INDEX_PORT);
160 static void w83627hf_pnp_set_resources(device_t dev)
162 pnp_enter_ext_func_mode(dev);
163 pnp_set_resources(dev);
164 pnp_exit_ext_func_mode(dev);
167 static void w83627hf_pnp_enable_resources(device_t dev)
169 pnp_enter_ext_func_mode(dev);
170 pnp_enable_resources(dev);
171 switch(dev->path.pnp.device) {
173 printk(BIOS_DEBUG, "W83627HF HWM SMBus enabled\n");
174 enable_hwm_smbus(dev);
177 pnp_exit_ext_func_mode(dev);
180 static void w83627hf_pnp_enable(device_t dev)
185 pnp_enter_ext_func_mode(dev);
186 pnp_set_logical_device(dev);
187 pnp_set_enable(dev, 0);
188 pnp_exit_ext_func_mode(dev);
191 static struct device_operations ops = {
192 .read_resources = pnp_read_resources,
193 .set_resources = w83627hf_pnp_set_resources,
194 .enable_resources = w83627hf_pnp_enable_resources,
195 .enable = w83627hf_pnp_enable,
196 .init = w83627hf_init,
199 static struct pnp_info pnp_dev_info[] = {
200 { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
201 { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
202 { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
203 { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
204 { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
205 { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
206 { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
207 { &ops, W83627HF_GPIO2, },
208 { &ops, W83627HF_GPIO3, },
209 { &ops, W83627HF_ACPI, },
210 { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
213 static void enable_dev(struct device *dev)
215 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
218 struct chip_operations superio_winbond_w83627hf_ops = {
219 CHIP_NAME("Winbond W83627HF Super I/O")
220 .enable_dev = enable_dev,