src/superio/winbond/w83627hf/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2000 AG Electronics Ltd.
   5  * Copyright (C) 2003-2004 Linux Networx
   6  * Copyright (C) 2004 Tyan
   7  * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 #include <arch/io.h>
  25 #include <device/device.h>
  26 #include <device/pnp.h>
  27 #include <console/console.h>
  28 #include <string.h>
  29 #include <bitops.h>
  30 #include <uart8250.h>
  31 #include <pc80/keyboard.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <stdlib.h>
  34 #include "chip.h"
  35 #include "w83627hf.h"
  36
  37 static void pnp_enter_ext_func_mode(device_t dev)
  38 {
  39         outb(0x87, dev->path.pnp.port);
  40         outb(0x87, dev->path.pnp.port);
  41 }
  42
  43 static void pnp_exit_ext_func_mode(device_t dev)
  44 {
  45         outb(0xaa, dev->path.pnp.port);
  46 }
  47
  48 static void pnp_write_index(u16 port, u8 reg, u8 value)
  49 {
  50         outb(reg, port);
  51         outb(value, port + 1);
  52 }
  53
  54 static u8 pnp_read_index(u16 port, u8 reg)
  55 {
  56         outb(reg, port);
  57         return inb(port + 1);
  58 }
  59
  60 #if CONFIG_EXPERT
  61 static void w83627hf_16_bit_addr_qual(device_t dev)
  62 {
  63         u8 reg8;
  64
  65         /* Enable 16 bit address qualification. */
  66         pnp_enter_ext_func_mode(dev);
  67         reg8 = pnp_read_config(dev, 0x24);
  68         reg8 |= (1 << 7);
  69         pnp_write_config(dev, 0x24, reg8);
  70         pnp_exit_ext_func_mode(dev);
  71 }
  72 #endif
  73
  74 static void enable_hwm_smbus(device_t dev)
  75 {
  76         u8 reg8;
  77
  78         /* Configure pins 91/92 as SDA/SCL (I2C bus). */
  79         reg8 = pnp_read_config(dev, 0x2b);
  80         reg8 &= 0x3f;
  81         pnp_write_config(dev, 0x2b, reg8);
  82 }
  83
  84 static void init_acpi(device_t dev)
  85 {
  86         u8 value = 0x20; /* FIXME: The 0x20 value here is never used? */
  87         int power_on = 1;
  88
  89         get_option(&power_on, "power_on_after_fail");
  90
  91         pnp_enter_ext_func_mode(dev);
  92         pnp_set_logical_device(dev);
  93         value = pnp_read_config(dev, 0xE4);
  94         value &= ~(3 << 5);
  95         if (power_on)
  96                 value |= (1 << 5);
  97         pnp_write_config(dev, 0xE4, value);
  98         pnp_exit_ext_func_mode(dev);
  99 }
 100
 101 static void init_hwm(u16 base)
 102 {
 103         u8 reg, value;
 104         int i;
 105
 106         u8 hwm_reg_values[] = {
 107         /*      reg   mask  data */
 108                 0x40, 0xff, 0x81, /* Start HWM. */
 109                 0x48, 0xaa, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */
 110                 0x4a, 0x21, 0x21, /* Set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1. */
 111                 0x4e, 0x80, 0x00,
 112                 0x43, 0x00, 0xff,
 113                 0x44, 0x00, 0x3f,
 114                 0x4c, 0xbf, 0x18,
 115                 0x4d, 0xff, 0x80, /* Turn off beep */
 116         };
 117
 118         for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
 119                 reg = hwm_reg_values[i];
 120                 value = pnp_read_index(base, reg);
 121                 value &= 0xff & hwm_reg_values[i + 1];
 122                 value |= 0xff & hwm_reg_values[i + 2];
 123                 printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, "
 124                        "value = 0x%02x\n", base, reg, value);
 125                 pnp_write_index(base, reg, value);
 126         }
 127 }
 128
 129 static void w83627hf_init(device_t dev)
 130 {
 131         struct superio_winbond_w83627hf_config *conf = dev->chip_info;
 132         struct resource *res0, *res1;
 133
 134         if (!dev->enabled)
 135                 return;
 136
 137         switch(dev->path.pnp.device) {
 138         case W83627HF_SP1:
 139                 res0 = find_resource(dev, PNP_IDX_IO0);
 140                 init_uart8250(res0->base, &conf->com1);
 141                 break;
 142         case W83627HF_SP2:
 143                 res0 = find_resource(dev, PNP_IDX_IO0);
 144                 init_uart8250(res0->base, &conf->com2);
 145                 break;
 146         case W83627HF_KBC:
 147                 res0 = find_resource(dev, PNP_IDX_IO0);
 148                 res1 = find_resource(dev, PNP_IDX_IO1);
 149                 pc_keyboard_init(&conf->keyboard);
 150                 break;
 151         case W83627HF_HWM:
 152                 res0 = find_resource(dev, PNP_IDX_IO0);
 153 #define HWM_INDEX_PORT 5
 154                 init_hwm(res0->base + HWM_INDEX_PORT);
 155                 break;
 156         case W83627HF_ACPI:
 157                 init_acpi(dev);
 158                 break;
 159         }
 160 }
 161
 162 static void w83627hf_pnp_set_resources(device_t dev)
 163 {
 164         pnp_enter_ext_func_mode(dev);
 165         pnp_set_resources(dev);
 166         pnp_exit_ext_func_mode(dev);
 167 }
 168
 169 static void w83627hf_pnp_enable_resources(device_t dev)
 170 {
 171         pnp_enter_ext_func_mode(dev);
 172         pnp_enable_resources(dev);
 173         switch(dev->path.pnp.device) {
 174         case W83627HF_HWM:
 175                 printk(BIOS_DEBUG, "W83627HF HWM SMBus enabled\n");
 176                 enable_hwm_smbus(dev);
 177                 break;
 178         }
 179         pnp_exit_ext_func_mode(dev);
 180 }
 181
 182 static void w83627hf_pnp_enable(device_t dev)
 183 {
 184         if (dev->enabled)
 185                 return;
 186
 187         pnp_enter_ext_func_mode(dev);
 188         pnp_set_logical_device(dev);
 189         pnp_set_enable(dev, 0);
 190         pnp_exit_ext_func_mode(dev);
 191 }
 192
 193 static struct device_operations ops = {
 194         .read_resources   = pnp_read_resources,
 195         .set_resources    = w83627hf_pnp_set_resources,
 196         .enable_resources = w83627hf_pnp_enable_resources,
 197         .enable           = w83627hf_pnp_enable,
 198         .init             = w83627hf_init,
 199 };
 200
 201 static struct pnp_info pnp_dev_info[] = {
 202         { &ops, W83627HF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 203         { &ops, W83627HF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 204         { &ops, W83627HF_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 205         { &ops, W83627HF_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 206         { &ops, W83627HF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
 207         { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 208         { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
 209         { &ops, W83627HF_GPIO2, },
 210         { &ops, W83627HF_GPIO3, },
 211         { &ops, W83627HF_ACPI, },
 212         { &ops, W83627HF_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
 213 };
 214
 215 static void enable_dev(struct device *dev)
 216 {
 217         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 218 }
 219
 220 struct chip_operations superio_winbond_w83627hf_ops = {
 221         CHIP_NAME("Winbond W83627HF Super I/O")
 222         .enable_dev = enable_dev,
 223 };