src/superio/winbond/w83627ehg/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2000 AG Electronics Ltd.
   5  * Copyright (C) 2003-2004 Linux Networx
   6  * Copyright (C) 2004 Tyan
   7  * Copyright (C) 2007 AMD
   8  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 #include <arch/io.h>
  25 #include <device/device.h>
  26 #include <device/pnp.h>
  27 #include <console/console.h>
  28 #include <string.h>
  29 #include <bitops.h>
  30 #include <uart8250.h>
  31 #include <pc80/keyboard.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <stdlib.h>
  34 #include "chip.h"
  35 #include "w83627ehg.h"
  36
  37 static void pnp_enter_ext_func_mode(device_t dev)
  38 {
  39         outb(0x87, dev->path.pnp.port);
  40         outb(0x87, dev->path.pnp.port);
  41 }
  42
  43 static void pnp_exit_ext_func_mode(device_t dev)
  44 {
  45         outb(0xaa, dev->path.pnp.port);
  46 }
  47
  48 static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
  49 {
  50         outb(reg, port_base);
  51         outb(value, port_base + 1);
  52 }
  53
  54 static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
  55 {
  56         outb(reg, port_base);
  57         return inb(port_base + 1);
  58 }
  59
  60 static void enable_hwm_smbus(device_t dev) {
  61         /* Set the pin 91,92 as I2C bus. */
  62         uint8_t reg, value;
  63         reg = 0x2a;
  64         value = pnp_read_config(dev, reg);
  65         value |= (1 << 1);
  66         pnp_write_config(dev, reg, value);
  67 }
  68
  69 static void init_acpi(device_t dev)
  70 {
  71         uint8_t value = 0x20;
  72         uint32_t power_on = 1;
  73
  74         get_option("power_on_after_fail", &power_on);
  75         pnp_enter_ext_func_mode(dev);
  76         pnp_write_index(dev->path.pnp.port, 7, 0x0a);
  77         value = pnp_read_config(dev, 0xe4);
  78         value &= ~(3 << 5);
  79         if (power_on) {
  80                 value |= (1 << 5);
  81         }
  82         pnp_write_config(dev, 0xe4, value);
  83         pnp_exit_ext_func_mode(dev);
  84 }
  85
  86 static void init_hwm(unsigned long base)
  87 {
  88         int i;
  89         uint8_t reg, value;
  90
  91         /* reg mask data */
  92         unsigned hwm_reg_values[] = {
  93                 0x40, 0xff, 0x81, /* Start HWM. */
  94                 0x48, 0x7f, 0x2a, /* Set SMBus base to 0x54 >> 1. */
  95         };
  96
  97         for(i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
  98                 reg = hwm_reg_values[i];
  99                 value = pnp_read_index(base, reg);
 100                 value &= 0xff & (~(hwm_reg_values[i + 1]));
 101                 value |= 0xff & hwm_reg_values[i + 2];
 102                 // printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
 103                 pnp_write_index(base, reg, value);
 104         }
 105 }
 106
 107 static void w83627ehg_init(device_t dev)
 108 {
 109         struct superio_winbond_w83627ehg_config *conf;
 110         struct resource *res0, *res1;
 111         if (!dev->enabled) {
 112                 return;
 113         }
 114         conf = dev->chip_info;
 115         switch(dev->path.pnp.device) {
 116         case W83627EHG_SP1:
 117                 res0 = find_resource(dev, PNP_IDX_IO0);
 118                 init_uart8250(res0->base, &conf->com1);
 119                 break;
 120         case W83627EHG_SP2:
 121                 res0 = find_resource(dev, PNP_IDX_IO0);
 122                 init_uart8250(res0->base, &conf->com2);
 123                 break;
 124         case W83627EHG_KBC:
 125                 res0 = find_resource(dev, PNP_IDX_IO0);
 126                 res1 = find_resource(dev, PNP_IDX_IO1);
 127                 init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
 128                 break;
 129         case W83627EHG_HWM:
 130                 res0 = find_resource(dev, PNP_IDX_IO0);
 131 #define HWM_INDEX_PORT 5
 132                 init_hwm(res0->base + HWM_INDEX_PORT);
 133                 break;
 134         case W83627EHG_ACPI:
 135                 init_acpi(dev);
 136                 break;
 137         }
 138 }
 139
 140 void w83627ehg_pnp_set_resources(device_t dev)
 141 {
 142         pnp_enter_ext_func_mode(dev);
 143         pnp_set_resources(dev);
 144         pnp_exit_ext_func_mode(dev);
 145 }
 146
 147 void w83627ehg_pnp_enable_resources(device_t dev)
 148 {
 149         pnp_enter_ext_func_mode(dev);
 150         pnp_enable_resources(dev);
 151
 152         switch (dev->path.pnp.device) {
 153         case W83627EHG_HWM:
 154                 printk_debug("w83627ehg hwm smbus enabled\n");
 155                 enable_hwm_smbus(dev);
 156                 break;
 157         }
 158
 159         pnp_exit_ext_func_mode(dev);
 160 }
 161
 162 void w83627ehg_pnp_enable(device_t dev)
 163 {
 164         if (!dev->enabled) {
 165                 pnp_enter_ext_func_mode(dev);
 166                 pnp_set_logical_device(dev);
 167                 pnp_set_enable(dev, 0);
 168                 pnp_exit_ext_func_mode(dev);
 169         }
 170 }
 171
 172 static struct device_operations ops = {
 173         .read_resources   = pnp_read_resources,
 174         .set_resources    = w83627ehg_pnp_set_resources,
 175         .enable_resources = w83627ehg_pnp_enable_resources,
 176         .enable           = w83627ehg_pnp_enable,
 177         .init             = w83627ehg_init,
 178 };
 179
 180 static struct pnp_info pnp_dev_info[] = {
 181         { &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 182         { &ops, W83627EHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 183         { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 184         { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 185         // No 4 { 0,},
 186         { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
 187         { &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 188         { &ops, W83627EHG_WDTO_PLED, },
 189         { &ops, W83627EHG_ACPI, },
 190         { &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
 191         { &ops, W83627EHG_GAME, PNP_IO0, { 0x7ff, 0 }, },
 192         { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 } , {0x7fe, 0x4}, },
 193         { &ops, W83627EHG_GPIO1, },
 194         { &ops, W83627EHG_GPIO2, },
 195         { &ops, W83627EHG_GPIO3, },
 196         { &ops, W83627EHG_GPIO4, },
 197         { &ops, W83627EHG_GPIO5, },
 198         { &ops, W83627EHG_GPIO6, },
 199 };
 200
 201 static void enable_dev(struct device *dev)
 202 {
 203         pnp_enable_devices(dev, &ops,
 204                 ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 205 }
 206
 207 struct chip_operations superio_winbond_w83627ehg_ops = {
 208         CHIP_NAME("Winbond W83627EHG Super I/O")
 209         .enable_dev = enable_dev,
 210 };
 211