2 * This file is part of the coreboot project.
4 * Copyright (C) 2000 AG Electronics Ltd.
5 * Copyright (C) 2003-2004 Linux Networx
6 * Copyright (C) 2004 Tyan
7 * Copyright (C) 2007 AMD
8 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <device/device.h>
26 #include <device/pnp.h>
27 #include <console/console.h>
31 #include <pc80/keyboard.h>
32 #include <pc80/mc146818rtc.h>
35 #include "w83627ehg.h"
37 static void pnp_enter_ext_func_mode(device_t dev)
39 outb(0x87, dev->path.pnp.port);
40 outb(0x87, dev->path.pnp.port);
43 static void pnp_exit_ext_func_mode(device_t dev)
45 outb(0xaa, dev->path.pnp.port);
48 static void pnp_write_index(u16 port, u8 reg, u8 value)
51 outb(value, port + 1);
54 static u8 pnp_read_index(u16 port, u8 reg)
60 static void enable_hwm_smbus(device_t dev)
64 /* Configure pins 91/92 as SDA/SCL (I2C bus). */
65 reg8 = pnp_read_config(dev, 0x2a);
67 pnp_write_config(dev, 0x2a, reg8);
70 static void init_acpi(device_t dev)
72 u8 value = 0x20; /* TODO: 0x20 value here never used? */
75 get_option(&power_on, "power_on_after_fail");
76 pnp_enter_ext_func_mode(dev);
77 pnp_set_logical_device(dev);
78 value = pnp_read_config(dev, 0xe4);
82 pnp_write_config(dev, 0xe4, value);
83 pnp_exit_ext_func_mode(dev);
86 static void init_hwm(u16 base)
92 u8 hwm_reg_values[] = {
93 0x40, 0xff, 0x81, /* Start HWM. */
94 0x48, 0x7f, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */
97 for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
98 reg = hwm_reg_values[i];
99 value = pnp_read_index(base, reg);
100 value &= 0xff & (~(hwm_reg_values[i + 1]));
101 value |= 0xff & hwm_reg_values[i + 2];
102 printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, "
103 "value = 0x%02x\n", base, reg, value);
104 pnp_write_index(base, reg, value);
108 static void w83627ehg_init(device_t dev)
110 struct superio_winbond_w83627ehg_config *conf = dev->chip_info;
111 struct resource *res0;
116 switch(dev->path.pnp.device) {
118 res0 = find_resource(dev, PNP_IDX_IO0);
119 init_uart8250(res0->base, &conf->com1);
122 res0 = find_resource(dev, PNP_IDX_IO0);
123 init_uart8250(res0->base, &conf->com2);
126 pc_keyboard_init(&conf->keyboard);
129 res0 = find_resource(dev, PNP_IDX_IO0);
130 #define HWM_INDEX_PORT 5
131 init_hwm(res0->base + HWM_INDEX_PORT);
139 static void w83627ehg_pnp_set_resources(device_t dev)
141 pnp_enter_ext_func_mode(dev);
142 pnp_set_resources(dev);
143 pnp_exit_ext_func_mode(dev);
146 static void w83627ehg_pnp_enable_resources(device_t dev)
148 pnp_enter_ext_func_mode(dev);
149 pnp_enable_resources(dev);
151 switch (dev->path.pnp.device) {
153 printk(BIOS_DEBUG, "W83627EHG HWM SMBus enabled\n");
154 enable_hwm_smbus(dev);
158 pnp_exit_ext_func_mode(dev);
161 static void w83627ehg_pnp_enable(device_t dev)
166 pnp_enter_ext_func_mode(dev);
167 pnp_set_logical_device(dev);
168 pnp_set_enable(dev, 0);
169 pnp_exit_ext_func_mode(dev);
172 static struct device_operations ops = {
173 .read_resources = pnp_read_resources,
174 .set_resources = w83627ehg_pnp_set_resources,
175 .enable_resources = w83627ehg_pnp_enable_resources,
176 .enable = w83627ehg_pnp_enable,
177 .init = w83627ehg_init,
180 static struct pnp_info pnp_dev_info[] = {
181 { &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
182 { &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
183 { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
184 { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
185 { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
186 { &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
187 { &ops, W83627EHG_WDTO_PLED, },
188 { &ops, W83627EHG_ACPI, },
189 { &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
190 { &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
191 { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
192 { &ops, W83627EHG_GPIO1, },
193 { &ops, W83627EHG_GPIO2, },
194 { &ops, W83627EHG_GPIO3, },
195 { &ops, W83627EHG_GPIO4, },
196 { &ops, W83627EHG_GPIO5, },
197 { &ops, W83627EHG_GPIO6, },
200 static void enable_dev(struct device *dev)
202 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
205 struct chip_operations superio_winbond_w83627ehg_ops = {
206 CHIP_NAME("Winbond W83627EHG Super I/O")
207 .enable_dev = enable_dev,