src/superio/winbond/w83627dhg/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <arch/io.h>
  21 #include <device/device.h>
  22 #include <device/pnp.h>
  23 #include <uart8250.h>
  24 #include <pc80/keyboard.h>
  25 #include <stdlib.h>
  26 #include "chip.h"
  27 #include "w83627dhg.h"
  28
  29 static void pnp_enter_ext_func_mode(device_t dev)
  30 {
  31         outb(0x87, dev->path.pnp.port);
  32         outb(0x87, dev->path.pnp.port);
  33 }
  34
  35 static void pnp_exit_ext_func_mode(device_t dev)
  36 {
  37         outb(0xaa, dev->path.pnp.port);
  38 }
  39
  40 static void w83627dhg_init(device_t dev)
  41 {
  42         struct superio_winbond_w83627dhg_config *conf = dev->chip_info;
  43         struct resource *res0;
  44
  45         if (!dev->enabled)
  46                 return;
  47
  48         switch(dev->path.pnp.device) {
  49         case W83627DHG_SP1:
  50                 res0 = find_resource(dev, PNP_IDX_IO0);
  51                 init_uart8250(res0->base, &conf->com1);
  52                 break;
  53         case W83627DHG_SP2:
  54                 res0 = find_resource(dev, PNP_IDX_IO0);
  55                 init_uart8250(res0->base, &conf->com2);
  56                 break;
  57         case W83627DHG_KBC:
  58                 pc_keyboard_init(&conf->keyboard);
  59                 break;
  60         }
  61 }
  62
  63 static void w83627dhg_pnp_set_resources(device_t dev)
  64 {
  65         pnp_enter_ext_func_mode(dev);
  66         pnp_set_resources(dev);
  67         pnp_exit_ext_func_mode(dev);
  68 }
  69
  70 static void w83627dhg_pnp_enable_resources(device_t dev)
  71 {
  72         pnp_enter_ext_func_mode(dev);
  73         pnp_enable_resources(dev);
  74         pnp_exit_ext_func_mode(dev);
  75 }
  76
  77 static void w83627dhg_pnp_enable(device_t dev)
  78 {
  79         if (!dev->enabled)
  80                 return;
  81
  82         pnp_enter_ext_func_mode(dev);
  83         pnp_set_logical_device(dev);
  84         pnp_set_enable(dev, 0);
  85         pnp_exit_ext_func_mode(dev);
  86 }
  87
  88 static struct device_operations ops = {
  89         .read_resources   = pnp_read_resources,
  90         .set_resources    = w83627dhg_pnp_set_resources,
  91         .enable_resources = w83627dhg_pnp_enable_resources,
  92         .enable           = w83627dhg_pnp_enable,
  93         .init             = w83627dhg_init,
  94 };
  95
  96 static struct pnp_info pnp_dev_info[] = {
  97         { &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
  98         { &ops, W83627DHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
  99         { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 100         { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 101         { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
 102         /* the next line makes coreboot hang in pnp_enable_devices() */
 103         /* { &ops, W83627DHG_SPI, PNP_IO1, { 0x7f8, 0 }, }, */
 104         { &ops, W83627DHG_GPIO6, },
 105         { &ops, W83627DHG_WDTO_PLED, },
 106         { &ops, W83627DHG_GPIO2, },
 107         { &ops, W83627DHG_GPIO3, },
 108         { &ops, W83627DHG_GPIO4, },
 109         { &ops, W83627DHG_GPIO5, },
 110         { &ops, W83627DHG_ACPI, PNP_IRQ0, },
 111         { &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
 112         { &ops, W83627DHG_PECI_SST, },
 113 };
 114
 115 static void enable_dev(struct device *dev)
 116 {
 117         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 118 }
 119
 120 struct chip_operations superio_winbond_w83627dhg_ops = {
 121         CHIP_NAME("Winbond W83627DHG Super I/O")
 122         .enable_dev = enable_dev,
 123 };