2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pnp.h>
31 static u8 hwm_io_regs[] = {
32 0x10,0x03, 0x11,0x10, 0x12,0x0d, 0x13,0x7f,
33 0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a,
34 0x18,0x00, 0x19,0x00, 0x1a,0x00, 0x1b,0x00,
35 0x1d,0xff, 0x1e,0x00, 0x1f,0x73, 0x20,0x67,
36 0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2,
37 0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x00,
38 0x2a,0x00, 0x2b,0xff, 0x2c,0x00, 0x2d,0xff,
39 0x2e,0x00, 0x2f,0xff, 0x30,0x00, 0x31,0xff,
40 0x32,0x00, 0x33,0xff, 0x34,0x00, 0x39,0xff,
41 0x3a,0x00, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff,
42 0x3e,0x00, 0x3f,0xb0, 0x43,0xff, 0x44,0xff,
43 0x46,0xff, 0x47,0x50, 0x4a,0x03, 0x4b,0xc0,
44 0x4c,0x00, 0x4d,0x00, 0x4e,0x0f, 0x5d,0x77,
45 0x5c,0x00, 0x5f,0x33, 0x40,0x01,
48 static void pnp_enter_ext_func_mode(device_t dev)
50 outb(0x87, dev->path.pnp.port);
51 outb(0x87, dev->path.pnp.port);
54 static void pnp_exit_ext_func_mode(device_t dev)
56 outb(0xaa, dev->path.pnp.port);
59 static void vt1211_set_iobase(device_t dev, u8 index, u16 iobase)
61 switch (dev->path.pnp.device) {
66 pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff);
69 /* TODO: Error. VT1211_ROM doesn't have an I/O base. */
79 pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
80 pnp_write_config(dev, index + 1, iobase & 0xff);
85 /* Initialize VT1211 hardware monitor registers, which are at 0xECXX. */
86 static void init_hwm(u16 base)
90 for (i = 0; i < sizeof(hwm_io_regs); i += 2)
91 outb(hwm_io_regs[i + 1], base + hwm_io_regs[i]);
94 static void vt1211_init(struct device *dev)
96 struct superio_via_vt1211_config *conf = dev->chip_info;
97 struct resource *res0;
102 switch (dev->path.pnp.device) {
104 res0 = find_resource(dev, PNP_IDX_IO0);
105 init_uart8250(res0->base, &conf->com1);
108 res0 = find_resource(dev, PNP_IDX_IO0);
109 init_uart8250(res0->base, &conf->com2);
112 res0 = find_resource(dev, PNP_IDX_IO0);
113 init_hwm(res0->base);
124 /* TODO: Any init needed for these LDNs? */
127 printk(BIOS_INFO, "VT1211: Cannot init unknown device!\n");
131 static void vt1211_pnp_enable_resources(device_t dev)
133 printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev));
134 pnp_enter_ext_func_mode(dev);
135 pnp_enable_resources(dev);
136 pnp_exit_ext_func_mode(dev);
139 static void vt1211_pnp_set_resources(struct device *dev)
141 struct resource *res;
143 #if CONFIG_CONSOLE_SERIAL8250 == 1
144 /* TODO: Do the same for SP2? */
145 if (dev->path.pnp.device == VT1211_SP1) {
146 for (res = dev->resource_list; res; res = res->next) {
147 res->flags |= IORESOURCE_STORED;
148 report_resource_stored(dev, res, "");
154 pnp_enter_ext_func_mode(dev);
156 pnp_set_logical_device(dev);
158 /* Paranoia says I should disable the device here... */
159 for (res = dev->resource_list; res; res = res->next) {
160 if (!(res->flags & IORESOURCE_ASSIGNED)) {
161 printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx "
162 "not assigned\n", dev_path(dev), res->index,
163 resource_type(res), res->size);
167 /* Now store the resource. */
168 if (res->flags & IORESOURCE_IO) {
169 vt1211_set_iobase(dev, res->index, res->base);
170 } else if (res->flags & IORESOURCE_DRQ) {
171 pnp_set_drq(dev, res->index, res->base);
172 } else if (res->flags & IORESOURCE_IRQ) {
173 pnp_set_irq(dev, res->index, res->base);
175 printk(BIOS_ERR, "ERROR: %s %02lx unknown resource "
176 "type\n", dev_path(dev), res->index);
179 res->flags |= IORESOURCE_STORED;
181 report_resource_stored(dev, res, "");
184 pnp_exit_ext_func_mode(dev);
187 static void vt1211_pnp_enable(device_t dev)
192 pnp_enter_ext_func_mode(dev);
193 pnp_set_logical_device(dev);
194 pnp_set_enable(dev, 0);
195 pnp_exit_ext_func_mode(dev);
198 struct device_operations ops = {
199 .read_resources = pnp_read_resources,
200 .set_resources = vt1211_pnp_set_resources,
201 .enable_resources = vt1211_pnp_enable_resources,
202 .enable = vt1211_pnp_enable,
206 /* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */
207 static struct pnp_info pnp_dev_info[] = {
208 { &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
209 { &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
210 { &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
211 { &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
212 { &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 }, },
213 { &ops, VT1211_GAME, PNP_IO0, { 0xfff8, 0 }, },
214 { &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
215 { &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
216 { &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
217 { &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, { 0xff00, 0 }, },
218 { &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xff00, 0 }, },
219 { &ops, VT1211_ROM, },
222 static void enable_dev(struct device *dev)
224 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
227 struct chip_operations superio_via_vt1211_ops = {
228 CHIP_NAME("VIA VT1211 Super I/O")
229 .enable_dev = enable_dev,