src/superio/smsc/lpc47n227/lpc47n227_early_serial.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Digital Design Corporation
   5  * Copyright (C) 2008-2009 coresystems GmbH
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 /* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */
  22
  23 #include <arch/romcc_io.h>
  24 #include "lpc47n227.h"
  25
  26 //----------------------------------------------------------------------------------
  27 // Function:            pnp_enter_conf_state
  28 // Parameters:          dev - high 8 bits = Super I/O port
  29 // Return Value:        None
  30 // Description:         Enable access to the LPC47N227's configuration registers.
  31 //
  32 static inline void pnp_enter_conf_state(device_t dev)
  33 {
  34         unsigned port = dev >> 8;
  35         outb(0x55, port);
  36 }
  37
  38 //----------------------------------------------------------------------------------
  39 // Function:            pnp_exit_conf_state
  40 // Parameters:          dev - high 8 bits = Super I/O port
  41 // Return Value:        None
  42 // Description:         Disable access to the LPC47N227's configuration registers.
  43 //
  44 static void pnp_exit_conf_state(device_t dev)
  45 {
  46         unsigned port = dev >> 8;
  47         outb(0xaa, port);
  48 }
  49
  50 //----------------------------------------------------------------------------------
  51 // Function:            lpc47n227_pnp_set_iobase
  52 // Parameters:          dev - high 8 bits = Super I/O port,
  53 //                            low 8 bits = logical device number (per lpc47n227.h)
  54 //                      iobase - base I/O port for the logical device
  55 // Return Value:        None
  56 // Description:         Program the base I/O port for the specified logical device.
  57 //
  58 void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase)
  59 {
  60         // LPC47N227 requires base ports to be a multiple of 4
  61         ASSERT(!(iobase & 0x3));
  62
  63         switch (dev & 0xFF) {
  64         case LPC47N227_PP:
  65                 pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
  66                 break;
  67
  68         case LPC47N227_SP1:
  69                 pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
  70                 break;
  71
  72         case LPC47N227_SP2:
  73                 pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
  74                 break;
  75
  76         default:
  77                 break;
  78         }
  79 }
  80
  81 //----------------------------------------------------------------------------------
  82 // Function:            lpc47n227_pnp_set_enable
  83 // Parameters:          dev - high 8 bits = Super I/O port,
  84 //                      low 8 bits = logical device number (per lpc47n227.h)
  85 //                      enable - 0 to disable, anythig else to enable
  86 // Return Value:        None
  87 // Description:         Enable or disable the specified logical device.
  88 //                      Technically, a full disable requires setting the device's base
  89 //                      I/O port below 0x100. We don't do that here, because we don't
  90 //                      have access to a data structure that specifies what the 'real'
  91 //                      base port is (when asked to enable the device). Also the function
  92 //                      is used only to disable the device while its true base port is
  93 //                      programmed (see lpc47n227_enable_serial() below).
  94 //
  95 void lpc47n227_pnp_set_enable(device_t dev, int enable)
  96 {
  97         uint8_t power_register = 0;
  98         uint8_t power_mask = 0;
  99         uint8_t current_power;
 100         uint8_t new_power;
 101
 102         switch (dev & 0xFF) {
 103         case LPC47N227_PP:
 104                 power_register = 0x01;
 105                 power_mask = 0x04;
 106                 break;
 107
 108         case LPC47N227_SP1:
 109                 power_register = 0x02;
 110                 power_mask = 0x08;
 111                 break;
 112
 113         case LPC47N227_SP2:
 114                 power_register = 0x02;
 115                 power_mask = 0x80;
 116                 break;
 117
 118         default:
 119                 return;
 120         }
 121
 122         current_power = pnp_read_config(dev, power_register);
 123         new_power = current_power & ~power_mask;        // disable by default
 124
 125         if (enable)
 126                 new_power |= power_mask;        // Enable
 127
 128         pnp_write_config(dev, power_register, new_power);
 129 }
 130
 131 //----------------------------------------------------------------------------------
 132 // Function:            lpc47n227_enable_serial
 133 // Parameters:          dev - high 8 bits = Super I/O port,
 134 //                            low 8 bits = logical device number (per lpc47n227.h)
 135 //                      iobase - processor I/O port address to assign to this serial device
 136 // Return Value:        bool
 137 // Description:         Configure the base I/O port of the specified serial device
 138 //                      and enable the serial device.
 139 //
 140 static void lpc47n227_enable_serial(device_t dev, unsigned iobase)
 141 {
 142         // NOTE: Cannot use pnp_set_XXX() here because they assume chip
 143         // support for logical devices, which the LPC47N227 doesn't have
 144
 145         pnp_enter_conf_state(dev);
 146         lpc47n227_pnp_set_enable(dev, 0);
 147         lpc47n227_pnp_set_iobase(dev, iobase);
 148         lpc47n227_pnp_set_enable(dev, 1);
 149         pnp_exit_conf_state(dev);
 150 }