2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Digital Design Corporation
5 * Copyright (C) 2008-2009 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */
23 #include <arch/romcc_io.h>
24 #include "lpc47n227.h"
26 static void pnp_enter_conf_state(device_t dev)
32 static void pnp_exit_conf_state(device_t dev)
39 * Program the base I/O port for the specified logical device.
41 * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
42 * @param iobase Base I/O port for the logical device.
44 void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase)
46 /* LPC47N227 requires base ports to be a multiple of 4. */
47 ASSERT(!(iobase & 0x3));
51 pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
54 pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
57 pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
65 * Enable or disable the specified logical device.
67 * Technically, a full disable requires setting the device's base I/O port
68 * below 0x100. We don't do that here, because we don't have access to a data
69 * structure that specifies what the 'real' base port is (when asked to enable
70 * the device). Also the function is used only to disable the device while its
71 * true base port is programmed (see lpc47n227_enable_serial() below).
73 * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
74 * @param enable 0 to disable, anythig else to enable.
76 void lpc47n227_pnp_set_enable(device_t dev, int enable)
78 u8 power_register = 0, power_mask = 0, current_power, new_power;
82 power_register = 0x01;
86 power_register = 0x02;
90 power_register = 0x02;
97 current_power = pnp_read_config(dev, power_register);
98 new_power = current_power & ~power_mask; /* Disable by default. */
100 new_power |= power_mask; /* Enable. */
101 pnp_write_config(dev, power_register, new_power);
105 * Configure the base I/O port of the specified serial device and enable the
108 * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
109 * @param iobase Processor I/O port address to assign to this serial device.
111 static void lpc47n227_enable_serial(device_t dev, u16 iobase)
114 * NOTE: Cannot use pnp_set_XXX() here because they assume chip
115 * support for logical devices, which the LPC47N227 doesn't have.
117 pnp_enter_conf_state(dev);
118 lpc47n227_pnp_set_enable(dev, 0);
119 lpc47n227_pnp_set_iobase(dev, iobase);
120 lpc47n227_pnp_set_enable(dev, 1);
121 pnp_exit_conf_state(dev);