2 * This file is part of the coreboot project.
4 * Copyright (C) 2000 AG Electronics Ltd.
5 * Copyright (C) 2003-2004 Linux Networx
6 * Copyright (C) 2004 Tyan
7 * Copyright (C) 2005 Digital Design Corporation
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 /* RAM-based driver for SMSC LPC47N217 Super I/O chip. */
25 /* Based on coreboot code for SMSC 47B397. */
28 #include <device/device.h>
29 #include <device/pnp.h>
30 #include <console/console.h>
31 #include <device/smbus.h>
38 #include "lpc47n217.h"
40 /* Forward declarations */
41 static void enable_dev(device_t dev);
42 static void lpc47n217_pnp_set_resources(device_t dev);
43 static void lpc47n217_pnp_enable_resources(device_t dev);
44 static void lpc47n217_pnp_enable(device_t dev);
45 static void lpc47n217_init(device_t dev);
47 static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
48 static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
49 static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
50 static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
51 static void lpc47n217_pnp_set_enable(device_t dev, int enable);
53 static void pnp_enter_conf_state(device_t dev);
54 static void pnp_exit_conf_state(device_t dev);
56 struct chip_operations superio_smsc_lpc47n217_ops = {
57 CHIP_NAME("SMSC LPC47N217 Super I/O")
58 .enable_dev = enable_dev,
61 static struct device_operations ops = {
62 .read_resources = pnp_read_resources,
63 .set_resources = lpc47n217_pnp_set_resources,
64 .enable_resources = lpc47n217_pnp_enable_resources,
65 .enable = lpc47n217_pnp_enable,
66 .init = lpc47n217_init,
69 static struct pnp_info pnp_dev_info[] = {
70 { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
71 { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
72 { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
76 * Create device structures and allocate resources to devices specified in the
77 * pnp_dev_info array (above).
79 * @param dev Pointer to structure describing a Super I/O device.
81 static void enable_dev(device_t dev)
83 pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
88 * Configure the specified Super I/O device with the resources (I/O space,
89 * etc.) that have been allocate for it.
91 * @param dev Pointer to structure describing a Super I/O device.
93 static void lpc47n217_pnp_set_resources(device_t dev)
97 pnp_enter_conf_state(dev);
99 /* NOTE: Cannot use pnp_set_resources() here because it assumes chip
100 * support for logical devices, which the LPC47N217 doesn't have
102 for(res = dev->resource_list; res; res = res->next)
103 lpc47n217_pnp_set_resource(dev, res);
105 /* dump_pnp_device(dev); */
107 pnp_exit_conf_state(dev);
110 static void lpc47n217_pnp_enable_resources(device_t dev)
112 pnp_enter_conf_state(dev);
115 * NOTE: Cannot use pnp_enable_resources() here because it assumes chip
116 * support for logical devices, which the LPC47N217 doesn't have.
118 lpc47n217_pnp_set_enable(dev, 1);
120 pnp_exit_conf_state(dev);
123 static void lpc47n217_pnp_enable(device_t dev)
125 pnp_enter_conf_state(dev);
128 * NOTE: Cannot use pnp_set_enable() here because it assumes chip
129 * support for logical devices, which the LPC47N217 doesn't have.
132 lpc47n217_pnp_set_enable(dev, 1);
135 lpc47n217_pnp_set_enable(dev, 0);
138 pnp_exit_conf_state(dev);
142 * Initialize the specified Super I/O device.
144 * Devices other than COM ports are ignored. For COM ports, we configure the
147 * @param dev Pointer to structure describing a Super I/O device.
149 static void lpc47n217_init(device_t dev)
151 struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
152 struct resource *res0;
157 switch(dev->path.pnp.device) {
159 res0 = find_resource(dev, PNP_IDX_IO0);
160 init_uart8250(res0->base, &conf->com1);
164 res0 = find_resource(dev, PNP_IDX_IO0);
165 init_uart8250(res0->base, &conf->com2);
170 static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
172 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
173 printk(BIOS_ERR, "ERROR: %s %02x not allocated\n",
174 dev_path(dev), resource->index);
178 /* Now store the resource */
180 * NOTE: Cannot use pnp_set_XXX() here because they assume chip
181 * support for logical devices, which the LPC47N217 doesn't have.
183 if (resource->flags & IORESOURCE_IO) {
184 lpc47n217_pnp_set_iobase(dev, resource->base);
186 else if (resource->flags & IORESOURCE_DRQ) {
187 lpc47n217_pnp_set_drq(dev, resource->base);
189 else if (resource->flags & IORESOURCE_IRQ) {
190 lpc47n217_pnp_set_irq(dev, resource->base);
193 printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n",
194 dev_path(dev), resource->index);
197 resource->flags |= IORESOURCE_STORED;
199 report_resource_stored(dev, resource, "");
202 static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
204 ASSERT(!(iobase & 0x3));
206 switch(dev->path.pnp.device) {
208 pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
212 pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
216 pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
225 static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
227 if (dev->path.pnp.device == LPC47N217_PP) {
228 const uint8_t PP_DMA_MASK = 0x0F;
229 const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
230 uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
233 ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range?? */
234 new_config = (current_config & ~PP_DMA_MASK) | drq;
235 pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
241 static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
243 uint8_t irq_config_register = 0;
244 uint8_t irq_config_mask = 0;
245 uint8_t current_config;
248 switch(dev->path.pnp.device) {
250 irq_config_register = 0x27;
251 irq_config_mask = 0x0F;
255 irq_config_register = 0x28;
256 irq_config_mask = 0xF0;
261 irq_config_register = 0x28;
262 irq_config_mask = 0x0F;
270 ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range?? */
272 current_config = pnp_read_config(dev, irq_config_register);
273 new_config = (current_config & ~irq_config_mask) | irq;
274 pnp_write_config(dev, irq_config_register, new_config);
277 static void lpc47n217_pnp_set_enable(device_t dev, int enable)
279 uint8_t power_register = 0;
280 uint8_t power_mask = 0;
281 uint8_t current_power;
284 switch(dev->path.pnp.device) {
286 power_register = 0x01;
291 power_register = 0x02;
296 power_register = 0x02;
305 current_power = pnp_read_config(dev, power_register);
306 new_power = current_power & ~power_mask; /* disable by default */
309 struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
310 lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
312 new_power |= power_mask; /* Enable */
315 lpc47n217_pnp_set_iobase(dev, 0);
317 pnp_write_config(dev, power_register, new_power);
320 /** Enable access to the LPC47N217's configuration registers. */
321 static void pnp_enter_conf_state(device_t dev)
323 outb(0x55, dev->path.pnp.port);
326 /** Disable access to the LPC47N217's configuration registers. */
327 static void pnp_exit_conf_state(device_t dev)
329 outb(0xaa, dev->path.pnp.port);
334 * Print the values of all of the LPC47N217's configuration registers.
336 * NOTE: The LPC47N217 must be in config mode when this function is called.
338 * @param dev Pointer to structure describing a Super I/O device.
340 static void dump_pnp_device(device_t dev)
345 for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
346 uint8_t register_value;
348 if ((register_index & 0x0f) == 0) {
349 print_debug_hex8(register_index);
350 print_debug_char(':');
353 /* Skip over 'register' that would cause exit from configuration mode */
354 if (register_index == 0xaa)
355 register_value = 0xaa;
357 register_value = pnp_read_config(dev, register_index);
359 print_debug_char(' ');
360 print_debug_hex8(register_value);
361 if ((register_index & 0x0f) == 0x0f) {