2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Digital Design Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */
23 #include <arch/romcc_io.h>
25 #include "lpc47n217.h"
28 * Function: pnp_enter_conf_state
29 * Parameters: dev - high 8 bits = Super I/O port
31 * Description: Enable access to the LPC47N217's configuration registers.
33 static inline void pnp_enter_conf_state(device_t dev)
35 unsigned port = dev>>8;
40 * Function: pnp_exit_conf_state
41 * Parameters: dev - high 8 bits = Super I/O port
43 * Description: Disable access to the LPC47N217's configuration registers.
45 static void pnp_exit_conf_state(device_t dev)
47 unsigned port = dev>>8;
52 * Function: lpc47n217_pnp_set_iobase
53 * Parameters: dev - high 8 bits = Super I/O port,
54 * low 8 bits = logical device number (per lpc47n217.h)
55 * iobase - base I/O port for the logical device
57 * Description: Program the base I/O port for the specified logical device.
60 void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
62 /* LPC47N217 requires base ports to be a multiple of 4 */
63 ASSERT(!(iobase & 0x3));
67 pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
71 pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
75 pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
84 * Function: lpc47n217_pnp_set_enable
85 * Parameters: dev - high 8 bits = Super I/O port,
86 * low 8 bits = logical device number (per lpc47n217.h)
87 * enable - 0 to disable, anythig else to enable
89 * Description: Enable or disable the specified logical device.
90 * Technically, a full disable requires setting the device's base
91 * I/O port below 0x100. We don't do that here, because we don't
92 * have access to a data structure that specifies what the 'real'
93 * base port is (when asked to enable the device). Also the function
94 * is used only to disable the device while its true base port is
95 * programmed (see lpc47n217_enable_serial() below).
97 void lpc47n217_pnp_set_enable(device_t dev, int enable)
99 uint8_t power_register = 0;
100 uint8_t power_mask = 0;
101 uint8_t current_power;
106 power_register = 0x01;
111 power_register = 0x02;
116 power_register = 0x02;
124 current_power = pnp_read_config(dev, power_register);
125 new_power = current_power & ~power_mask; /* disable by default */
128 new_power |= power_mask; /* Enable */
130 pnp_write_config(dev, power_register, new_power);
134 * Function: lpc47n217_enable_serial
135 * Parameters: dev - high 8 bits = Super I/O port,
136 * low 8 bits = logical device number (per lpc47n217.h)
137 * iobase - processor I/O port address to assign to this serial device
139 * Description: Configure the base I/O port of the specified serial device
140 * and enable the serial device.
142 static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
144 /* NOTE: Cannot use pnp_set_XXX() here because they assume chip
145 * support for logical devices, which the LPC47N217 doesn't have*/
147 pnp_enter_conf_state(dev);
148 lpc47n217_pnp_set_enable(dev, 0);
149 lpc47n217_pnp_set_iobase(dev, iobase);
150 lpc47n217_pnp_set_enable(dev, 1);
151 pnp_exit_conf_state(dev);