2 * This file is part of the coreboot project.
4 * Copyright (C) 2000 AG Electronics Ltd.
5 * Copyright (C) 2003-2004 Linux Networx
6 * Copyright (C) 2004 Tyan
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <device/device.h>
25 #include <device/pnp.h>
26 #include <console/console.h>
27 #include <device/smbus.h>
31 #include <pc80/keyboard.h>
34 #include "lpc47b397.h"
36 static void pnp_enter_conf_state(device_t dev)
38 outb(0x55, dev->path.pnp.port);
41 static void pnp_exit_conf_state(device_t dev)
43 outb(0xaa, dev->path.pnp.port);
46 static void pnp_write_index(u16 port, u8 reg, u8 value)
49 outb(value, port + 1);
52 static u8 pnp_read_index(u16 port, u8 reg)
58 static void enable_hwm_smbus(device_t dev)
60 /* Enable SensorBus register access. */
63 reg8 = pnp_read_config(dev, 0xf0);
65 pnp_write_config(dev, 0xf0, reg8);
68 static void lpc47b397_init(device_t dev)
70 struct superio_smsc_lpc47b397_config *conf = dev->chip_info;
75 switch(dev->path.pnp.device) {
77 pc_keyboard_init(&conf->keyboard);
82 static void lpc47b397_pnp_set_resources(device_t dev)
84 pnp_enter_conf_state(dev);
85 pnp_set_resources(dev);
86 /* dump_pnp_device(dev); */
87 pnp_exit_conf_state(dev);
90 static void lpc47b397_pnp_enable_resources(device_t dev)
92 pnp_enter_conf_state(dev);
93 pnp_enable_resources(dev);
95 switch(dev->path.pnp.device) {
97 printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n");
98 pnp_set_logical_device(dev);
99 enable_hwm_smbus(dev);
102 /* dump_pnp_device(dev); */
103 pnp_exit_conf_state(dev);
106 static void lpc47b397_pnp_enable(device_t dev)
108 pnp_enter_conf_state(dev);
109 pnp_set_logical_device(dev);
110 pnp_set_enable(dev, !!dev->enabled);
111 pnp_exit_conf_state(dev);
114 static struct device_operations ops = {
115 .read_resources = pnp_read_resources,
116 .set_resources = lpc47b397_pnp_set_resources,
117 .enable_resources = lpc47b397_pnp_enable_resources,
118 .enable = lpc47b397_pnp_enable,
119 .init = lpc47b397_init,
124 #define SB_INDEX 0x0b
125 #define SB_DATA0 0x0c
126 #define SB_DATA1 0x0d
127 #define SB_DATA2 0x0e
128 #define SB_DATA3 0x0f
130 static int lsmbus_read_byte(device_t dev, u8 address)
133 struct resource *res;
136 device = dev->path.i2c.device;
138 res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
140 pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */
142 /* We only read it one byte one time. */
143 result = pnp_read_index(res->base + SB_INDEX, address);
148 static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
151 struct resource *res;
153 device = dev->path.i2c.device;
154 res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
156 pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */
158 /* We only write it one byte one time. */
159 pnp_write_index(res->base+SB_INDEX, address, val);
164 static struct smbus_bus_operations lops_smbus_bus = {
165 /* .recv_byte = lsmbus_recv_byte, */
166 /* .send_byte = lsmbus_send_byte, */
167 .read_byte = lsmbus_read_byte,
168 .write_byte = lsmbus_write_byte,
171 static struct device_operations ops_hwm = {
172 .read_resources = pnp_read_resources,
173 .set_resources = lpc47b397_pnp_set_resources,
174 .enable_resources = lpc47b397_pnp_enable_resources,
175 .enable = lpc47b397_pnp_enable,
176 .init = lpc47b397_init,
177 .scan_bus = scan_static_bus,
178 .ops_smbus_bus = &lops_smbus_bus,
181 static struct pnp_info pnp_dev_info[] = {
182 { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
183 { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
184 { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
185 { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
186 { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
187 { &ops_hwm, LPC47B397_HWM, PNP_IO0, {0x07f0, 0}, },
188 { &ops, LPC47B397_RT, PNP_IO0, {0x0780, 0}, },
191 static void enable_dev(struct device *dev)
193 pnp_enable_devices(dev, &pnp_ops,
194 ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
197 struct chip_operations superio_smsc_lpc47b397_ops = {
198 CHIP_NAME("SMSC LPC47B397 Super I/O")
199 .enable_dev = enable_dev,