src/superio/smsc/lpc47b397/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2000 AG Electronics Ltd.
   5  * Copyright (C) 2003-2004 Linux Networx
   6  * Copyright (C) 2004 Tyan
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  21  */
  22
  23 #include <arch/io.h>
  24 #include <device/device.h>
  25 #include <device/pnp.h>
  26 #include <console/console.h>
  27 #include <device/smbus.h>
  28 #include <string.h>
  29 #include <bitops.h>
  30 #include <uart8250.h>
  31 #include <pc80/keyboard.h>
  32 #include <stdlib.h>
  33 #include "chip.h"
  34 #include "lpc47b397.h"
  35
  36 static void pnp_enter_conf_state(device_t dev)
  37 {
  38         outb(0x55, dev->path.pnp.port);
  39 }
  40
  41 static void pnp_exit_conf_state(device_t dev)
  42 {
  43         outb(0xaa, dev->path.pnp.port);
  44 }
  45
  46 static void pnp_write_index(u16 port, u8 reg, u8 value)
  47 {
  48         outb(reg, port);
  49         outb(value, port + 1);
  50 }
  51
  52 static u8 pnp_read_index(u16 port, u8 reg)
  53 {
  54         outb(reg, port);
  55         return inb(port + 1);
  56 }
  57
  58 static void enable_hwm_smbus(device_t dev)
  59 {
  60         /* Enable SensorBus register access. */
  61         u8 reg8;
  62
  63         reg8 = pnp_read_config(dev, 0xf0);
  64         reg8 |= (1 << 1);
  65         pnp_write_config(dev, 0xf0, reg8);
  66 }
  67
  68 static void lpc47b397_init(device_t dev)
  69 {
  70         struct superio_smsc_lpc47b397_config *conf = dev->chip_info;
  71         struct resource *res0;
  72
  73         if (!dev->enabled)
  74                 return;
  75
  76         switch(dev->path.pnp.device) {
  77         case LPC47B397_SP1:
  78                 res0 = find_resource(dev, PNP_IDX_IO0);
  79                 init_uart8250(res0->base, &conf->com1);
  80                 break;
  81         case LPC47B397_SP2:
  82                 res0 = find_resource(dev, PNP_IDX_IO0);
  83                 init_uart8250(res0->base, &conf->com2);
  84                 break;
  85         case LPC47B397_KBC:
  86                 pc_keyboard_init(&conf->keyboard);
  87                 break;
  88         }
  89 }
  90
  91 static void lpc47b397_pnp_set_resources(device_t dev)
  92 {
  93         pnp_enter_conf_state(dev);
  94         pnp_set_resources(dev);
  95         /* dump_pnp_device(dev); */
  96         pnp_exit_conf_state(dev);
  97 }
  98
  99 static void lpc47b397_pnp_enable_resources(device_t dev)
 100 {
 101         pnp_enter_conf_state(dev);
 102         pnp_enable_resources(dev);
 103
 104         switch(dev->path.pnp.device) {
 105         case LPC47B397_HWM:
 106                 printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n");
 107                 pnp_set_logical_device(dev);
 108                 enable_hwm_smbus(dev);
 109                 break;
 110         }
 111         /* dump_pnp_device(dev); */
 112         pnp_exit_conf_state(dev);
 113 }
 114
 115 static void lpc47b397_pnp_enable(device_t dev)
 116 {
 117         pnp_enter_conf_state(dev);
 118         pnp_set_logical_device(dev);
 119         pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
 120         pnp_exit_conf_state(dev);
 121 }
 122
 123 static struct device_operations ops = {
 124         .read_resources   = pnp_read_resources,
 125         .set_resources    = lpc47b397_pnp_set_resources,
 126         .enable_resources = lpc47b397_pnp_enable_resources,
 127         .enable           = lpc47b397_pnp_enable,
 128         .init             = lpc47b397_init,
 129 };
 130
 131 #define HWM_INDEX 0
 132 #define HWM_DATA  1
 133 #define SB_INDEX  0x0b
 134 #define SB_DATA0  0x0c
 135 #define SB_DATA1  0x0d
 136 #define SB_DATA2  0x0e
 137 #define SB_DATA3  0x0f
 138
 139 static int lsmbus_read_byte(device_t dev, u8 address)
 140 {
 141         unsigned int device;
 142         struct resource *res;
 143         int result;
 144
 145         device = dev->path.i2c.device;
 146
 147         res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
 148
 149         pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */
 150
 151         /* We only read it one byte one time. */
 152         result = pnp_read_index(res->base + SB_INDEX, address);
 153
 154         return result;
 155 }
 156
 157 static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
 158 {
 159         unsigned int device;
 160         struct resource *res;
 161
 162         device = dev->path.i2c.device;
 163         res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
 164
 165         pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */
 166
 167         /* We only write it one byte one time. */
 168         pnp_write_index(res->base+SB_INDEX, address, val);
 169
 170         return 0;
 171 }
 172
 173 static struct smbus_bus_operations lops_smbus_bus = {
 174         /* .recv_byte  = lsmbus_recv_byte, */
 175         /* .send_byte  = lsmbus_send_byte, */
 176         .read_byte  = lsmbus_read_byte,
 177         .write_byte = lsmbus_write_byte,
 178 };
 179
 180 static struct device_operations ops_hwm = {
 181         .read_resources   = pnp_read_resources,
 182         .set_resources    = lpc47b397_pnp_set_resources,
 183         .enable_resources = lpc47b397_pnp_enable_resources,
 184         .enable           = lpc47b397_pnp_enable,
 185         .init             = lpc47b397_init,
 186         .scan_bus         = scan_static_bus,
 187         .ops_smbus_bus    = &lops_smbus_bus,
 188 };
 189
 190 static struct pnp_info pnp_dev_info[] = {
 191         { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
 192         { &ops, LPC47B397_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
 193         { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 194         { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 195         { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
 196         { &ops_hwm, LPC47B397_HWM,  PNP_IO0, {0x07f0, 0}, },
 197         { &ops, LPC47B397_RT,  PNP_IO0, {0x0780, 0}, },
 198 };
 199
 200 static void enable_dev(struct device *dev)
 201 {
 202         pnp_enable_devices(dev, &pnp_ops,
 203                 ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 204 }
 205
 206 struct chip_operations superio_smsc_lpc47b397_ops = {
 207         CHIP_NAME("SMSC LPC47B397 Super I/O")
 208         .enable_dev = enable_dev,
 209 };