src/superio/smsc/lpc47b397/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2000 AG Electronics Ltd.
   5  * Copyright (C) 2003-2004 Linux Networx
   6  * Copyright (C) 2004 Tyan
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  21  */
  22
  23 #include <arch/io.h>
  24 #include <device/device.h>
  25 #include <device/pnp.h>
  26 #include <console/console.h>
  27 #include <device/smbus.h>
  28 #include <string.h>
  29 #include <bitops.h>
  30 #include <uart8250.h>
  31 #include <pc80/keyboard.h>
  32 #include <stdlib.h>
  33 #include "chip.h"
  34 #include "lpc47b397.h"
  35
  36 static void pnp_enter_conf_state(device_t dev)
  37 {
  38         outb(0x55, dev->path.pnp.port);
  39 }
  40 static void pnp_exit_conf_state(device_t dev)
  41 {
  42         outb(0xaa, dev->path.pnp.port);
  43 }
  44
  45 static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
  46 {
  47         outb(reg, port_base);
  48         outb(value, port_base + 1);
  49 }
  50
  51 static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
  52 {
  53         outb(reg, port_base);
  54         return inb(port_base + 1);
  55 }
  56
  57 static void enable_hwm_smbus(device_t dev)
  58 {
  59         /* enable SensorBus register access */
  60         uint8_t reg, value;
  61         reg = 0xf0;
  62         value = pnp_read_config(dev, reg);
  63         value |= 0x01;
  64         pnp_write_config(dev, reg, value);
  65 }
  66
  67 static void lpc47b397_init(device_t dev)
  68 {
  69         struct superio_smsc_lpc47b397_config *conf;
  70         struct resource *res0;
  71         if (!dev->enabled) {
  72                 return;
  73         }
  74         conf = dev->chip_info;
  75         switch(dev->path.pnp.device) {
  76         case LPC47B397_SP1:
  77                 res0 = find_resource(dev, PNP_IDX_IO0);
  78                 init_uart8250(res0->base, &conf->com1);
  79                 break;
  80         case LPC47B397_SP2:
  81                 res0 = find_resource(dev, PNP_IDX_IO0);
  82                 init_uart8250(res0->base, &conf->com2);
  83                 break;
  84         case LPC47B397_KBC:
  85                 pc_keyboard_init(&conf->keyboard);
  86                 break;
  87         }
  88 }
  89
  90 static void lpc47b397_pnp_set_resources(device_t dev)
  91 {
  92         pnp_enter_conf_state(dev);
  93         pnp_set_resources(dev);
  94 #if 0
  95         dump_pnp_device(dev);
  96 #endif
  97         pnp_exit_conf_state(dev);
  98 }
  99
 100 static void lpc47b397_pnp_enable_resources(device_t dev)
 101 {
 102         pnp_enter_conf_state(dev);
 103         pnp_enable_resources(dev);
 104
 105         switch(dev->path.pnp.device) {
 106         case LPC47B397_HWM:
 107                 printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\n");
 108                 pnp_set_logical_device(dev);
 109                 enable_hwm_smbus(dev);
 110                 break;
 111         }
 112 #if 0
 113         dump_pnp_device(dev);
 114 #endif
 115         pnp_exit_conf_state(dev);
 116 }
 117
 118 static void lpc47b397_pnp_enable(device_t dev)
 119 {
 120         pnp_enter_conf_state(dev);
 121         pnp_set_logical_device(dev);
 122
 123         if(dev->enabled) {
 124                 pnp_set_enable(dev, 1);
 125         }
 126         else {
 127                 pnp_set_enable(dev, 0);
 128         }
 129         pnp_exit_conf_state(dev);
 130 }
 131
 132 static struct device_operations ops = {
 133         .read_resources   = pnp_read_resources,
 134         .set_resources    = lpc47b397_pnp_set_resources,
 135         .enable_resources = lpc47b397_pnp_enable_resources,
 136         .enable           = lpc47b397_pnp_enable,
 137         .init             = lpc47b397_init,
 138 };
 139
 140 #define HWM_INDEX 0
 141 #define HWM_DATA  1
 142 #define SB_INDEX  0x0b
 143 #define SB_DATA0  0x0c
 144 #define SB_DATA1  0x0d
 145 #define SB_DATA2  0x0e
 146 #define SB_DATA3  0x0f
 147
 148 static int lsmbus_read_byte(device_t dev, uint8_t address)
 149 {
 150         unsigned device;
 151         struct resource *res;
 152         int result;
 153
 154         device = dev->path.i2c.device;
 155
 156         res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
 157
 158         pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */
 159
 160         result = pnp_read_index(res->base+SB_INDEX, address);  /* we only read it one byte one time */
 161
 162         return result;
 163 }
 164
 165 static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
 166 {
 167         unsigned device;
 168         struct resource *res;
 169
 170         device = dev->path.i2c.device;
 171         res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
 172
 173         pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */
 174
 175         pnp_write_index(res->base+SB_INDEX, address, val); /* we only write it one byte one time */
 176
 177         return 0;
 178 }
 179
 180 static struct smbus_bus_operations lops_smbus_bus = {
 181         /* .recv_byte  = lsmbus_recv_byte, */
 182         /* .send_byte  = lsmbus_send_byte, */
 183         .read_byte  = lsmbus_read_byte,
 184         .write_byte = lsmbus_write_byte,
 185 };
 186 static struct device_operations ops_hwm = {
 187         .read_resources   = pnp_read_resources,
 188         .set_resources    = lpc47b397_pnp_set_resources,
 189         .enable_resources = lpc47b397_pnp_enable_resources,
 190         .enable           = lpc47b397_pnp_enable,
 191         .init             = lpc47b397_init,
 192         .scan_bus         = scan_static_bus,
 193         .ops_smbus_bus    = &lops_smbus_bus,
 194 };
 195
 196 static struct pnp_info pnp_dev_info[] = {
 197         { &ops, LPC47B397_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 198         { &ops, LPC47B397_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 199         { &ops, LPC47B397_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 200         { &ops, LPC47B397_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 201         { &ops, LPC47B397_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
 202         { &ops_hwm, LPC47B397_HWM,  PNP_IO0, { 0x7f0, 0 }, },
 203         { &ops, LPC47B397_RT,   PNP_IO0, { 0x780, 0 }, },
 204 };
 205
 206 static void enable_dev(struct device *dev)
 207 {
 208         pnp_enable_devices(dev, &pnp_ops,
 209                 ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 210 }
 211
 212 struct chip_operations superio_smsc_lpc47b397_ops = {
 213         CHIP_NAME("SMSC LPC47B397 Super I/O")
 214         .enable_dev = enable_dev,
 215 };