2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Digital Design Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */
23 #include <arch/romcc_io.h>
24 #include "lpc47b272.h"
26 static void pnp_enter_conf_state(device_t dev)
32 static void pnp_exit_conf_state(device_t dev)
39 * Configure the base I/O port of the specified serial device and enable the
42 * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
43 * @param iobase Processor I/O port address to assign to this serial device.
45 static void lpc47b272_enable_serial(device_t dev, u16 iobase)
47 pnp_enter_conf_state(dev);
48 pnp_set_logical_device(dev);
49 pnp_set_enable(dev, 0);
50 pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
51 pnp_set_enable(dev, 1);
52 pnp_exit_conf_state(dev);