2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/romcc_io.h>
22 #include "fdc37m60x.h"
24 /* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */
25 #define SIO_BASE 0x3f0
26 #define SIO_INDEX SIO_BASE
27 #define SIO_DATA SIO_BASE+1
29 /* Global configuration registers. */
30 #define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */
31 #define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
32 #define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */
33 #define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */
34 #define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */
36 #define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */
38 /* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the
39 LDN the register belongs to, before you can access the register. */
40 static void fdc37m60x_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
42 outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE);
44 outb(index, SIO_BASE);
45 outb(value, SIO_DATA);
48 /* Enable the peripheral devices on the FDC37M60X Super I/O chip. */
49 static void fdc37m60x_enable_serial(device_t dev, unsigned iobase)
51 /* (1) Enter the configuration state. */
52 outb(0x55, FDC37M60X_CONFIGURATION_PORT);
54 /* (2) Modify the data of configuration registers. */
56 /* Power on all devices by setting the respective bit.
57 Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */
58 fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39);
60 /* Disable intelligent power management. */
61 fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00);
63 /* Turn on OSC, turn on BRG clock. */
64 fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04);
66 /* Configure serial port 1. */
67 fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03);
68 fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */
69 fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */
70 fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */
72 /* Enable serial port 1. */
73 fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01);
75 /* (3) Exit the configuration state. */
76 outb(0xaa, FDC37M60X_CONFIGURATION_PORT);