2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/romcc_io.h>
24 /* The base address is 0x2e or 0x4e, depending on config bytes. */
26 #define SIO_INDEX SIO_BASE
27 #define SIO_DATA SIO_BASE+1
29 /* Global configuration registers. */
30 #define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
31 #define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
32 #define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
33 #define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
34 #define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
36 #define IT8718F_CONFIGURATION_PORT 0x2e /* Write-only. */
38 /* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the
39 LDN the register belongs to, before you can access the register. */
40 static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
42 outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
44 outb(index, SIO_BASE);
45 outb(value, SIO_DATA);
48 static void it8718f_enter_conf(void)
50 /* Enter the configuration state (MB PnP mode). */
52 /* Perform MB PnP setup to put the SIO chip at 0x2e. */
53 /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
54 /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
55 outb(0x87, IT8718F_CONFIGURATION_PORT);
56 outb(0x01, IT8718F_CONFIGURATION_PORT);
57 outb(0x55, IT8718F_CONFIGURATION_PORT);
58 outb(0x55, IT8718F_CONFIGURATION_PORT);
61 static void it8718f_exit_conf(void)
63 /* Exit the configuration state (MB PnP mode). */
64 it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
67 void it8718f_24mhz_clkin(void)
71 /* Select 24MHz CLKIN (48MHZ default)*/
72 it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
77 /* GIGABYTE uses a special SuperIO register to protect its Dual BIOS
78 * mechanism. It lives in the GPIO LDN. However, register 0xEF is not
79 * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for
82 void it8718f_disable_reboot(void)
86 it8718f_sio_write(0x07, 0xEF, 0x7E);
91 /* Enable the peripheral devices on the IT8718F Super I/O chip. */
92 void it8718f_enable_serial(device_t dev, unsigned iobase)
94 /* (1) Enter the configuration state (MB PnP mode). */
97 /* (2) Modify the data of configuration registers. */
99 /* Select the chip to configure (if there's more than one).
100 Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
101 If this register is not written, both chips are configured. */
102 /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
104 /* Enable serial port(s). */
105 it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
106 it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
108 /* Clear software suspend mode (clear bit 0). TODO: Needed? */
109 /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
111 /* (3) Exit the configuration state (MB PnP mode). */