2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/romcc_io.h>
24 /* The base address is 0x2e or 0x4e, depending on config bytes. */
26 #define SIO_INDEX SIO_BASE
27 #define SIO_DATA (SIO_BASE + 1)
29 /* Global configuration registers. */
30 #define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
31 #define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
32 #define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
33 #define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
34 #define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
36 static void it8718f_sio_write(u8 ldn, u8 index, u8 value)
38 outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
40 outb(index, SIO_BASE);
41 outb(value, SIO_DATA);
44 static void it8718f_enter_conf(void)
46 u16 port = 0x2e; /* TODO: Don't hardcode! */
51 outb((port == 0x4e) ? 0xaa : 0x55, port);
54 static void it8718f_exit_conf(void)
56 it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
59 /* Select 24MHz CLKIN (48MHz default). */
60 void it8718f_24mhz_clkin(void)
63 it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
68 * GIGABYTE uses a special Super I/O register to protect its Dual BIOS
69 * mechanism. It lives in the GPIO LDN. However, register 0xEF is not
70 * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now.
72 void it8718f_disable_reboot(void)
75 it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E);
79 /* Enable the serial port(s). */
80 void it8718f_enable_serial(device_t dev, u16 iobase)
82 /* (1) Enter the configuration state (MB PnP mode). */
85 /* (2) Modify the data of configuration registers. */
88 * Select the chip to configure (if there's more than one).
89 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
90 * If this register is not written, both chips are configured.
93 /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
95 /* Enable serial port(s). */
96 it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
97 it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
99 /* Clear software suspend mode (clear bit 0). TODO: Needed? */
100 /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
102 /* (3) Exit the configuration state (MB PnP mode). */