2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/romcc_io.h>
24 /* The base address is 0x2e or 0x4e, depending on config bytes. */
26 #define SIO_INDEX SIO_BASE
27 #define SIO_DATA (SIO_BASE + 1)
29 /* Global configuration registers. */
30 #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
31 #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
32 #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
33 #define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
34 #define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
35 #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
36 #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
38 static void it8712f_sio_write(u8 ldn, u8 index, u8 value)
40 outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
42 outb(index, SIO_BASE);
43 outb(value, SIO_DATA);
46 static void it8712f_enter_conf(void)
48 u16 port = 0x2e; /* TODO: Don't hardcode! */
53 outb((port == 0x4e) ? 0xaa : 0x55, port);
56 static void it8712f_exit_conf(void)
58 it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
61 /* Select 24MHz CLKIN (48MHz is the default). */
62 void it8712f_24mhz_clkin(void)
65 it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
70 * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
72 * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
74 * Enable 3VSBSW#. (For System Suspend-to-RAM)
75 * 0: 3VSBSW# will be always inactive.
76 * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
78 void it8712f_enable_3vsbsw(void)
81 it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80);
85 void it8712f_kill_watchdog(void)
88 it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
92 /* Enable the serial port(s). */
93 void it8712f_enable_serial(device_t dev, u16 iobase)
95 /* (1) Enter the configuration state (MB PnP mode). */
98 /* (2) Modify the data of configuration registers. */
101 * Select the chip to configure (if there's more than one).
102 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
103 * If this register is not written, both chips are configured.
106 /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
108 /* Enable serial port(s). */
109 it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
110 it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
112 /* Clear software suspend mode (clear bit 0). TODO: Needed? */
113 /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
115 /* (3) Exit the configuration state (MB PnP mode). */