2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/romcc_io.h>
24 /* The base address is 0x2e or 0x4e, depending on config bytes. */
26 #define SIO_INDEX SIO_BASE
27 #define SIO_DATA SIO_BASE+1
29 /* Global configuration registers. */
30 #define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
31 #define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
32 #define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
34 /* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */
35 #define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */
36 #define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */
38 #define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */
40 /* The content of IT8705F_CONFIG_REG_LDN (index 0x07) must be set to the
41 LDN the register belongs to, before you can access the register. */
42 static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
44 outb(IT8705F_CONFIG_REG_LDN, SIO_BASE);
46 outb(index, SIO_BASE);
47 outb(value, SIO_DATA);
50 /* Enable the peripheral devices on the IT8705F Super I/O chip. */
51 static void it8705f_enable_serial(device_t dev, unsigned iobase)
53 /* (1) Enter the configuration state (MB PnP mode). */
55 /* Perform MB PnP setup to put the SIO chip at 0x2e. */
56 /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
57 /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
58 outb(0x87, IT8705F_CONFIGURATION_PORT);
59 outb(0x01, IT8705F_CONFIGURATION_PORT);
60 outb(0x55, IT8705F_CONFIGURATION_PORT);
61 outb(0x55, IT8705F_CONFIGURATION_PORT);
63 /* (2) Modify the data of configuration registers. */
65 /* Select the chip to configure (if there's more than one).
66 Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
67 If this register is not written, both chips are configured. */
68 /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */
70 /* Enable serial port(s). */
71 it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */
72 it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */
74 /* Select 24MHz CLKIN (set bit 0). */
75 it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01);
77 /* Clear software suspend mode (clear bit 0). TODO: Needed? */
78 /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */
80 /* (3) Exit the configuration state (MB PnP mode). */
81 it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02);