2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/romcc_io.h>
24 /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
25 #define SIO_BASE 0x3f0
26 #define SIO_INDEX SIO_BASE
27 #define SIO_DATA (SIO_BASE + 1)
29 /* Global configuration registers. */
30 #define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
31 #define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
32 #define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
33 #define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */
35 #define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
38 * Special values used for entering MB PnP mode. The first four bytes of
39 * each line determine the address port, the last four are data.
41 static const uint8_t init_values[] = {
42 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
43 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
44 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
45 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
49 * The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the
50 * LDN the register belongs to, before you can access the register.
52 static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
54 outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
56 outb(index, SIO_BASE);
57 outb(value, SIO_DATA);
60 /* Enter the configuration state (MB PnP mode). */
61 static void it8671f_enter_conf(void)
65 /* Perform MB PnP setup to put the SIO chip at 0x3f0. */
66 /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
67 /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
68 /* Base address 0x370: 0x86 0x80 0xaa 0x55. */
69 outb(0x86, IT8671F_CONFIGURATION_PORT);
70 outb(0x80, IT8671F_CONFIGURATION_PORT);
71 outb(0x55, IT8671F_CONFIGURATION_PORT);
72 outb(0x55, IT8671F_CONFIGURATION_PORT);
74 /* Sequentially write the 32 special values. */
75 for (i = 0; i < 32; i++)
76 outb(init_values[i], SIO_BASE);
79 /* Exit the configuration state (MB PnP mode). */
80 static void it8671f_exit_conf(void)
82 it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
85 /* Select 48MHz CLKIN (24MHz is the default). */
86 void it8671f_48mhz_clkin(void)
89 it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6));
93 /* Enable the serial ports on the IT8671F Super I/O chip. */
94 static void it8671f_enable_serial(device_t dev, unsigned iobase)
98 /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
99 PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */
100 it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
102 /* Enable serial port(s). */
103 it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */
104 it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */