6cf2f621ec0985083856f43d81c464301e802a0c
[coreboot.git] / src / superio / fintek / f71805f / superio.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
19  */
20
21 /* Datasheet: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf */
22
23 #include <arch/io.h>
24 #include <device/device.h>
25 #include <device/pnp.h>
26 #include <console/console.h>
27 #include <stdlib.h>
28 #include <uart8250.h>
29 #include "chip.h"
30 #include "f71805f.h"
31
32 static void pnp_enter_conf_state(device_t dev)
33 {
34         outb(0x87, dev->path.pnp.port);
35 }
36
37 static void pnp_exit_conf_state(device_t dev)
38 {
39         outb(0xaa, dev->path.pnp.port);
40 }
41
42 static void f71805f_init(device_t dev)
43 {
44         struct superio_fintek_f71805f_config *conf = dev->chip_info;
45         struct resource *res0;
46
47         if (!dev->enabled)
48                 return;
49
50         switch(dev->path.pnp.device) {
51         /* TODO: Might potentially need code for HWM or FDC etc. */
52         case F71805F_SP1:
53                 res0 = find_resource(dev, PNP_IDX_IO0);
54                 init_uart8250(res0->base, &conf->com1);
55                 break;
56         case F71805F_SP2:
57                 res0 = find_resource(dev, PNP_IDX_IO0);
58                 init_uart8250(res0->base, &conf->com2);
59                 break;
60         }
61 }
62
63 static void f71805f_pnp_set_resources(device_t dev)
64 {
65         pnp_enter_conf_state(dev);
66         pnp_set_resources(dev);
67         pnp_exit_conf_state(dev);
68 }
69
70 static void f71805f_pnp_enable_resources(device_t dev)
71 {
72         pnp_enter_conf_state(dev);
73         pnp_enable_resources(dev);
74         pnp_exit_conf_state(dev);
75 }
76
77 static void f71805f_pnp_enable(device_t dev)
78 {
79         pnp_enter_conf_state(dev);
80         pnp_set_logical_device(dev);
81         (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
82         pnp_exit_conf_state(dev);
83 }
84
85 static struct device_operations ops = {
86         .read_resources   = pnp_read_resources,
87         .set_resources    = f71805f_pnp_set_resources,
88         .enable_resources = f71805f_pnp_enable_resources,
89         .enable           = f71805f_pnp_enable,
90         .init             = f71805f_init,
91 };
92
93 static struct pnp_info pnp_dev_info[] = {
94         /* TODO: Some of the 0x7f8 etc. values may not be correct. */
95         { &ops, F71805F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
96         { &ops, F71805F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
97         { &ops, F71805F_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
98         { &ops, F71805F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
99         { &ops, F71805F_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
100         { &ops, F71805F_GPIO, PNP_IRQ0, },
101         { &ops, F71805F_PME, },
102 };
103
104 static void enable_dev(device_t dev)
105 {
106         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
107 }
108
109 struct chip_operations superio_fintek_f71805f_ops = {
110         CHIP_NAME("Fintek F71805F Super I/O")
111         .enable_dev = enable_dev
112 };