src/superio/fintek/f71805f/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <arch/io.h>
  22 #include <device/device.h>
  23 #include <device/pnp.h>
  24 #include <console/console.h>
  25 #include <stdlib.h>
  26 #include <uart8250.h>
  27 #include "chip.h"
  28 #include "f71805f.h"
  29
  30 static void pnp_enter_conf_state(device_t dev)
  31 {
  32         outb(0x87, dev->path.pnp.port);
  33 }
  34
  35 static void pnp_exit_conf_state(device_t dev)
  36 {
  37         outb(0xaa, dev->path.pnp.port);
  38 }
  39
  40 static void f71805f_init(device_t dev)
  41 {
  42         struct superio_fintek_f71805f_config *conf = dev->chip_info;
  43         struct resource *res0;
  44
  45         if (!dev->enabled)
  46                 return;
  47
  48         switch(dev->path.pnp.device) {
  49         /* TODO: Might potentially need code for HWM or FDC etc. */
  50         case F71805F_SP1:
  51                 res0 = find_resource(dev, PNP_IDX_IO0);
  52                 init_uart8250(res0->base, &conf->com1);
  53                 break;
  54         case F71805F_SP2:
  55                 res0 = find_resource(dev, PNP_IDX_IO0);
  56                 init_uart8250(res0->base, &conf->com2);
  57                 break;
  58         }
  59 }
  60
  61 static void f71805f_pnp_set_resources(device_t dev)
  62 {
  63         pnp_enter_conf_state(dev);
  64         pnp_set_resources(dev);
  65         pnp_exit_conf_state(dev);
  66 }
  67
  68 static void f71805f_pnp_enable_resources(device_t dev)
  69 {
  70         pnp_enter_conf_state(dev);
  71         pnp_enable_resources(dev);
  72         pnp_exit_conf_state(dev);
  73 }
  74
  75 static void f71805f_pnp_enable(device_t dev)
  76 {
  77         pnp_enter_conf_state(dev);
  78         pnp_set_logical_device(dev);
  79         (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
  80         pnp_exit_conf_state(dev);
  81 }
  82
  83 static struct device_operations ops = {
  84         .read_resources   = pnp_read_resources,
  85         .set_resources    = f71805f_pnp_set_resources,
  86         .enable_resources = f71805f_pnp_enable_resources,
  87         .enable           = f71805f_pnp_enable,
  88         .init             = f71805f_init,
  89 };
  90
  91 static struct pnp_info pnp_dev_info[] = {
  92         /* TODO: Some of the 0x7f8 etc. values may not be correct. */
  93         { &ops, F71805F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
  94         { &ops, F71805F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
  95         { &ops, F71805F_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
  96         { &ops, F71805F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
  97         { &ops, F71805F_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
  98         { &ops, F71805F_GPIO, PNP_IRQ0, },
  99         { &ops, F71805F_PME, },
 100 };
 101
 102 static void enable_dev(device_t dev)
 103 {
 104         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 105 }
 106
 107 struct chip_operations superio_fintek_f71805f_ops = {
 108         CHIP_NAME("Fintek F71805F/FG Super I/O")
 109         .enable_dev = enable_dev
 110 };