2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* Based on other VIA SB code. */
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <console/console.h>
30 * No native mode. Interrupts from unconnected HDDs might occur if
31 * IRQ14/15 is used for PCI. Therefore no native mode support.
33 static void ide_init(struct device *dev)
35 struct southbridge_via_vt8237r_config *sb =
36 (struct southbridge_via_vt8237r_config *)dev->chip_info;
43 printk_info("%s IDE interface %s\n", "Primary",
44 sb->ide0_enable ? "enabled" : "disabled");
45 printk_info("%s IDE interface %s\n", "Secondary",
46 sb->ide1_enable ? "enabled" : "disabled");
47 enables = pci_read_config8(dev, IDE_CS) & ~0x3;
48 enables |= (sb->ide0_enable << 1) | sb->ide1_enable;
49 pci_write_config8(dev, IDE_CS, enables);
50 enables = pci_read_config8(dev, IDE_CS);
51 printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
53 /* Enable only compatibility mode. */
54 enables = pci_read_config8(dev, 0x09);
56 pci_write_config8(dev, 0x09, enables);
58 enables = pci_read_config8(dev, IDE_CONF_II);
60 pci_write_config8(dev, IDE_CONF_II, enables);
61 enables = pci_read_config8(dev, IDE_CONF_II);
62 printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
64 /* Enable prefetch buffers. */
65 enables = pci_read_config8(dev, IDE_CONF_I);
67 pci_write_config8(dev, IDE_CONF_I, enables);
69 /* Flush FIFOs at half. */
70 enables = pci_read_config8(dev, IDE_CONF_FIFO);
72 enables |= (1 << 2) | (1 << 0);
73 pci_write_config8(dev, IDE_CONF_FIFO, enables);
75 /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */
76 enables = pci_read_config8(dev, IDE_MISC_I);
78 enables |= (1 << 4) | (1 << 3);
79 pci_write_config8(dev, IDE_MISC_I, enables);
81 /* Use memory read multiple, Memory-Write-and-Invalidate. */
82 enables = pci_read_config8(dev, IDE_MISC_II);
84 enables |= (1 << 2) | (1 << 3);
85 pci_write_config8(dev, IDE_MISC_II, enables);
87 /* Force interrupts to use compat mode. */
88 pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
89 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
92 cablesel = pci_read_config32(dev, IDE_UDMA);
93 cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4));
94 cablesel |= (sb->ide0_80pin_cable << 28) |
95 (sb->ide0_80pin_cable << 20) |
96 (sb->ide1_80pin_cable << 12) |
97 (sb->ide1_80pin_cable << 4);
98 pci_write_config32(dev, IDE_UDMA, cablesel);
100 #if CONFIG_EPIA_VT8237R_INIT
101 /* Set PATA Output Drive Strength */
102 lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
103 PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
105 pci_write_config8(lpc_dev, 0x7C, 0x20);
109 static const struct device_operations ide_ops = {
110 .read_resources = pci_dev_read_resources,
111 .set_resources = pci_dev_set_resources,
112 .enable_resources = pci_dev_enable_resources,
118 static const struct pci_driver northbridge_driver __pci_driver = {
120 .vendor = PCI_VENDOR_ID_VIA,
121 .device = PCI_DEVICE_ID_VIA_82C586_1,