2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
5 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <device/pci_ids.h>
28 * Print an error, should it occur. If no error, just exit.
30 * @param host_status The data returned on the host status register after
31 * a transaction is processed.
32 * @param loops The number of times a transaction was attempted.
34 static void smbus_print_error(u8 host_status, int loops)
36 /* Check if there actually was an error. */
37 if ((host_status == 0x00 || host_status == 0x40 ||
38 host_status == 0x42) && (loops < SMBUS_TIMEOUT))
41 if (loops >= SMBUS_TIMEOUT)
42 print_err("SMBus timeout\r\n");
43 if (host_status & (1 << 4))
44 print_err("Interrupt/SMI# was Failed Bus Transaction\r\n");
45 if (host_status & (1 << 3))
46 print_err("Bus error\r\n");
47 if (host_status & (1 << 2))
48 print_err("Device error\r\n");
49 if (host_status & (1 << 1))
50 print_debug("Interrupt/SMI# completed successfully\r\n");
51 if (host_status & (1 << 0))
52 print_err("Host busy\r\n");
56 * Wait for the SMBus to become ready to process the next transaction.
58 static void smbus_wait_until_ready(void)
62 PRINT_DEBUG("Waiting until SMBus ready\r\n");
65 /* Yes, this is a mess, but it's the easiest way to do it. */
66 while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
69 smbus_print_error(inb(SMBHSTSTAT), loops);
73 * Reset and take ownership of the SMBus.
75 static void smbus_reset(void)
77 outb(HOST_RESET, SMBHSTSTAT);
79 /* Datasheet says we have to read it to take ownership of SMBus. */
82 PRINT_DEBUG("After reset status: ");
83 PRINT_DEBUG_HEX16(inb(SMBHSTSTAT));
88 * Read a byte from the SMBus.
90 * @param dimm The address location of the DIMM on the SMBus.
91 * @param offset The offset the data is located at.
93 u8 smbus_read_byte(u8 dimm, u8 offset)
98 PRINT_DEBUG_HEX16(dimm);
99 PRINT_DEBUG(" OFFSET ");
100 PRINT_DEBUG_HEX16(offset);
105 /* Clear host data port. */
106 outb(0x00, SMBHSTDAT0);
108 smbus_wait_until_ready();
110 /* Actual addr to reg format. */
113 outb(dimm, SMBXMITADD);
114 outb(offset, SMBHSTCMD);
116 /* Start transaction, byte data read. */
117 outb(0x48, SMBHSTCTL);
119 smbus_wait_until_ready();
121 val = inb(SMBHSTDAT0);
122 PRINT_DEBUG("Read: ");
123 PRINT_DEBUG_HEX16(val);
126 /* Probably don't have to do this, but it can't hurt. */
133 * Enable the smbus on vt8237r-based systems
135 void enable_smbus(void)
139 /* Power management controller */
140 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
141 PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
143 if (dev == PCI_DEV_INVALID)
144 die("Power management controller not found\r\n");
146 /* 7 = SMBus Clock from RTC 32.768KHz
147 * 5 = Internal PLL reset from susp
149 pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0);
152 pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG,
153 VT8237R_SMBUS_IO_BASE | 0x1);
155 /* SMBus Host Configuration, enable. */
156 pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01);
158 /* Make it work for I/O. */
159 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
163 /* Reset the internal pointer. */
168 * A fixup for some systems that need time for the SMBus to "warm up". This is
169 * needed on some VT823x based systems, where the SMBus spurts out bad data for
170 * a short time after power on. This has been seen on the VIA Epia series and
171 * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
172 * known-good data from a slot/address. Exits on either good data or a timeout.
174 * TODO: This should probably go into some global file, but one would need to
175 * be created just for it. If some other chip needs/wants it, we can
176 * worry about it then.
178 * @param ctrl The memory controller and SMBus addresses.
180 void smbus_fixup(const struct mem_controller *ctrl)
182 int i, ram_slots, current_slot = 0;
185 ram_slots = ARRAY_SIZE(ctrl->channel0);
187 print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
191 PRINT_DEBUG("Waiting for SMBus to warm up");
194 * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
195 * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
196 * VT8237R has only been seen on DDR and DDR2 based systems, so far.
198 for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
199 (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) {
201 if (current_slot > ram_slots)
204 result = smbus_read_byte(ctrl->channel0[current_slot],
210 if (i >= SMBUS_TIMEOUT)
211 print_err("SMBus timed out while warming up\r\n");
213 PRINT_DEBUG("Done\r\n");