2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
21 #define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
23 /* Static resources for the VT8237R southbridge */
25 #define VT8237R_APIC_ID 0x2
26 #define VT8237R_ACPI_IO_BASE 0x500
27 #define DEFAULT_PMBASE VT8237R_ACPI_IO_BASE
28 #define VT8237R_SMBUS_IO_BASE 0x400
29 /* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */
30 #define VT8237R_ACPI_IRQ 0x9
32 #define VT8237S_SPI_MEM_BASE 0xfed02000ULL
34 #define VT8237S_SPI_MEM_BASE 0xfed02000UL
36 #define VT8237R_HPET_ADDR 0xfed00000ULL
38 /* PMBASE FIXME mostly taken from ich7 */
40 #define WAK_STS (1 << 15)
41 #define PCIEXPWAK_STS (1 << 14)
42 #define PRBTNOR_STS (1 << 11)
43 #define RTC_STS (1 << 10)
44 #define PWRBTN_STS (1 << 8)
45 #define GBL_STS (1 << 5)
46 #define BM_STS (1 << 4)
47 #define TMROF_STS (1 << 0)
49 #define PCIEXPWAK_DIS (1 << 14)
50 #define RTC_EN (1 << 10)
51 #define PWRBTN_EN (1 << 8)
52 #define GBL_EN (1 << 5)
53 #define TMROF_EN (1 << 0)
55 #define SLP_EN (1 << 13)
56 #define SLP_TYP (7 << 10)
57 #define GBL_RLS (1 << 2)
58 #define BM_RLD (1 << 1)
59 #define SCI_EN (1 << 0)
70 #define IDE_CONF_I 0x41
71 #define IDE_CONF_II 0x42
72 #define IDE_CONF_FIFO 0x43
73 #define IDE_MISC_I 0x44
74 #define IDE_MISC_II 0x45
77 #define VT8237R_IDE0_80PIN_CABLE ((1UL<<28)|(1UL<<20))
78 #define VT8237R_IDE1_80PIN_CABLE ((1UL<<12)|(1UL<< 4))
79 #define VT8237R_IDE_CABLESEL_MASK (VT8237R_IDE0_80PIN_CABLE|VT8237R_IDE1_80PIN_CABLE)
82 #define VT8237R_PSON 0x82
83 #define VT8237R_POWER_WELL 0x94
84 #define VT8237R_SMBUS_IO_BASE_REG 0xd0
85 #define VT8237R_SMBUS_HOST_CONF 0xd2
87 #define SMBHSTSTAT (VT8237R_SMBUS_IO_BASE + 0x0)
88 #define SMBSLVSTAT (VT8237R_SMBUS_IO_BASE + 0x1)
89 #define SMBHSTCTL (VT8237R_SMBUS_IO_BASE + 0x2)
90 #define SMBHSTCMD (VT8237R_SMBUS_IO_BASE + 0x3)
91 #define SMBXMITADD (VT8237R_SMBUS_IO_BASE + 0x4)
92 #define SMBHSTDAT0 (VT8237R_SMBUS_IO_BASE + 0x5)
94 #define HOST_RESET 0xff
95 /* 1 in the 0 bit of SMBHSTADD states to READ. */
97 #define SMBUS_TIMEOUT (100 * 1000 * 10)
98 #define I2C_TRANS_CMD 0x40
99 #define CLOCK_SLAVE_ADDRESS 0x69
101 #if CONFIG_DEBUG_SMBUS
102 #define PRINT_DEBUG(x) print_debug(x)
103 #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
105 #define PRINT_DEBUG(x)
106 #define PRINT_DEBUG_HEX16(x)
109 #define SMBUS_DELAY() inb(0x80)
111 struct vt8237_network_rom {
134 #if defined(__GNUC__)
135 __attribute__ ((packed))
139 #define MAINBOARD_POWER_OFF 0
140 #define MAINBOARD_POWER_ON 1
141 #define MAINBOARD_POWER_KEEP 2
143 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
144 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
150 u8 smbus_read_byte(u8 dimm, u8 offset);
151 void enable_smbus(void);
152 void smbus_fixup(const struct mem_controller *ctrl);
153 // these are in vt8237_early_smbus.c - do they really belong there?
154 void vt8237_sb_enable_fid_vid(void);
155 void enable_rom_decode(void);
156 void vt8237_early_spi_init(void);
157 int vt8237_early_network_init(struct vt8237_network_rom *rom);
160 void writeback(device_t dev, u16 where, u8 what);
161 void dump_south(device_t dev);
162 u32 vt8237_ide_80pin_detect(device_t dev);