2 #include <console/console.h>
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_ids.h>
8 #include <pc80/mc146818rtc.h>
12 /* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C.
13 This is how the Award bios sets it up too.
14 epia can be more generous as it does not need to reserve interrupts for cardbus devices, but if changed then
15 make sure that ACPI dsdt is changed to suit.
22 IRQ 5 = available for PCI interrupts
23 IRQ 6 = floppy or availbale for PCI if floppy controller disabled
24 IRQ 7 = LPT or available if LPT port disabled
26 IRQ 9 = available for PCI interrupts
27 IRQ 10 = cardbus slot or available for PCI if no cardbus (ie epia)
28 IRQ 11 = cardbus slot or available for PCI if no cardbus (ie epia)
29 IRQ 12 = PS2 mouse (hardwired to 12)
30 IRQ 13 = legacy FPU interrupt
31 IRQ 14 = IDE controller 1
32 IRQ 15 = IDE controller 2
35 static const unsigned char pciIrqs[4] = { 5 , 9 , 9, 5 };
37 static const unsigned char usbPins[4] = { 'A','B','C','D'};
38 static const unsigned char enetPins[4] = { 'A','B','C','D'};
39 static const unsigned char slotPins[4] = { 'B','C','D','A'};
40 static const unsigned char firewirePins[4] = { 'B','C','D','A'};
41 static const unsigned char vt8235Pins[4] = { 'A','B','C','D'};
42 static const unsigned char vgaPins[4] = { 'A','B','C','D'};
43 static const unsigned char cbPins[4] = { 'A','B','C','D'};
44 static const unsigned char riserPins[4] = { 'A','B','C','D'};
47 static unsigned char *pin_to_irq(const unsigned char *pin)
49 static unsigned char Irqs[4];
51 for (i = 0 ; i < 4 ; i++)
52 Irqs[i] = pciIrqs[ pin[i] - 'A' ];
57 static void pci_routing_fixup(struct device *dev)
59 printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
61 /* set up PCI IRQ routing */
62 pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
63 pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
64 pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
67 // firewire built into southbridge
68 printk(BIOS_INFO, "setting firewire\n");
69 pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins));
71 // Standard usb components
72 printk(BIOS_INFO, "setting usb\n");
73 pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
75 // VT8235 + sound hardware
76 printk(BIOS_INFO, "setting vt8235\n");
77 pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins));
79 // Ethernet built into southbridge
80 printk(BIOS_INFO, "setting ethernet\n");
81 pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
84 printk(BIOS_INFO, "setting vga\n");
85 pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
88 printk(BIOS_INFO, "setting pci slot\n");
89 pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
92 printk(BIOS_INFO, "setting cardbus slot\n");
93 pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins));
95 // Via 2 slot riser card 2nd slot
96 printk(BIOS_INFO, "setting riser slot\n");
97 pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
99 printk(BIOS_SPEW, "%s: DONE\n", __func__);
103 * Set up the power management capabilities directly into ACPI mode. This
104 * avoids having to handle any System Management Interrupts (SMI's) which I
105 * can't figure out how to do !!!!
108 void setup_pm(device_t dev)
112 pci_write_config8(dev, 0x80, 0x20);
114 // Set ACPI base address to IO 0x4000
115 pci_write_config16(dev, 0x88, 0x0401);
118 pci_write_config8(dev, 0x82, 0x45);
120 // primary interupt channel
121 pci_write_config16(dev, 0x84, 0x30f2);
123 // throttle / stop clock control
124 pci_write_config8(dev, 0x8d, 0x18);
126 pci_write_config8(dev, 0x93, 0x88);
127 pci_write_config8(dev, 0x94, 0xb0);
128 pci_write_config8(dev, 0x95, 0xc0);
129 pci_write_config8(dev, 0x98, 0);
130 pci_write_config8(dev, 0x99, 0xea);
131 pci_write_config8(dev, 0xe4, 0x14);
132 pci_write_config8(dev, 0xe5, 0x08);
135 // Enable ACPI access (and setup like award)
136 pci_write_config8(dev, 0x81, 0x84);
141 outl(0xffffffff, 0x430);
149 outl(0xffff7fff, 0x448);
153 static void vt8235_init(struct device *dev)
155 unsigned char enables;
157 printk(BIOS_DEBUG, "vt8235 init\n");
159 // enable the internal I/O decode
160 enables = pci_read_config8(dev, 0x6C);
162 pci_write_config8(dev, 0x6C, enables);
164 // Map 4MB of FLASH into the address space
165 pci_write_config8(dev, 0x41, 0x7f);
167 // Set bit 6 of 0x40, because Award does it (IO recovery time)
168 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
169 // interrupts can be properly marked as level triggered.
170 enables = pci_read_config8(dev, 0x40);
172 pci_write_config8(dev, 0x40, enables);
174 // Set 0x42 to 0xf0 to match Award bios
175 enables = pci_read_config8(dev, 0x42);
177 pci_write_config8(dev, 0x42, enables);
179 /* Set 0x58 to 0x03 to match Award */
180 pci_write_config8(dev, 0x58, 0x03);
182 /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
183 enables = pci_read_config8(dev, 0x4f);
185 pci_write_config8(dev, 0x4f, enables);
187 // Set bit 3 of 0x4a, to match award (dummy pci request)
188 enables = pci_read_config8(dev, 0x4a);
190 pci_write_config8(dev, 0x4a, enables);
192 // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
193 enables = pci_read_config8(dev, 0x4f);
195 pci_write_config8(dev, 0x4f, enables);
197 // Set 0x58 to 0x03 to match Award
198 pci_write_config8(dev, 0x58, 0x03);
201 /* enable serial irq */
202 pci_write_config8(dev, 0x52, 0x9);
205 pci_write_config8(dev, 0x53, 0x00);
207 // Power management setup
210 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
211 pci_write_config8(dev, 0x40, 0x54);
217 /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this
218 device has a resource to set - so set a dummy one */
219 void vt8235_read_resources(device_t dev)
221 struct resource *res;
223 pci_dev_read_resources(dev);
225 res = new_resource(dev, 1);
228 res->limit = 0xffffUL;
229 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
231 res = new_resource(dev, 3); /* IOAPIC */
232 res->base = 0xfec00000;
233 res->size = 0x00001000;
234 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
237 void vt8235_set_resources(device_t dev)
239 struct resource *resource;
240 //resource = find_resource(dev,1);
241 //resource->flags |= IORESOURCE_STORED;
242 pci_dev_set_resources(dev);
245 void vt8235_enable_resources(device_t dev)
247 /* vt8235 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses)
248 however it does control the isa bus and so we need to manually call enable childrens resources on that bus */
249 pci_dev_enable_resources(dev);
250 enable_childrens_resources(dev);
254 static void southbridge_init(struct device *dev)
257 pci_routing_fixup(dev);
260 static struct device_operations vt8235_lpc_ops = {
261 .read_resources = vt8235_read_resources,
262 .set_resources = vt8235_set_resources,
263 .enable_resources = vt8235_enable_resources,
264 .init = &southbridge_init,
265 .scan_bus = scan_static_bus,
268 static const struct pci_driver lpc_driver __pci_driver = {
269 .ops = &vt8235_lpc_ops,
270 .vendor = PCI_VENDOR_ID_VIA,
271 .device = PCI_DEVICE_ID_VIA_8235,