1 #define SMBUS_IO_BASE 0xf00
12 #define SMBTRNSADD 0x9
13 #define SMBSLVDATA 0xa
14 #define SMLINK_PIN_CTL 0xe
15 #define SMBUS_PIN_CTL 0xf
17 /* Define register settings */
18 #define HOST_RESET 0xff
19 #define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
20 #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
23 #define SMBUS_TIMEOUT (100*1000*10)
25 #define I2C_TRANS_CMD 0x40
26 #define CLOCK_SLAVE_ADDRESS 0x69
28 static void enable_smbus(void)
34 /* Power management controller */
35 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
36 PCI_DEVICE_ID_VIA_8235), 0);
38 if (dev == PCI_DEV_INVALID) {
39 die("SMBUS controller not found\n");
42 // set IO base address to SMBUS_IO_BASE
43 pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
46 pci_write_config8(dev, 0xd2, (0x4 << 1) | 1);
48 /* make it work for I/O ...
50 pci_write_config16(dev, 4, 1);
52 /* FIX for half baud rate problem */
53 /* let clocks and the like settle */
54 /* as yet arbitrary count - 1000 is too little 5000 works */
55 for(i = 0 ; i < 5000 ; i++)
59 * The VT1211 serial port needs 48 mhz clock, on power up it is getting
60 * only 24 mhz, there is some mysterious device on the smbus that can
61 * fix this...this code below does it.
63 outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
64 outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
65 outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
66 outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD);
67 outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
70 c = inb(SMBUS_IO_BASE+SMBHSTSTAT);
77 static inline void smbus_delay(void)
82 static int smbus_wait_until_ready(void)
86 loops = SMBUS_TIMEOUT;
89 c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
94 c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
102 void smbus_reset(void)
104 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
105 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
106 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
107 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
109 smbus_wait_until_ready();
110 print_debug("After reset status ");
111 print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
117 static int smbus_wait_until_done(void)
121 loops = SMBUS_TIMEOUT;
125 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
133 static void smbus_print_error(unsigned char host_status_register)
136 print_err("smbus_error: ");
137 print_err_hex8(host_status_register);
139 if (host_status_register & (1 << 4)) {
140 print_err("Interrup/SMI# was Failed Bus Transaction\n");
142 if (host_status_register & (1 << 3)) {
143 print_err("Bus Error\n");
145 if (host_status_register & (1 << 2)) {
146 print_err("Device Error\n");
148 if (host_status_register & (1 << 1)) {
149 print_err("Interrupt/SMI# was Successful Completion\n");
151 if (host_status_register & (1 << 0)) {
152 print_err("Host Busy\n");
157 /* SMBus routines borrowed from VIA's Trident Driver */
158 /* this works, so I am not going to touch it for now -- rgm */
159 static unsigned char smbus_read_byte(unsigned char devAdr,
160 unsigned char bIndex)
164 unsigned char sts = 0;
166 /* clear host status */
167 outb(0xff, SMBUS_IO_BASE);
169 /* check SMBUS ready */
170 for ( i = 0; i < 0xFFFF; i++ )
171 if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
174 /* set host command */
175 outb(bIndex, SMBUS_IO_BASE+3);
177 /* set slave address */
178 outb(devAdr | 0x01, SMBUS_IO_BASE+4);
181 outb(0x48, SMBUS_IO_BASE+2);
183 /* SMBUS Wait Ready */
184 for ( i = 0; i < 0xFFFF; i++ )
185 if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 )
188 if ((sts & ~3) != 0) {
189 smbus_print_error(sts);
192 bData=inb(SMBUS_IO_BASE+5);
198 /* for reference, here is the fancier version which we will use at some
202 int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
204 unsigned char host_status_register;
209 smbus_wait_until_ready();
211 /* setup transaction */
212 /* disable interrupts */
213 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
214 /* set the device I'm talking too */
215 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
216 /* set the command/address... */
217 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
218 /* set up for a byte data read */
219 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
220 SMBUS_IO_BASE + SMBHSTCTL);
222 /* clear any lingering errors, so the transaction will run */
223 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
225 /* clear the data byte...*/
226 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
228 /* start the command */
229 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
230 SMBUS_IO_BASE + SMBHSTCTL);
232 /* poll for transaction completion */
233 smbus_wait_until_done();
235 host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
237 /* Ignore the In Use Status... */
238 host_status_register &= ~(1 << 6);
240 /* read results of transaction */
241 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
242 smbus_print_error(byte);
245 return host_status_register != 0x02;