1 #define SMBUS_IO_BASE 0xf00
12 #define SMBTRNSADD 0x9
13 #define SMBSLVDATA 0xa
14 #define SMLINK_PIN_CTL 0xe
15 #define SMBUS_PIN_CTL 0xf
17 /* Define register settings */
18 #define HOST_RESET 0xff
19 #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
22 #define SMBUS_TIMEOUT (100*1000*10)
24 #define I2C_TRANS_CMD 0x40
25 #define CLOCK_SLAVE_ADDRESS 0x69
27 static void enable_smbus(void)
33 /* Power management controller */
34 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
35 PCI_DEVICE_ID_VIA_8235), 0);
37 if (dev == PCI_DEV_INVALID) {
38 die("SMBUS controller not found\n");
41 // set IO base address to SMBUS_IO_BASE
42 pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
45 pci_write_config8(dev, 0xd2, (0x4 << 1) | 1);
47 /* make it work for I/O ...
49 pci_write_config16(dev, 4, 1);
51 /* FIX for half baud rate problem */
52 /* let clocks and the like settle */
53 /* as yet arbitrary count - 1000 is too little 5000 works */
54 for(i = 0 ; i < 5000 ; i++)
58 * The VT1211 serial port needs 48 mhz clock, on power up it is getting
59 * only 24 mhz, there is some mysterious device on the smbus that can
60 * fix this...this code below does it.
62 outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
63 outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
64 outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
65 outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD);
66 outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
69 c = inb(SMBUS_IO_BASE+SMBHSTSTAT);
76 static inline void smbus_delay(void)
81 static int smbus_wait_until_ready(void)
85 loops = SMBUS_TIMEOUT;
88 c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
93 c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
101 void smbus_reset(void)
103 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
104 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
105 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
106 outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
108 smbus_wait_until_ready();
109 print_debug("After reset status ");
110 print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
116 static int smbus_wait_until_done(void)
120 loops = SMBUS_TIMEOUT;
124 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
132 static void smbus_print_error(unsigned char host_status_register)
135 print_err("smbus_error: ");
136 print_err_hex8(host_status_register);
138 if (host_status_register & (1 << 4)) {
139 print_err("Interrup/SMI# was Failed Bus Transaction\n");
141 if (host_status_register & (1 << 3)) {
142 print_err("Bus Error\n");
144 if (host_status_register & (1 << 2)) {
145 print_err("Device Error\n");
147 if (host_status_register & (1 << 1)) {
148 print_err("Interrupt/SMI# was Successful Completion\n");
150 if (host_status_register & (1 << 0)) {
151 print_err("Host Busy\n");
156 /* SMBus routines borrowed from VIA's Trident Driver */
157 /* this works, so I am not going to touch it for now -- rgm */
158 static unsigned char smbus_read_byte(unsigned char devAdr,
159 unsigned char bIndex)
163 unsigned char sts = 0;
165 /* clear host status */
166 outb(0xff, SMBUS_IO_BASE);
168 /* check SMBUS ready */
169 for ( i = 0; i < 0xFFFF; i++ )
170 if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
173 /* set host command */
174 outb(bIndex, SMBUS_IO_BASE+3);
176 /* set slave address */
177 outb(devAdr | 0x01, SMBUS_IO_BASE+4);
180 outb(0x48, SMBUS_IO_BASE+2);
182 /* SMBUS Wait Ready */
183 for ( i = 0; i < 0xFFFF; i++ )
184 if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 )
187 if ((sts & ~3) != 0) {
188 smbus_print_error(sts);
191 bData=inb(SMBUS_IO_BASE+5);
197 /* for reference, here is the fancier version which we will use at some
201 int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
203 unsigned char host_status_register;
208 smbus_wait_until_ready();
210 /* setup transaction */
211 /* disable interrupts */
212 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
213 /* set the device I'm talking too */
214 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
215 /* set the command/address... */
216 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
217 /* set up for a byte data read */
218 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
219 SMBUS_IO_BASE + SMBHSTCTL);
221 /* clear any lingering errors, so the transaction will run */
222 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
224 /* clear the data byte...*/
225 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
227 /* start the command */
228 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
229 SMBUS_IO_BASE + SMBHSTCTL);
231 /* poll for transaction completion */
232 smbus_wait_until_done();
234 host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
236 /* Ignore the In Use Status... */
237 host_status_register &= ~(1 << 6);
239 /* read results of transaction */
240 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
241 smbus_print_error(byte);
244 return host_status_register != 0x02;