1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
4 #include <device/pci_ops.h>
5 #include <device/pci_ids.h>
7 #include <pc80/mc146818rtc.h>
13 void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
14 static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
15 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
16 static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
19 Our IDSEL mappings are as follows
20 PCI slot is AD31 (device 15) (00:14.0)
21 Southbridge is AD28 (device 12) (00:11.0)
23 static void pci_routing_fixup(struct device *dev)
26 printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
28 /* initialize PCI interupts - these assignments depend
29 on the PCB routing of PINTA-D
36 pci_write_config8(dev, 0x55, 0xb0);
37 pci_write_config8(dev, 0x56, 0xa5);
38 pci_write_config8(dev, 0x57, 0xc0);
41 // Standard southbridge components
42 printk(BIOS_INFO, "setting southbridge\n");
43 pci_assign_irqs(0, 0x11, southbridgeIrqs);
45 // Ethernet built into southbridge
46 printk(BIOS_INFO, "setting ethernet\n");
47 pci_assign_irqs(0, 0x12, enetIrqs);
50 printk(BIOS_INFO, "setting pci slot\n");
51 pci_assign_irqs(0, 0x14, slotIrqs);
52 printk(BIOS_INFO, "%s: DONE\n", __func__);
55 static void vt8231_init(struct device *dev)
57 unsigned char enables;
58 struct southbridge_via_vt8231_config *conf = dev->chip_info;
60 printk(BIOS_DEBUG, "vt8231 init\n");
62 // enable the internal I/O decode
63 enables = pci_read_config8(dev, 0x6C);
65 pci_write_config8(dev, 0x6C, enables);
67 // Map 4MB of FLASH into the address space
68 pci_write_config8(dev, 0x41, 0x7f);
70 // Set bit 6 of 0x40, because Award does it (IO recovery time)
71 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
72 // interrupts can be properly marked as level triggered.
73 enables = pci_read_config8(dev, 0x40);
74 pci_write_config8(dev, 0x40, enables);
76 // Set 0x42 to 0xf0 to match Award bios
77 enables = pci_read_config8(dev, 0x42);
79 pci_write_config8(dev, 0x42, enables);
81 // Set bit 3 of 0x4a, to match award (dummy pci request)
82 enables = pci_read_config8(dev, 0x4a);
84 pci_write_config8(dev, 0x4a, enables);
86 // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
87 enables = pci_read_config8(dev, 0x4f);
89 pci_write_config8(dev, 0x4f, enables);
91 // Set 0x58 to 0x03 to match Award
92 pci_write_config8(dev, 0x58, 0x03);
94 // enable the ethernet/RTC
96 enables = pci_read_config8(dev, 0x51);
98 pci_write_config8(dev, 0x51, enables);
101 // enable IDE, since Linux won't do it.
102 // First do some more things to devfn (17,0)
103 // note: this should already be cleared, according to the book.
104 enables = pci_read_config8(dev, 0x50);
105 printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables);
106 enables &= ~8; // need manifest constant here!
107 printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables);
108 pci_write_config8(dev, 0x50, enables);
110 // set default interrupt values (IDE)
111 enables = pci_read_config8(dev, 0x4c);
112 printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf);
113 // clear out whatever was there.
116 printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables);
117 pci_write_config8(dev, 0x4c, enables);
119 // set up the serial port interrupts.
120 // com2 to 3, com1 to 4
121 pci_write_config8(dev, 0x46, 0x04);
122 pci_write_config8(dev, 0x47, 0x03);
123 pci_write_config8(dev, 0x6e, 0x98);
125 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
126 pci_write_config8(dev, 0x40, 0x54);
133 void vt8231_read_resources(device_t dev)
135 struct resource *res;
137 pci_dev_read_resources(dev);
139 res = new_resource(dev, 1);
142 res->limit = 0xffffUL;
143 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
145 res = new_resource(dev, 3); /* IOAPIC */
146 res->base = 0xfec00000;
147 res->size = 0x00001000;
148 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
151 static void southbridge_init(struct device *dev)
154 pci_routing_fixup(dev);
157 static struct device_operations vt8231_lpc_ops = {
158 .read_resources = vt8231_read_resources,
159 .set_resources = pci_dev_set_resources,
160 .enable_resources = pci_dev_enable_resources,
161 .init = &southbridge_init,
162 .scan_bus = scan_static_bus,
167 static const struct pci_driver lpc_driver __pci_driver = {
168 .ops = &vt8231_lpc_ops,
169 .vendor = PCI_VENDOR_ID_VIA,
170 .device = PCI_DEVICE_ID_VIA_8231,