2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License v2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <device/device.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
23 #include <console/console.h>
26 static void mmconfig_set_resources(device_t dev)
28 struct resource *resource;
31 resource = find_resource(dev, K8T890_MMCONFIG_MBAR);
33 report_resource_stored(dev, resource, "<mmconfig>");
35 /* Remember this resource has been stored. */
36 resource->flags |= IORESOURCE_STORED;
37 pci_write_config8(dev, K8T890_MMCONFIG_MBAR,
38 (resource->base >> 28));
39 reg = pci_read_config8(dev, 0x60);
41 /* Enable MMCONFIG decoding. */
42 pci_write_config8(dev, 0x60, reg);
44 pci_dev_set_resources(dev);
47 static void apic_mmconfig_read_resources(device_t dev)
50 pci_dev_read_resources(dev);
52 res = new_resource(dev, 0x40);
53 /* NB APIC fixed to this address. */
54 res->base = K8T890_APIC_BASE;
56 res->limit = res->base + res->size - 1;
59 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
60 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
62 /* Add an MMCONFIG resource. */
63 res = new_resource(dev, K8T890_MMCONFIG_MBAR);
64 res->size = 256 * 1024 * 1024;
65 res->align = log2(res->size);
66 res->gran = log2(res->size);
67 res->limit = 0xffffffff; /* 4G */
68 res->flags = IORESOURCE_MEM;
71 static void traf_ctrl_enable(struct device *dev)
76 /* Enable D3F1-D3F3, no device2 redirect, enable just one device behind
77 * bridge device 2 and device 3).
79 pci_write_config8(dev, 0x60, 0x88);
81 /* Will enable MMCONFIG later. */
82 pci_write_config8(dev, 0x64, 0x23);
83 /* No extended RCRB Base Address. */
84 pci_write_config8(dev, 0x62, 0x00);
86 /* Offset80 ->95 bit 4 in 1 in Award. */
88 /* Enable APIC, to K8T890_APIC_BASE. */
89 pci_write_config8(dev, 0x41, 0x00);
90 pci_write_config8(dev, 0x40, 0x8c);
91 /* BT_INTR enable, APIC Nonshare Mode Enable. */
92 pci_write_config8(dev, 0x42, 0x5);
94 apic = (u32 *)K8T890_APIC_BASE;
96 /* Set APIC to FSB transported messages. */
99 apic[4] = (data & 0xFFFFFE) | 1;
104 apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
107 static const struct device_operations traf_ctrl_ops = {
108 .read_resources = apic_mmconfig_read_resources,
109 .set_resources = mmconfig_set_resources,
110 .enable_resources = pci_dev_enable_resources,
111 .enable = traf_ctrl_enable,
115 static const struct pci_driver northbridge_driver __pci_driver = {
116 .ops = &traf_ctrl_ops,
117 .vendor = PCI_VENDOR_ID_VIA,
118 .device = PCI_DEVICE_ID_VIA_K8T890CE_5,