src/southbridge/via/k8t890/k8t890_host_ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ops.h>
  23 #include <device/pci_ids.h>
  24 #include <console/console.h>
  25 #include "k8t890.h"
  26
  27 /* this may be later merged */
  28
  29 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
  30 static void host_ctrl_enable_k8t890(struct device *dev)
  31 {
  32         dump_south(dev);
  33
  34         /*
  35          * Bit 4 is reserved but set by AW. Set PCI to HT outstanding
  36          * requests to 3.
  37          */
  38         pci_write_config8(dev, 0xa0, 0x13);
  39
  40         /*
  41          * NVRAM I/O base at K8T890_NVRAM_IO_BASE
  42          * Some bits are set and reserved.
  43          */
  44         pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
  45
  46         /* enable NB NVRAM and enable non-posted PCI writes. */
  47         pci_write_config8(dev, 0xa1, 0x8f);
  48         /* Arbitration control, some bits are reserved. */
  49         pci_write_config8(dev, 0xa5, 0x3c);
  50
  51         /* Arbitration control 2 */
  52         pci_write_config8(dev, 0xa6, 0x80);
  53
  54         /* this will be possibly removed, when I figure out
  55          * if the ROM SIP is good, second reason is that the
  56          * unknown bits are AGP related, which are dummy on K8T890
  57          */
  58
  59         writeback(dev, 0xa0, 0x13);     /* Bit4 is reserved! */
  60         writeback(dev, 0xa1, 0x8e);     /* Some bits are reserved. */
  61         writeback(dev, 0xa2, 0x0e);     /* I/O NVRAM base 0xe00-0xeff disabled. */
  62         writeback(dev, 0xa3, 0x31);
  63         writeback(dev, 0xa4, 0x30);
  64
  65         writeback(dev, 0xa5, 0x3c);     /* Some bits reserved. */
  66         writeback(dev, 0xa6, 0x80);     /* Some bits reserved. */
  67         writeback(dev, 0xa7, 0x86);     /* Some bits reserved. */
  68         writeback(dev, 0xa8, 0x7f);     /* Some bits reserved. */
  69         writeback(dev, 0xa9, 0xcf);     /* Some bits reserved. */
  70         writeback(dev, 0xaa, 0x44);
  71         writeback(dev, 0xab, 0x22);
  72         writeback(dev, 0xac, 0x35);     /* Maybe bit0 is read-only? */
  73
  74         writeback(dev, 0xae, 0x22);
  75         writeback(dev, 0xaf, 0x40);
  76         /* b0 is missing. */
  77         writeback(dev, 0xb1, 0x13);
  78         writeback(dev, 0xb4, 0x02);     /* Some bits are reserved. */
  79         writeback(dev, 0xc0, 0x20);
  80         writeback(dev, 0xc1, 0xaa);
  81         writeback(dev, 0xc2, 0xaa);
  82         writeback(dev, 0xc3, 0x02);
  83         writeback(dev, 0xc4, 0x50);
  84         writeback(dev, 0xc5, 0x50);
  85
  86         dump_south(dev);
  87 }
  88
  89 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
  90 static void host_ctrl_enable_k8m890(struct device *dev) {
  91
  92         /*
  93          * Set PCI to HT outstanding requests to 03.
  94          * Bit 4 32 AGP ADS Read Outstanding Request Number
  95          */
  96         pci_write_config8(dev, 0xa0, 0x13);
  97
  98         /*
  99          * NVRAM I/O base at K8T890_NVRAM_IO_BASE
 100          */
 101
 102         pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
 103
 104         /* Enable NVRAM and enable non-posted PCI writes. */
 105         pci_write_config8(dev, 0xa1, 0x8f);
 106
 107         /* Arbitration control  */
 108         pci_write_config8(dev, 0xa5, 0x3c);
 109
 110         /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */
 111         pci_write_config8(dev, 0xa6, 0x83);
 112
 113 }
 114
 115 static const struct device_operations host_ctrl_ops_t = {
 116         .read_resources         = pci_dev_read_resources,
 117         .set_resources          = pci_dev_set_resources,
 118         .enable_resources       = pci_dev_enable_resources,
 119         .enable                 = host_ctrl_enable_k8t890,
 120         .ops_pci                = 0,
 121 };
 122
 123 static const struct device_operations host_ctrl_ops_m = {
 124         .read_resources         = pci_dev_read_resources,
 125         .set_resources          = pci_dev_set_resources,
 126         .enable_resources       = pci_dev_enable_resources,
 127         .enable                 = host_ctrl_enable_k8m890,
 128         .ops_pci                = 0,
 129 };
 130
 131 static const struct pci_driver northbridge_driver_t __pci_driver = {
 132         .ops    = &host_ctrl_ops_t,
 133         .vendor = PCI_VENDOR_ID_VIA,
 134         .device = PCI_DEVICE_ID_VIA_K8T890CE_2,
 135 };
 136
 137 static const struct pci_driver northbridge_driver_m __pci_driver = {
 138         .ops    = &host_ctrl_ops_m,
 139         .vendor = PCI_VENDOR_ID_VIA,
 140         .device = PCI_DEVICE_ID_VIA_K8M890CE_2,
 141 };