src/southbridge/via/k8t890/k8t890_host.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ops.h>
  23 #include <device/pci_ids.h>
  24 #include <console/console.h>
  25 #include "k8t890.h"
  26
  27 static void host_enable(struct device *dev)
  28 {
  29         /* Multiple function control */
  30         pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
  31
  32 }
  33
  34
  35 static void host_init(struct device *dev)
  36 {
  37         u8 reg;
  38
  39         /* AGP Capability Header Control */
  40         reg = pci_read_config8(dev, 0x4d);
  41         reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */
  42         pci_write_config8(dev, 0x4d, reg);
  43
  44         /* GD Output Stagger Delay */
  45         reg = pci_read_config8(dev, 0x42);
  46         reg |= 0x10; /* AD[31:16] with 1ns */
  47         pci_write_config8(dev, 0x42, reg);
  48
  49         /* AGP Control */
  50         reg = pci_read_config8(dev, 0xbc);
  51         reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */
  52         pci_write_config8(dev, 0xbc, reg);
  53
  54 }
  55
  56 static const struct device_operations host_ops_t = {
  57         .read_resources         = pci_dev_read_resources,
  58         .set_resources          = pci_dev_set_resources,
  59         .enable_resources       = pci_dev_enable_resources,
  60         .enable                 = host_enable,
  61         .ops_pci                = 0,
  62 };
  63
  64 static const struct device_operations host_ops_m = {
  65         .read_resources         = pci_dev_read_resources,
  66         .set_resources          = pci_dev_set_resources,
  67         .enable_resources       = pci_dev_enable_resources,
  68         .enable                 = host_enable,
  69         .init                   = host_init,
  70         .ops_pci                = 0,
  71 };
  72
  73 static const struct pci_driver northbridge_driver_t __pci_driver = {
  74         .ops    = &host_ops_t,
  75         .vendor = PCI_VENDOR_ID_VIA,
  76         .device = PCI_DEVICE_ID_VIA_K8T890CE_0,
  77 };
  78
  79 static const struct pci_driver northbridge_driver_m __pci_driver = {
  80         .ops    = &host_ops_m,
  81         .vendor = PCI_VENDOR_ID_VIA,
  82         .device = PCI_DEVICE_ID_VIA_K8M890CE_0,
  83 };