2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <device/device.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
23 #include <console/console.h>
24 #include <cpu/x86/msr.h>
25 #include <cpu/amd/mtrr.h>
26 #include <pc80/mc146818rtc.h>
30 static void dram_enable(struct device *dev)
36 * Enable Lowest Interrupt arbitration for APIC, enable NB APIC
37 * decoding, MSI support, no SMRAM, compatible SMM.
39 pci_write_config8(dev, 0x86, 0x39);
42 * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if
43 * memory is doing K8 the DMA from SB will fail if we have it wrong,
44 * AND even we have it here, we must later copy it to SB to make it work :/
47 /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for
50 pci_write_config8(dev, 0x80, 0xff);
51 /* For page D0000-DFFFF */
52 pci_write_config8(dev, 0x81, 0xff);
53 /* For page E0000-EFFFF */
54 pci_write_config8(dev, 0x82, 0xff);
55 pci_write_config8(dev, 0x83, 0x30);
58 reg = pci_read_config16(dev, 0x84);
60 pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg);
62 reg = pci_read_config16(dev, 0x88);
65 /* The Address Next to the Last Valid DRAM Address */
66 pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);
70 static void dram_enable_k8m890(struct device *dev)
74 /* enable VGA, so the bridges gets VGA_EN and resources are set */
75 pci_write_config8(dev, 0xa1, 0x80);
78 static struct resource *resmax;
80 static void get_memres(void *gp, struct device *dev, struct resource *res)
82 unsigned int *fbsize = (unsigned int *) gp;
83 uint64_t proposed_base = res->base + res->size - *fbsize;
85 printk(BIOS_DEBUG, "get_memres: res->base=%llx res->size=%llx %d %d %d\n",
86 res->base, res->size, (res->size > *fbsize),
87 (!(proposed_base & (*fbsize - 1))),
88 (proposed_base < ((uint64_t) 0xffffffff)));
90 /* if we fit and also align OK, and must be below 4GB */
91 if ((res->size > *fbsize) && (!(proposed_base & (*fbsize - 1))) &&
92 (proposed_base < ((uint64_t) 0xffffffff) )) {
95 #if CONFIG_WRITE_HIGH_TABLES==1
96 /* in arch/i386/boot/tables.c */
97 extern uint64_t high_tables_base, high_tables_size;
99 if ((high_tables_base) && ((high_tables_base > proposed_base) &&
100 (high_tables_base < (res->base + res->size)))) {
101 high_tables_base = proposed_base - high_tables_size;
102 printk(BIOS_DEBUG, "Moving the high_tables_base pointer to "
103 "new base %llx\n", high_tables_base);
112 k8m890_host_fb_size_get(void)
114 struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
115 PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
118 tmp = pci_read_config8(dev, 0xA1);
121 return 4 << (tmp & 7);
126 static void dram_init_fb(struct device *dev)
129 * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg:
130 * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB
131 * bits 3:0 BASE [31:28]
132 * reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access
135 uint64_t proposed_base;
136 unsigned int fbbits = 0;
141 ret = get_option(&fbbits, "videoram_size");
143 printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret);
147 if ((fbbits < 1) || (fbbits > 7)) {
148 printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n",
153 fbsize = 4 << (fbbits + 20);
156 search_global_resources(
157 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
158 get_memres, (void *) &fbsize);
160 /* no space for FB */
162 printk(BIOS_ERR, "VIA FB: no space for framebuffer in RAM\n");
166 proposed_base = resmax->base + resmax->size - fbsize;
167 resmax->size -= fbsize;
169 printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", 4 << fbbits);
171 /* Step 1: enable UMA but no FB */
172 pci_write_config8(dev, 0xa1, 0x80);
174 /* Step 2: enough is just the FB size, the CPU accessible address is not needed */
175 tmp = (fbbits << 4) | 0x80;
176 pci_write_config8(dev, 0xa1, tmp);
178 /* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */
181 static const struct device_operations dram_ops_t = {
182 .read_resources = pci_dev_read_resources,
183 .set_resources = pci_dev_set_resources,
184 .enable_resources = pci_dev_enable_resources,
185 .enable = dram_enable,
189 static const struct device_operations dram_ops_m = {
190 .read_resources = pci_dev_read_resources,
191 .set_resources = pci_dev_set_resources,
192 .enable_resources = pci_dev_enable_resources,
193 .enable = dram_enable_k8m890,
194 .init = dram_init_fb,
198 static const struct pci_driver northbridge_driver_t __pci_driver = {
200 .vendor = PCI_VENDOR_ID_VIA,
201 .device = PCI_DEVICE_ID_VIA_K8T890CE_3,
204 static const struct pci_driver northbridge_driver_m __pci_driver = {
206 .vendor = PCI_VENDOR_ID_VIA,
207 .device = PCI_DEVICE_ID_VIA_K8M890CE_3,