2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <string.h> /* for memset */
29 #include <pc80/vga_io.h>
37 chrome_vga_init(struct device *dev)
39 vga_sr_write(0x10, 0x01); /* unlock extended regs */
41 vga_sr_mask(0x1A, 0x02, 0x02); /* enable mmio */
43 vga_sr_mask(0x1A, 0x40, 0x40); /* Software Reset */
45 vga_cr_mask(0x6A, 0x00, 0xC8); /* Disable CRTC2 & Simultaneous */
47 /* Make sure that non of the primary VGA overflow registers are set */
48 vga_cr_write(0x33, 0x00);
49 vga_cr_write(0x35, 0x00);
50 vga_cr_mask(0x11, 0x00, 0x30);
52 vga_sr_mask(0x16, 0x00, 0x40); /* Wire CRT to CRTC1 */
53 vga_cr_mask(0x36, 0x00, 0x30); /* Power on CRT */
55 /* Disable Extended Display Mode */
56 vga_sr_mask(0x15, 0x00, 0x02);
58 /* Disable Wrap-around */
59 vga_sr_mask(0x15, 0x00, 0x20);
61 /* Disable Extended Mode memory access */
62 vga_sr_mask(0x1A, 0x00, 0x08);
64 /* Make sure that we only touch CRTC1s DAC */
65 vga_sr_mask(0x1A, 0x00, 0x01);
67 /* Set up power to the clocks/crtcs */
68 vga_sr_mask(0x19, 0x7F, 0x7F); /* enable clock gating for all. */
69 vga_sr_mask(0x1B, 0xC0, 0xC0); /* secondary clock according to pm */
70 vga_sr_mask(0x1B, 0x20, 0x30); /* primary clock is always on */
72 /* set everything according to PM/Engine idle state except pci dma */
73 vga_sr_write(0x2D, 0xFF); /* Power management control 1 */
74 vga_sr_write(0x2E, 0xFB); /* Power management control 2 */
75 vga_sr_write(0x3F, 0xFF); /* Power management control 3 */
77 /* now set up the engine clock. */
78 vga_sr_write(0x47, 0xB8);
79 vga_sr_write(0x48, 0x08);
80 vga_sr_write(0x49, 0x03);
82 /* trigger engine clock setting */
83 vga_sr_mask(0x40, 0x01, 0x01);
84 vga_sr_mask(0x40, 0, 0x01);
86 vga_cr_mask(0x30, 0x04, 0x04); /* Enable PowerNow in primary path */
87 vga_cr_mask(0x36, 0x01, 0x01); /* Enable PCI Power Management */
89 /* Power now indicators... */
90 vga_cr_write(0x41, 0xB9);
91 vga_cr_write(0x42, 0xB4);
92 /* could these be the CRTC2 power now indicators? */
93 vga_cr_write(0x9D, 0x80); /* Power Now Ending position enable */
94 vga_cr_write(0x9E, 0xB4); /* Power Now Control 3 */
96 /* primary fifo setting */
97 vga_sr_mask(0x16, 0x28, 0xBF); /* pthreshold: 160 */
98 vga_sr_write(0x17, 0x60); /* max depth: 194 */
99 vga_sr_mask(0x18, 0x0E, 0xBF); /* high priority threshold: 56 */
100 vga_sr_write(0x1C, 0x54); /* Fetch count */
102 vga_sr_write(0x20, 0x40); /* display queue typical arbiter control 0 */
103 vga_sr_write(0x21, 0x40); /* display queue typical arbiter control 1 */
104 vga_sr_mask(0x22, 0x14, 0x1F); /* display queue expire number */
106 /* Typical Arbiter Control */
107 vga_sr_mask(0x41, 0x40, 0xF0); /* Request threshold */
108 vga_sr_mask(0x42, 0x20, 0x20); /* Support Fetch Cycle with Length 2 */
110 vga_sr_write(0x50, 0x1F); /* AGP Control Register */
111 vga_sr_write(0x51, 0xF5); /* AGP FIFO Control 1 */
113 vga_cr_mask(0x33, 0x08, 0x08); /* Enable Prefetch Mode */
116 #endif /* CONFIG_VGA */
122 chrome_init(struct device *dev)
124 uint32_t fb_size, fb_address;
126 fb_size = k8m890_host_fb_size_get();
128 printk(BIOS_WARNING, "Chrome: Device has not been initialised in the"
129 " ramcontroller!\n");
133 fb_address = pci_read_config32(dev, 0x10);
136 printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n");
140 printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
141 fb_size, fb_address);
143 //k8m890_host_fb_direct_set(fb_address);
146 /* Now set up the VGA console */
147 vga_io_init(); /* Enable full IO access */
149 chrome_vga_init(dev);
153 #if CONFIG_CONSOLE_VGA == 1
157 printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n");
159 #if CONFIG_CONSOLE_VGA == 0
160 /* if we don't have console, at least print something... */
161 vga_line_write(0, "Chrome VGA Textmode initialized.");
164 #endif /* CONFIG_VGA */
167 static struct device_operations
169 .read_resources = pci_dev_read_resources,
170 .set_resources = pci_dev_set_resources,
171 .enable_resources = pci_dev_enable_resources,
177 static const struct pci_driver unichrome_driver __pci_driver = {